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| mcf5282 and mcf5216 coldfire ? microcontroller user?s manual devices supported: mcf5214 mcf5216 mcf5280 mcf5281 mcf5282 document number: mcf5282um rev. 3 2/2009
how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2009. all rights reserved. mcf5282um rev. 3 2/2009 overview coldfire core enhanced multiply-acc umulate unit (emac) cache static ram (sram) coldfire flash module (cfm) power management system control module (scm) clock module interrupt controller modules edge port module (eport) chip select module external interface module (eim) synchronous dram controller module dma controller module fast ethernet controller (fec) watchdog timer module programmable interrupt timer (pit) modules general purpose timer (gpt) modules flexcan module general purpose i/o module i 2 c module 3 4 5 7 8 9 10 11 12 13 15 16 17 18 19 24 6 20 25 26 21 23 22 dma timers queued serial peripheral interface module (qspi) uart modules 1 2 27 28 29 30 31 32 33 a chip configuration module (ccm) queued analog-to-digital converter (qadc) reset controller module debug support ieee 1149.1 test access port (jtag) mechanical data electrical characteristics memory map b revision history signal descriptions 14 ind index overview coldfire core enhanced multiply-accumulate unit (emac) cache static ram (sram) coldfire flash module (cfm) power management system control module (scm) clock module interrupt controller modules edge port module (eport) chip select module external interface module (eim) signal descriptions synchronous dram controller module dma controller module fast ethernet controller (fec) watchdog timer module programmable interrupt timer (pit) modules general purpose timer (gpt) modules flexcan module general purpose i/o module i 2 c module 3 4 5 7 8 9 10 11 12 13 14 15 16 17 18 19 24 6 20 25 26 21 23 22 dma timers queued serial peripheral interface module (qspi) uart modules 1 2 27 28 29 30 31 32 33 a chip configuration module (ccm) queued analog-to-digi tal converter (qadc) reset controller module debug support ieee 1149.1 test access port (jtag) mechanical data electrical characteristics memory map b revision history ind index freescale semiconductor v chapter 1 overview 1.1 key features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1.1 version 2 coldfire core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.1.1.1 cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.1.1.2 sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.1.1.3 flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 1.1.1.4 debug module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 1.1.2 system control module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 1.1.3 external interface module (eim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.1.4 chip select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.1.5 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.1.6 general input/output port s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.1.7 interrupt controllers (intc0/int c1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.1.8 sdram controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 1.1.9 test access port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 1.1.10 uart modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 1.1.11 dma timers (dtim0-dtim3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 1.1.12 general-purpose timers (gpta/ gptb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 1.1.13 periodic interrupt ti mers (pit0-pit3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 1.1.14 software watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 1.1.15 phase locked loop (pll) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 1.1.16 dma controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 1.1.17 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 1.2 mcf5282-specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 1.2.1 fast ethernet controller (fec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 1.2.2 flexcan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 1.2.3 i 2 c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 1.2.4 queued serial peripheral interfac e (qspi) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 1.2.5 queued analog-to-digital conver ter (qadc) . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 chapter 2 coldfire core 2.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.2 memory map/register descrip tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2.1 data registers (d0?d7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2.2 address registers (a0?a6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2.3 supervisor/user stack pointe rs (a7 and other_a7) . . . . . . . . . . . . . . . . . . . 2-5 2.2.4 condition code register (ccr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.2.5 program counter (pc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.2.6 cache control register (cacr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.2.7 access contro l registers (acr n ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.2.8 vector base register ( vbr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 vi freescale semiconductor 2.2.9 status register (sr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.2.10 memory base address r egisters (rambar, flas hbar) . . . . . . . . . . . . . . . 2-8 2.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 -9 2.3.1 version 2 coldfire microarchitectu re . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 2.3.2 instruction set architec ture (isa_a+) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.3.3 exception processing overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2.3.3.1 exception stack frame defi nition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.3.4 processor exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.3.4.1 access error exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.3.4.2 address error exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.3.4.3 illegal instruction excepti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.3.4.4 divide-by-zero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.3.4.5 privilege violation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.3.4.6 trace except ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.3.4.7 unimplemented line-a opc ode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.3.4.8 unimplemented line-f opc ode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.3.4.9 debug interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.3.4.10 rte and format error exc eption . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.3.4.11 trap instruction exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.3.4.12 unsupported instruction e xception . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.3.4.13 interrupt exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.3.4.14 fault-on-fault halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.3.4.15 reset exception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.3.5 instruction execution timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 2.3.5.1 timing assumptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 2.3.5.2 move instruction execution times . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 2.3.5.3 standard one oper and instruction execut ion times . . . . . . . . . . . . . 2-28 2.3.5.4 standard two operand inst ruction execution times . . . . . . . . . . . . . 2-28 2.3.5.5 miscellaneous inst ruction execution times . . . . . . . . . . . . . . . . . . . . 2-30 2.3.5.6 emac instruction execution times . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31 2.3.5.7 branch instruction execution times . . . . . . . . . . . . . . . . . . . . . . . . . . 2-32 chapter 3 enhanced multiply-accumulate unit (emac) 3.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1.1.1 introduction to the mac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 memory map/register definiti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2.1 mac status register (macsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.2.2 mask register (mask) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 3.2.3 accumulator registers (acc0?3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 3.2.4 accumulator extension regist ers (accext01, accext23) . . . . . . . . . . . . . . . . 3-7 3.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 -8 3.3.1 fractional operation m ode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.3.1.1 rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor vii 3.3.1.2 saving and restorin g the emac programming model . . . . . . . . . . . . 3-11 3.3.1.3 muls/mulu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3.3.1.4 scale factor in mac or ms ac instructions . . . . . . . . . . . . . . . . . . . . 3-12 3.3.2 emac instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 3.3.3 emac instruction execution time s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3.3.4 data representation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 3.3.5 mac opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 chapter 4 cache 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1.2 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.2 memory map/register definiti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2.1 cache control register (cacr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 4.2.2 access control register s (acr0, acr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 -7 4.3.1 interaction with other m odules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 4.3.2 memory reference attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.3.3 cache coherency and invalidation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.3.4 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 4.3.5 cache miss fetch algorithm/line fi lls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 chapter 5 static ram (sram) 5.1 sram features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.2 sram operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.3 sram programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.3.1 sram base address register (r ambar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.3.2 sram initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.3.3 sram initialization code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.3.4 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 chapter 6 coldfire flash module (cfm) 6.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 6.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2 6.3 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-4 6.3.1 cfm configuration field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6.3.2 flash base address register (flashbar) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5 6.3.3 cfm registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7 6.3.4 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 6.3.4.1 cfm configuration register (cfmcr) . . . . . . . . . . . . . . . . . . . . . . . . . 6-8 6.3.4.2 cfm clock divider regist er (cfmclkd) . . . . . . . . . . . . . . . . . . . . . . . 6-9 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 viii freescale semiconductor 6.3.4.3 cfm security register (c fmsec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10 6.3.4.4 cfm protection register (cfmprot) . . . . . . . . . . . . . . . . . . . . . . . . 6-12 6.3.4.5 cfm supervisor access register (cfmsacc) . . . . . . . . . . . . . . . . . 6-13 6.3.4.6 cfm data access register (cfmdacc) . . . . . . . . . . . . . . . . . . . . . . 6-14 6.3.4.7 cfm user status regist er (cfmustat) . . . . . . . . . . . . . . . . . . . . . . 6-15 6.3.4.8 cfm command register (cfm cmd) . . . . . . . . . . . . . . . . . . . . . . . . . 6-16 6.4 cfm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 -16 6.4.1 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17 6.4.2 write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17 6.4.3 program and erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17 6.4.3.1 setting the cfmclkd regist er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17 6.4.3.2 program, erase, and verify sequences . . . . . . . . . . . . . . . . . . . . . . . 6-18 6.4.3.3 flash valid commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-19 6.4.3.4 flash user mode illegal operations . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21 6.4.4 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21 6.4.5 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 6.5 flash security operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 6.5.1 back door access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 6.5.2 erase verify check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 6.6 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 6.7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 chapter 7 power management 7.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.2 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.2.1 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 7.2.2 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.2.3 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2 7.2.3.1 low-power interrupt control register (l picr) . . . . . . . . . . . . . . . . . . 7-2 7.2.3.2 low-power control register (lpcr) . . . . . . . . . . . . . . . . . . . . . . . . . . 7-4 7.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 -5 7.3.1 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.3.1.1 run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-5 7.3.1.2 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.3.1.3 doze mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.3.1.4 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.3.1.5 peripheral shut down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.3.2 peripheral behavior in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.3.2.1 coldfire core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.3.2.2 static random -access memory (sram) . . . . . . . . . . . . . . . . . . . . . . . 7-6 7.3.2.3 flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7.3.2.4 system control module (scm ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7.3.2.5 sdram controll er (sdramc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7.3.2.6 chip select module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor ix 7.3.2.7 dma controller (d mac0?dma3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-7 7.3.2.8 uart modules (uart0, u art1, and uart2) . . . . . . . . . . . . . . . . . . 7-8 7.3.2.9 i2c module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 7.3.2.10 queued serial peripheral interface (qspi) . . . . . . . . . . . . . . . . . . . . 7-8 7.3.2.11 dma timers (dmat0?dmat3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-8 7.3.2.12 interrupt controllers (intc0, intc1) . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 7.3.2.13 fast ethernet controller (f ec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 7.3.2.14 i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 7.3.2.15 reset controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 7.3.2.16 chip configuration module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-9 7.3.2.17 clock module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 7.3.2.18 edge port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 7.3.2.19 watchdog ti mer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-10 7.3.2.20 programmable interrupt timers (pit0, pit1, pit2 and pit3) . . . . . 7-10 7.3.2.21 queued analog-to- digital converter (qadc) . . . . . . . . . . . . . . . . . . 7-11 7.3.2.22 general purpose timers (gpta and gptb) . . . . . . . . . . . . . . . . . . 7-11 7.3.2.23 flexcan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-11 7.3.2.24 coldfire flash module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 7.3.2.25 bdm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 7.3.2.26 jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-13 7.3.3 summary of peripheral state during low-po wer modes . . . . . . . . . . . . . . . . 7-13 chapter 8 system control module (scm) 8.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-1 8.3 memory map and register defi nition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-2 8.4 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 -2 8.4.1 internal peripheral system base address r egister (ipsbar) . . . . . . . . . . . . . 8-2 8.4.2 memory base address register (rambar) . . . . . . . . . . . . . . . . . . . . . . . . . . 8-3 8.4.3 core reset status register (cr sr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 8.4.4 core watchdog control register (cwcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5 8.4.5 core watchdog service register (cwsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 8.5 internal bus arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-7 8.5.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8 8.5.2 arbitration algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 8.5.2.1 round-robin mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 8.5.2.2 fixed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 8.5.3 bus master park register (mpa rk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-9 8.6 system access control unit (sacu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 8.6.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-11 8.6.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 8.6.3 memory map/register de finition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12 8.6.3.1 master privilege register (mpr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-13 8.6.3.2 peripheral access co ntrol registers (pacr0?pacr8) . . . . . . . . . . . 8-13 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 x freescale semiconductor 8.6.3.3 grouped peri pheral access control registers (gpacr0 & gpacr1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15 chapter 9 clock module 9.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 -1 9.2.1 normal pll mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.2.2 1:1 pll mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.2.3 external clock mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 9.3 low-power mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-2 9.5 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 9.5.1 extal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-4 9.5.2 xtal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 9.5.3 clkout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 9.5.4 clkmod[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 9.5.5 rstout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 9.6 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 9.6.1 module memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-5 9.6.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-6 9.6.2.1 synthesizer control regist er (syncr) . . . . . . . . . . . . . . . . . . . . . . . . 9-6 9.6.2.2 synthesizer status regist er (synsr) . . . . . . . . . . . . . . . . . . . . . . . . . 9-8 9.7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 0 9.7.1 system clock modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-10 9.7.2 clock operation during reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 9.7.3 system clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 9.7.4 pll operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-11 9.7.4.1 phase and frequency detector (pfd) . . . . . . . . . . . . . . . . . . . . . . . . 9-12 9.7.4.2 charge pump/loop filt er . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 9.7.4.3 voltage control ou tput (vco) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 9.7.4.4 multiplication factor divi der (mfd) . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 9.7.4.5 pll lock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-13 9.7.4.6 pll loss of lock conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 9.7.4.7 pll loss of lock reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 9.7.4.8 loss of clock detect ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 9.7.4.9 loss of clock reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 9.7.4.10 alternate clock sele ction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 9.7.4.11 loss of clock in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16 chapter 10 interrupt cont roller modules 10.1 68k/coldfire interrupt arch itecture overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-1 10.1.1 interrupt controller theory of op eration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-2 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor xi 10.1.1.1 interrupt recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-3 10.1.1.2 interrupt prioritiza tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.1.1.3 interrupt vector determination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.2 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-4 10.3 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 -6 10.3.1 interrupt pending registers (i prhn, iprln) . . . . . . . . . . . . . . . . . . . . . . . . . 10-6 10.3.2 interrupt mask register (imrhn , imrln) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7 10.3.3 interrupt force registers (i ntfrchn, intfrcln) . . . . . . . . . . . . . . . . . . . . 10-9 10.3.4 interrupt request level regist er (irlrn) . . . . . . . . . . . . . . . . . . . . . . . . . . 10-11 10.3.5 interrupt acknowledge level and priority register (iacklprn) . . . . . . . . . 10-11 10.3.6 interrupt control register (i crnx, (x = 1, 2,..., 63)) . . . . . . . . . . . . . . . . . . . 10-12 10.3.6.1 interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-13 10.3.7 software and level n ia ck registers (swi ackr, l1iack?l7iack) . . . . . 10-16 10.4 prioritization between inte rrupt controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17 10.5 low-power wakeup operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-17 chapter 11 edge port module (eport) 11.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.2 low-power mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-1 11.3 interrupt/general-purpose i/o pin de scriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2 11.4 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.4.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.4.2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3 11.4.2.1 eport pin assignment register (eppar) . . . . . . . . . . . . . . . . . . . 11-3 11.4.2.2 eport data direction re gister (epddr) . . . . . . . . . . . . . . . . . . . . 11-4 11.4.2.3 edge port interrupt e nable register (epier) . . . . . . . . . . . . . . . . . . 11-5 11.4.2.4 edge port data register (epdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-5 11.4.2.5 edge port pin data regi ster (eppdr) . . . . . . . . . . . . . . . . . . . . . . . 11-6 11.4.2.6 edge port flag r egister (epfr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-6 chapter 12 chip select module 12.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.2 chip select module signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-1 12.3 chip select operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 -3 12.3.1 general chip select operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 12.3.1.1 8-, 16-, and 32-bit po rt sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-3 12.3.1.2 external boot chip sele ct operation . . . . . . . . . . . . . . . . . . . . . . . . 12-4 12.4 chip select registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 -4 12.4.1 chip select module regi sters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-6 12.4.1.1 chip select address registers (csar0?csar 6) . . . . . . . . . . . . . . 12-6 12.4.1.2 chip select mask regi sters (csmr0?csmr6) . . . . . . . . . . . . . . . . 12-6 12.4.1.3 chip select control registers (cscr0?cscr6) . . . . . . . . . . . . . . . 12-7 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 xii freescale semiconductor chapter 13 external interface module (eim) 13.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.2 bus and control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 13.3 bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.4 data transfer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-2 13.4.1 bus cycle execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3 13.4.2 data transfer cycl e states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4 13.4.3 read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-6 13.4.4 write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-7 13.4.5 fast termination cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8 13.4.6 back-to-back bus cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9 13.4.7 burst cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10 13.4.7.1 line transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10 13.4.7.2 line read bus cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-10 13.4.7.3 line write bu s cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12 13.5 misaligned operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14 chapter 14 signal descriptions 14.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 14.1.1 single-chip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-17 14.1.2 external boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18 14.2 external signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18 14.2.1 external interface module (eim ) signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-18 14.2.1.1 address bus (a[23: 0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19 14.2.1.2 data bus (d[31:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19 14.2.1.3 byte strobes (bs [3:0] ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19 14.2.1.4 output enable (oe ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19 14.2.1.5 transfer acknowledge (ta ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-19 14.2.1.6 transfer error acknowledge (tea ) . . . . . . . . . . . . . . . . . . . . . . . . . 14-20 14.2.1.7 read/write (r/w ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-20 14.2.1.8 transfer size(siz[1:0] ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-20 14.2.1.9 transfer start (ts ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-20 14.2.1.10 transfer in progress (tip ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-21 14.2.1.11 chip selects (cs [6:0] ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-21 14.2.2 sdram controller signal s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-21 14.2.2.1 sdram row address strobe (sras ) . . . . . . . . . . . . . . . . . . . . . . 14-21 14.2.2.2 sdram column address strobe (scas ) . . . . . . . . . . . . . . . . . . . 14-21 14.2.2.3 sdram write enable (dramw ) . . . . . . . . . . . . . . . . . . . . . . . . . . 14-21 14.2.2.4 sdram bank selects (sdram_cs [1:0] ) . . . . . . . . . . . . . . . . . . . 14-21 14.2.2.5 sdram clock enabl e (scke) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22 14.2.3 clock and reset signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22 14.2.3.1 reset in (rsti ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor xiii 14.2.3.2 reset out (rsto) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22 14.2.3.3 extal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22 14.2.3.4 xtal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22 14.2.3.5 clock output (clkout) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22 14.2.4 chip configurati on signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22 14.2.4.1 rcon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22 14.2.4.2 clkmod[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-22 14.2.5 external interrupt signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-23 14.2.5.1 external interrupts (irq [7:1] ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-23 14.2.6 ethernet module signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-23 14.2.6.1 management data (emdio) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-23 14.2.6.2 management data clock (em dc) . . . . . . . . . . . . . . . . . . . . . . . . . 14-23 14.2.6.3 transmit clock (etx clk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-23 14.2.6.4 transmit enable (e txen) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-23 14.2.6.5 transmit data 0 (etxd0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-23 14.2.6.6 collision (ecol) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-24 14.2.6.7 receive clock (erxclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-24 14.2.6.8 receive data valid (erxdv) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-24 14.2.6.9 receive data 0 (e rxd0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-24 14.2.6.10 carrier receive sense ( ecrs) . . . . . . . . . . . . . . . . . . . . . . . . . . 14-24 14.2.6.11 transmit data 1?3 (etxd[3: 1]) . . . . . . . . . . . . . . . . . . . . . . . . . . 14-24 14.2.6.12 transmit erro r (etxer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-24 14.2.6.13 receive data 1? 3 (erxd[3:1]) . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-24 14.2.6.14 receive error (erxer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-25 14.2.7 queued serial peripheral interface (qspi) signa ls . . . . . . . . . . . . . . . . . . . 14-25 14.2.7.1 qspi synchronous seri al output (qspi_dout) . . . . . . . . . . . . . . 14-25 14.2.7.2 qspi synchronous seri al data input (qspi_din) . . . . . . . . . . . . . 14-25 14.2.7.3 qspi serial clock (qspi_clk) . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-25 14.2.7.4 qspi chip selects (qspi_cs[3:0]) . . . . . . . . . . . . . . . . . . . . . . . . 14-25 14.2.8 flexcan signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-25 14.2.8.1 flexcan transmit (cantx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-25 14.2.8.2 flexcan receive (canrx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-25 14.2.9 i 2 c signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26 14.2.9.1 serial clock (scl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26 14.2.9.2 serial data (sda) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26 14.2.10uart module signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26 14.2.10.1 transmit serial data output (utxd[2:0]) . . . . . . . . . . . . . . . . . . . 14-26 14.2.10.2 receive serial data input (urxd[2:0]) . . . . . . . . . . . . . . . . . . . . 14-26 14.2.10.3 clear-to-send (ucts [1:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-26 14.2.10.4 request-to-send (urts [1:0] ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-27 14.2.11general purpose timer signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-27 14.2.11.1 gpta[3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-27 14.2.11.2 gptb[3:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-27 14.2.11.3 external clock input (synca/syncb) . . . . . . . . . . . . . . . . . . . . 14-27 14.2.12dma timer signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-27 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 xiv freescale semiconductor 14.2.12.1 dma timer 0 input (dtin0 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-27 14.2.12.2 dma timer 0 output (d tout0) . . . . . . . . . . . . . . . . . . . . . . . . . . 14-27 14.2.12.3 dma timer 1 input (dtin1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-27 14.2.12.4 dma timer 1 output (d tout1) . . . . . . . . . . . . . . . . . . . . . . . . . . 14-28 14.2.12.5 dma timer 2 input (dtin2 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-28 14.2.12.6 dma timer 2 output (d tout2) . . . . . . . . . . . . . . . . . . . . . . . . . . 14-28 14.2.12.7 dma timer 3 input (dtin3 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-28 14.2.12.8 dma timer 3 output (d tout3) . . . . . . . . . . . . . . . . . . . . . . . . . . 14-28 14.2.13analog-to-digital converter si gnals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-28 14.2.13.1 qadc analog input (an0/anw) . . . . . . . . . . . . . . . . . . . . . . . . . 14-28 14.2.13.2 qadc analog input (an1/anx) . . . . . . . . . . . . . . . . . . . . . . . . . . 14-28 14.2.13.3 qadc analog input (an2/any) . . . . . . . . . . . . . . . . . . . . . . . . . . 14-29 14.2.13.4 qadc analog input (an3/anz) . . . . . . . . . . . . . . . . . . . . . . . . . . 14-29 14.2.13.5 qadc analog input (an52/ma0) . . . . . . . . . . . . . . . . . . . . . . . . . 14-29 14.2.13.6 qadc analog input (an53/ma1) . . . . . . . . . . . . . . . . . . . . . . . . . 14-29 14.2.13.7 qadc analog input (an55/trig1) . . . . . . . . . . . . . . . . . . . . . . . 14-29 14.2.13.8 qadc analog input (an56/trig2) . . . . . . . . . . . . . . . . . . . . . . . 14-29 14.2.14debug support signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-29 14.2.14.1 jtag_en . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-29 14.2.14.2 development serial clock/test reset (dsclk/trst ) . . . . . . . . 14-30 14.2.14.3 breakpoint/tes t mode select (bkpt /tms) . . . . . . . . . . . . . . . . . 14-30 14.2.14.4 development se rial input/test data (dsi/tdi) . . . . . . . . . . . . . . . 14-30 14.2.14.5 development serial output/test data (dso/t do) . . . . . . . . . . . 14-30 14.2.14.6 test clock (tclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-30 14.2.14.7 debug data (ddata[3:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-31 14.2.14.8 processor status out puts (pst[3:0]) . . . . . . . . . . . . . . . . . . . . . . 14-31 14.2.15test signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-31 14.2.15.1 test (test) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-31 14.2.16power and reference signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-32 14.2.16.1 qadc analog reference (vrh, vrl) . . . . . . . . . . . . . . . . . . . . . 14-32 14.2.16.2 qadc analog supply (vdda, vssa) . . . . . . . . . . . . . . . . . . . . . 14-32 14.2.16.3 pll analog supply (vddp ll, vsspll) . . . . . . . . . . . . . . . . . . . 14-32 14.2.16.4 qadc positive supply (vddh) . . . . . . . . . . . . . . . . . . . . . . . . . . 14-32 14.2.16.5 power for flash erase/ program (vpp) . . . . . . . . . . . . . . . . . . . . . 14-32 14.2.16.6 power and ground for flash array (vddf, vssf) . . . . . . . . . . . 14-32 14.2.16.7 standby power (vstby) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-32 14.2.16.8 positive supply (vdd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-32 14.2.16.9 ground (vss) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-32 chapter 15 synchronous dram controller module 15.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.1.1 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.1.2 block diagram and major compo nents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-1 15.2 sdram controller oper ation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-3 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor xv 15.2.1 dram controller signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 15.2.2 memory map for sdramc registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 15.2.2.1 dram control register (dcr ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-4 15.2.2.2 dram address and cont rol registers (da cr0/dacr1) . . . . . . . . 15-6 15.2.2.3 dram controller mask registers (dmr 0/dmr1) . . . . . . . . . . . . . . 15-8 15.2.3 general synchronous operation guidelines . . . . . . . . . . . . . . . . . . . . . . . . . 15-9 15.2.3.1 address multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-9 15.2.3.2 sdram byte strobe connec tions . . . . . . . . . . . . . . . . . . . . . . . . . 15-13 15.2.3.3 interfacing example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13 15.2.3.4 burst page mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-13 15.2.3.5 auto-refresh operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-15 15.2.3.6 self-refresh operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-16 15.2.4 initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-17 15.2.4.1 mode register sett ings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-18 15.3 sdram example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-18 15.3.1 sdram interface configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-20 15.3.2 dcr initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-20 15.3.3 dacr initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-20 15.3.4 dmr initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-22 15.3.5 mode register initializa tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-23 15.3.6 initialization code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-23 chapter 16 dma controller module 16.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-1 16.1.1 dma module features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 16.2 dma request control (dmareqc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-2 16.3 dma transfer overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4 16.4 dma controller module programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4 16.4.1 source address registers (sar 0?sar3) . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5 16.4.2 destination address re gisters (dar0?dar3) . . . . . . . . . . . . . . . . . . . . . . . . 16-6 16.4.3 byte count registers (bcr0?bcr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7 16.4.4 dma control registers (dcr0?dcr 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7 16.4.5 dma status registers (dsr0?d sr3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-10 16.5 dma controller module func tional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-11 16.5.1 transfer requests (cycle-steal and continuo us modes) . . . . . . . . . . . . . . . 16-11 16.5.2 data transfer modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12 16.5.2.1 dual-address transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12 16.5.3 channel initialization and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12 16.5.3.1 channel prioritizati on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-12 16.5.3.2 programming the dma cont roller module . . . . . . . . . . . . . . . . . . . 16-12 16.5.4 data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13 16.5.4.1 auto-alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-13 16.5.4.2 bandwidth control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14 16.5.5 termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-14 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 xvi freescale semiconductor chapter 17 fast ethernet controller (fec) 17.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.1.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-1 17.1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-3 17.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 -4 17.2.1 full and half duplex operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.2.2 interface options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.2.2.1 10 mbps and 100 mbps mii interface . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.2.2.2 10 mpbs 7-wire in terface operation . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.2.3 address recognition options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.2.4 internal loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-4 17.3 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5 17.4 memory map/register definiti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-5 17.4.1 mib block counters memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-7 17.4.2 ethernet interrupt event register (eir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-9 17.4.3 interrupt mask register (eimr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-10 17.4.4 receive descriptor active regi ster (rdar) . . . . . . . . . . . . . . . . . . . . . . . . . 17-11 17.4.5 transmit descriptor active register (tdar) . . . . . . . . . . . . . . . . . . . . . . . . . 17-12 17.4.6 ethernet control register (ecr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-12 17.4.7 mii management frame r egister (mmfr) . . . . . . . . . . . . . . . . . . . . . . . . . . 17-13 17.4.8 mii speed control regist er (mscr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-15 17.4.9 mib control register (mibc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16 17.4.10receive control register (rcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-16 17.4.11transmit control register (tcr ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-17 17.4.12physical address lower register (palr) . . . . . . . . . . . . . . . . . . . . . . . . . . 17-18 17.4.13physical address upper register (paur) . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19 17.4.14opcode/pause duration register (opd) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-19 17.4.15descriptor individual upper address register (iaur) . . . . . . . . . . . . . . . . . 17-20 17.4.16descriptor individual lower address register (ialr) . . . . . . . . . . . . . . . . . 17-20 17.4.17descriptor group upper address register (gau r) . . . . . . . . . . . . . . . . . . 17-21 17.4.18descriptor group lower address register (gal r) . . . . . . . . . . . . . . . . . . . 17-21 17.4.19transmit fifo wate rmark register (tfwr) . . . . . . . . . . . . . . . . . . . . . . . . 17-22 17.4.20fifo receive bound register (frbr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-22 17.4.21fifo receive start re gister (frsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-23 17.4.22receive descriptor ring start register (erds r) . . . . . . . . . . . . . . . . . . . . 17-23 17.4.23transmit buffer descripto r ring start registers (etsdr) . . . . . . . . . . . . . 17-24 17.4.24receive buffer size register (emrbr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-24 17.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 5 17.5.1 buffer descriptors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-25 17.5.1.1 driver/dma oper ation with buffer descriptors . . . . . . . . . . . . . . . . 17-25 17.5.1.2 ethernet receive buffer descriptor (rx bd) . . . . . . . . . . . . . . . . . . 17-27 17.5.1.3 ethernet transmit buffer descriptor (txb d) . . . . . . . . . . . . . . . . . . 17-29 17.5.2 initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-30 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor xvii 17.5.2.1 hardware controlled initia lization . . . . . . . . . . . . . . . . . . . . . . . . . . 17-30 17.5.3 user initialization (prior to setting ecr[ether_ en]) . . . . . . . . . . . . . . . . . 17-31 17.5.4 microcontroller initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-32 17.5.5 user initialization (after setting ecr[ether_en]) . . . . . . . . . . . . . . . . . . . 17-32 17.5.6 network interface options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-32 17.5.7 fec frame transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-33 17.5.7.1 duplicate frame transmi ssion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-34 17.5.8 fec frame reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-35 17.5.9 ethernet address recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-35 17.5.10hash algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-38 17.5.11full duplex flow contro l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-41 17.5.12inter-packet gap (ipg) time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-42 17.5.13collision managing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-42 17.5.14mii internal and external loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-42 17.5.15ethernet error-managing procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-42 17.5.15.1 transmission errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-43 17.5.15.2 reception errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-43 chapter 18 watchdog timer module 18.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 18.2 low-power mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-1 18.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 18.4 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 18.5 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 18.5.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-2 18.5.2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 18.5.2.1 watchdog control register (wcr) . . . . . . . . . . . . . . . . . . . . . . . . . . 18-3 18.5.2.2 watchdog modulus register (wmr) . . . . . . . . . . . . . . . . . . . . . . . . 18-4 18.5.2.3 watchdog count r egister (wcntr) . . . . . . . . . . . . . . . . . . . . . . . . 18-5 18.5.2.4 watchdog service register (wsr) . . . . . . . . . . . . . . . . . . . . . . . . . 18-5 chapter 19 programmable interrup t timers (pit0?pit3) 19.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 19.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 19.1.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 19.1.3 low-power mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-1 19.2 memory map/register definiti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-2 19.2.1 pit control and st atus register (pcsr n ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-3 19.2.2 pit modulus register (pmr n ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5 19.2.3 pit count register (pcntr n ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-5 19.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 -6 19.3.1 set-and-forget timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 xviii freescale semiconductor 19.3.2 free-running timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-6 19.3.3 timeout specificatio ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7 19.3.4 interrupt operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19-7 chapter 20 general purpose timer mo dules (gpta and gptb) 20.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 20.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-2 20.3 low-power mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3 20.4 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3 20.4.1 gptn[2:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3 20.4.2 gptn3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-3 20.4.3 syncn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4 20.5 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-4 20.5.1 gpt input capture/output compare select register (gptio s) . . . . . . . . . . 20-5 20.5.2 gpt compare force register (gpcforc) . . . . . . . . . . . . . . . . . . . . . . . . . . 20-6 20.5.3 gpt output compare 3 mask register (gptoc3m) . . . . . . . . . . . . . . . . . . . 20-6 20.5.4 gpt output compare 3 data register (gptoc3d) . . . . . . . . . . . . . . . . . . . 20-7 20.5.5 gpt counter register (gptcnt) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-7 20.5.6 gpt system control register 1 (gptscr1) . . . . . . . . . . . . . . . . . . . . . . . . . 20-8 20.5.7 gpt toggle-on-overflow register (gpttov) . . . . . . . . . . . . . . . . . . . . . . . . 20-9 20.5.8 gpt control register 1 (gptc tl1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-9 20.5.9 gpt control register 2 (gptc tl2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-10 20.5.10gpt interrupt enable register (gptie) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-10 20.5.11gpt system control register 2 (gptscr2) . . . . . . . . . . . . . . . . . . . . . . . 20-11 20.5.12gpt flag register 1 (g ptflg1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-12 20.5.13gpt flag register 2 (g ptflg2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-12 20.5.14gpt channel registers (gptcn) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-13 20.5.15pulse accumulator control r egister (gptpactl) . . . . . . . . . . . . . . . . . . . 20-14 20.5.16pulse accumulator flag register (gptpaflg) . . . . . . . . . . . . . . . . . . . . . 20-15 20.5.17pulse accumulator counter register (gptpa cnt) . . . . . . . . . . . . . . . . . . 20-16 20.5.18gpt port data register (gpt port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-16 20.5.19gpt port data direction r egister (gptddr) . . . . . . . . . . . . . . . . . . . . . . . 20-17 20.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-1 7 20.6.1 prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-17 20.6.2 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-17 20.6.3 output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-18 20.6.4 pulse accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-18 20.6.5 event counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-18 20.6.6 gated time accumulation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-19 20.6.7 general-purpose i/o ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-19 20.7 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-21 20.8 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-21 20.8.1 gpt channel interrupts (cnf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-21 20.8.2 pulse accumulator overflow (p aovf) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-22 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor xix 20.8.3 pulse accumulator input (paif) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-22 20.8.4 timer overflow (tof) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-22 chapter 21 dma timers (dtim0?dtim3) 21.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 21.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-1 21.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-2 21.2 memory map/register definiti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3 21.2.1 dma timer mo de registers (dtmr n ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-3 21.2.2 dma timer extended mode registers (dtxmr n ) . . . . . . . . . . . . . . . . . . . . . 21-5 21.2.3 dma timer event registers (dter n ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-5 21.2.4 dma timer reference registers (dtrr n ) . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7 21.2.5 dma timer capture registers (dtcr n ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-7 21.2.6 dma timer counters (dtcn n ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8 21.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 -8 21.3.1 prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8 21.3.2 capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8 21.3.3 reference compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-8 21.3.4 output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9 21.4 initialization/application in formation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9 21.4.1 code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-9 21.4.2 calculating time-out values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21-10 chapter 22 queued serial peripheral interface (qspi) 22.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 22.1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-1 22.1.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 22.1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 22.1.4 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 22.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-2 22.3 memory map/register definiti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3 22.3.1 qspi mode register (qmr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-3 22.3.2 qspi delay register (qdlyr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-5 22.3.3 qspi wrap register (qwr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 22.3.4 qspi interrupt register (qir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-6 22.3.5 qspi address register (qar) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-7 22.3.6 qspi data register (qdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8 22.3.7 command ram registers (qcr 0?qcr15) . . . . . . . . . . . . . . . . . . . . . . . . . . 22-8 22.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 -9 22.4.1 qspi ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11 22.4.1.1 receive ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-11 22.4.1.2 transmit ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-12 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 xx freescale semiconductor 22.4.1.3 command ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-12 22.4.2 baud rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-12 22.4.3 transfer delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-13 22.4.4 transfer length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-14 22.4.5 data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-14 22.5 initialization/application in formation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22-15 chapter 23 uart modules 23.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 23.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 23.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-2 23.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3 23.3 memory map/register definiti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-3 23.3.1 uart mode registers 1 (umr1 n ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-5 23.3.2 uart mode register 2 (umr2 n ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-6 23.3.3 uart status registers (usr n ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-8 23.3.4 uart clock select registers (ucsr n ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-9 23.3.5 uart command registers (ucr n ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-9 23.3.6 uart receive buffers (urb n ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-11 23.3.7 uart transmit buffers (utb n ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-12 23.3.8 uart input port change registers (uipcr n ) . . . . . . . . . . . . . . . . . . . . . . . 23-12 23.3.9 uart auxiliary control register (uacr n ) . . . . . . . . . . . . . . . . . . . . . . . . . . 23-13 23.3.10uart interrupt stat us/mask registers (uisr n /uimr n ) . . . . . . . . . . . . . . . 23-13 23.3.11uart baud rate g enerator registers (ubg1 n /ubg2 n ) . . . . . . . . . . . . . . 23-15 23.3.12uart input port register (uip n ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-15 23.3.13uart output port command registers (uop1n /uop0n ) . . . . . . . . . . . . . 23-16 23.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-1 6 23.4.1 transmitter/receiver clock sour ce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-16 23.4.1.1 programmable divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-17 23.4.1.2 calculating baud rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-17 23.4.2 transmitter and rece iver operating modes . . . . . . . . . . . . . . . . . . . . . . . . . 23-18 23.4.2.1 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-18 23.4.2 .2 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-20 23.4.2.3 fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-21 23.4.3 looping modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-22 23.4.3.1 automatic echo mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-23 23.4.3.2 local loopback mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-23 23.4.3.3 remote loopback mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-23 23.4.4 multidrop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-24 23.4.5 bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-26 23.4.5.1 read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-26 23.4.5.2 write cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-26 23.5 initialization/application in formation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-26 23.5.1 interrupt and dma request initia lization . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-26 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor xxi 23.5.1.1 setting up the uart to generate core interrupts . . . . . . . . . . . . . 23-26 23.5.1.2 setting up the uart to request dma service . . . . . . . . . . . . . . . 23-27 23.5.2 uart module initializa tion sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-29 chapter 24 i 2 c interface 24.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1 24.1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1 24.1.2 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2 24.1.3 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2 24.2 memory map/register definiti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3 24.2.1 i 2 c address register (i2adr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3 24.2.2 i 2 c frequency divider register (i2fdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3 24.2.3 i 2 c control register (i2cr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4 24.2.4 i 2 c status register (i2sr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5 24.2.5 i 2 c data i/o register (i2dr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6 24.3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 -7 24.3.1 start signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-7 24.3.2 slave address transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-8 24.3.3 data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-8 24.3.4 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9 24.3.5 stop signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9 24.3.6 repeated start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9 24.3.7 clock synchronization and arbitr ation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-11 24.3.8 handshaking and clock stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12 24.4 initialization/application in formation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12 24.4.1 initialization sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12 24.4.2 generation of start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12 24.4.3 post-transfer software response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-13 24.4.4 generation of stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-13 24.4.5 generation of repeated start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14 24.4.6 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14 24.4.7 arbitration lost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14 chapter 25 flexcan 25.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1 25.1.1 flexcan memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2 25.1.2 external signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3 25.2 the can system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 -4 25.3 message buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4 25.3.1 message buffer structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4 25.3.1.1 common fields for extended and standard format frames . . . . . . 25-5 25.3.1.2 fields for extended forma t frames . . . . . . . . . . . . . . . . . . . . . . . . . 25-7 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 xxii freescale semiconductor 25.3.1.3 fields for standar d format frames . . . . . . . . . . . . . . . . . . . . . . . . . 25-7 25.3.2 message buffer memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-7 25.4 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 -8 25.4.1 transmit process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-8 25.4.2 receive process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-9 25.4.2.1 self-received frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-10 25.4.3 message buffer handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-10 25.4.3.1 serial message buffers (smb s) . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-10 25.4.3.2 transmit message bu ffer deactivation . . . . . . . . . . . . . . . . . . . . . . 25-10 25.4.3.3 receive message buffer deactivation . . . . . . . . . . . . . . . . . . . . . . 25-10 25.4.3.4 locking and releasing message buffers . . . . . . . . . . . . . . . . . . . . 25-11 25.4.4 remote frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-11 25.4.5 overload frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12 25.4.6 time stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12 25.4.7 listen-only mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12 25.4.8 bit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-12 25.4.8.1 configuring the flexcan bit timing . . . . . . . . . . . . . . . . . . . . . . . . 25-13 25.4.9 flexcan error counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-13 25.4.10flexcan initiali zation sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-14 25.4.11special operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15 25.4.11.1 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-15 25.4.11.2 low-power stop mode fo r power saving . . . . . . . . . . . . . . . . . . . 25-15 25.4.11.3 auto-power save mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-17 25.4.12interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-17 25.5 programmer?s model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-17 25.5.1 can module configur ation register (canmcr) . . . . . . . . . . . . . . . . . . . . . 25-18 25.5.2 flexcan control register 0 (c anctrl0) . . . . . . . . . . . . . . . . . . . . . . . . . . 25-20 25.5.3 flexcan control register 1 (c anctrl1) . . . . . . . . . . . . . . . . . . . . . . . . . . 25-21 25.5.4 p rescaler divide regist er (presdiv) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-22 25.5.5 flexcan control register 2 (c anctrl2) . . . . . . . . . . . . . . . . . . . . . . . . . . 25-22 25.5.6 free running timer (timer ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-23 25.5.7 rx mask registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-23 25.5.7.1 receive mask registers (r xgmask, rx14mask, rx15mask) . 25-24 25.5.8 flexcan error and status register (estat) . . . . . . . . . . . . . . . . . . . . . . . . 25-25 25.5.9 interrupt mask register (imask) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-27 25.5.10interrupt flag register (iflag) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-28 25.5.11flexcan receive error count er (rxectr) . . . . . . . . . . . . . . . . . . . . . . . . 25-29 25.5.12flexcan transmit erro r counter (txectr) . . . . . . . . . . . . . . . . . . . . . . . . 25-30 chapter 26 general purpose i/o module 26.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-1 26.1.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4 26.1.2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4 26.1.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor xxiii 26.2 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-4 26.3 memory map/register definiti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-7 26.3.1 register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-7 26.3.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-10 26.3.2.1 port output data regi sters (portn) . . . . . . . . . . . . . . . . . . . . . . . 26-10 26.3.2.2 port data direction registers (ddrn) . . . . . . . . . . . . . . . . . . . . . . 26-11 26.3.2.3 port pin data/set da ta registers (portnp/setn) . . . . . . . . . . . . 26-13 26.3.2.4 port clear output data registers (clrn) . . . . . . . . . . . . . . . . . . . 26-14 26.3.2.5 port b/c/d pin assi gnment register (pbcdpar) . . . . . . . . . . . . . 26-16 26.3.2.6 port e pin assignment r egister (pepar) . . . . . . . . . . . . . . . . . . . 26-17 26.3.2.7 port f pin assignment re gister (pfpar) . . . . . . . . . . . . . . . . . . . 26-19 26.3.2.8 port j pin assignment register (pjpar) . . . . . . . . . . . . . . . . . . . . 26-20 26.3.2.9 port sd pin assignment register (psdpar) . . . . . . . . . . . . . . . . . 26-21 26.3.2.10 port as pin a ssignment register (paspar) . . . . . . . . . . . . . . . . 26-21 26.3.2.11 port eh/el pin assign ment register (pehlpar) . . . . . . . . . . . . 26-22 26.3.2.12 port qs pin assignment register (pqspar) . . . . . . . . . . . . . . . 26-23 26.3.2.13 port tc pin assignment register (ptcpar) . . . . . . . . . . . . . . . . 26-24 26.3.2.14 port td pin assignment register (ptdpar) . . . . . . . . . . . . . . . . 26-25 26.3.2.15 port ua pin assignment register (puapar) . . . . . . . . . . . . . . . . 26-26 26.4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-2 7 26.4.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-27 26.4.2 port digital i/o timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-27 26.5 initialization/application in formation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26-28 chapter 27 chip configuration module (ccm) 27.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1 27.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 -1 27.2.1 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1 27.2.2 single-chip mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-1 27.3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2 27.4 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2 27.4.1 rcon . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2 27.4.2 clkmod[1:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-2 27.4.3 d[26:24, 21, 19:16] (reset configuration override) . . . . . . . . . . . . . . . . . . . . 27-3 27.5 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3 27.5.1 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3 27.5.2 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-3 27.5.3 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-4 27.5.3.1 chip configuration regist er (ccr) . . . . . . . . . . . . . . . . . . . . . . . . . 27-4 27.5.3.2 reset configuration regist er (rcon) . . . . . . . . . . . . . . . . . . . . . . . 27-5 27.5.3.3 chip identification regist er (cir) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-6 27.6 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 -6 27.6.1 reset configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-7 27.6.2 chip mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-8 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 xxiv freescale semiconductor 27.6.3 boot device selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-9 27.6.4 output pad strength c onfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-9 27.6.5 clock mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-9 27.6.6 chip select configurati on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-10 27.7 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-10 27.8 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27-10 chapter 28 queued analog-to-digital converter (qadc) 28.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-1 28.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-2 28.3 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 -2 28.3.1 debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-2 28.3.2 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-3 28.4 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-3 28.4.1 port qa signal functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-3 28.4.1.1 port qa analog input signa ls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-4 28.4.1.2 port qa digital input/out put signals . . . . . . . . . . . . . . . . . . . . . . . . 28-4 28.4.2 port qb signal functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-4 28.4.2.1 port qb analog input signa ls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-4 28.4.2.2 port qb digital i/ o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-5 28.4.3 external trigger input si gnals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-5 28.4.4 multiplexed address output sig nals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-5 28.4.5 multiplexed analog i nput signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-5 28.4.6 voltage reference signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-6 28.4.7 dedicated analog supply signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-6 28.4.8 dedicated digital i/o port suppl y signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-6 28.5 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-6 28.6 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 -7 28.6.1 qadc module configur ation register (qadcmcr) . . . . . . . . . . . . . . . . . . . 28-7 28.6.2 qadc test register (q adctest) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-8 28.6.3 port data registers (portqa & portqb) . . . . . . . . . . . . . . . . . . . . . . . . . 28-8 28.6.4 port qa and qb data direc tion register (ddrqa & ddrqb) . . . . . . . . . . . 28-9 28.6.5 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-10 28.6.5.1 qadc control register 0 (qacr0) . . . . . . . . . . . . . . . . . . . . . . . . 28-10 28.6.5.2 qadc control register 1 (qacr1) . . . . . . . . . . . . . . . . . . . . . . . . 28-12 28.6.5.3 qadc control register 2 (qacr2) . . . . . . . . . . . . . . . . . . . . . . . . 28-14 28.6.6 status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-17 28.6.6.1 qadc status regi ster 0 (qasr0) . . . . . . . . . . . . . . . . . . . . . . . . . 28-17 28.6.6.2 qadc status regi ster 1 (qasr1) . . . . . . . . . . . . . . . . . . . . . . . . . 28-23 28.6.7 conversion command word table (ccw) . . . . . . . . . . . . . . . . . . . . . . . . . . 28-24 28.6.8 result registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-27 28.6.8.1 right-justified unsigned result regist er (rjurr) . . . . . . . . . . . . 28-27 28.6.8.2 left-justified signed re sult register (ljsrr) . . . . . . . . . . . . . . . . 28-27 28.6.8.3 left-justified unsigned result regist er (ljurr) . . . . . . . . . . . . . . 28-28 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor xxv 28.7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-2 8 28.7.1 result coherency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-28 28.7.2 external multiplexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-29 28.7.2.1 external multiplexing oper ation . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-29 28.7.2.2 module version options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-31 28.7.3 analog subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-31 28.7.3.1 analog-to-digital conver ter operation . . . . . . . . . . . . . . . . . . . . . . 28-31 28.7.3.2 conversion cycle times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-32 28.7.3.3 channel decode and multip lexer . . . . . . . . . . . . . . . . . . . . . . . . . . 28-33 28.7.3.4 sample buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-33 28.7.3.5 comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-33 28.7.3.6 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-34 28.7.3.7 successive approximati on register (sar) . . . . . . . . . . . . . . . . . . 28-34 28.7.3.8 state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-34 28.8 digital control subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-34 28.8.1 queue priority timing examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-34 28.8.1.1 queue priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-34 28.8.1.2 queue priority schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-36 28.8.2 boundary conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-45 28.8.3 scan modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-46 28.8.4 disabled mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-47 28.8.5 reserved mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-47 28.8.6 single-scan modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-47 28.8.6.1 software-initiated singl e-scan mode . . . . . . . . . . . . . . . . . . . . . . . 28-48 28.8.6.2 externally triggered si ngle-scan mode . . . . . . . . . . . . . . . . . . . . . 28-48 28.8.6.3 externally gated single- scan mode . . . . . . . . . . . . . . . . . . . . . . . . 28-48 28.8.6.4 interval timer single-scan mode . . . . . . . . . . . . . . . . . . . . . . . . . . 28-49 28.8.7 continuous-scan modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-49 28.8.7.1 software-initiated cont inuous-scan mode . . . . . . . . . . . . . . . . . . . 28-50 28.8.7.2 externally triggered continuous-scan m ode . . . . . . . . . . . . . . . . . 28-50 28.8.7.3 externally gated cont inuous-scan mode . . . . . . . . . . . . . . . . . . . . 28-51 28.8.7.4 periodic timer continu ous-scan mode . . . . . . . . . . . . . . . . . . . . . 28-51 28.8.8 qadc clock (qclk) g eneration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-52 28.8.9 periodic/interval timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-52 28.8.10conversion command word table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-53 28.8.11result word table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-55 28.9 signal connection considerat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-56 28.9.1 analog reference signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-56 28.9.2 analog power signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-56 28.9.3 conversion timing schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-58 28.9.4 analog supply filteri ng and grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-61 28.9.5 accommodating positive/negat ive stress conditions . . . . . . . . . . . . . . . . . 28-62 28.9.6 analog input considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-64 28.9.7 analog input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-66 28.9.7.1 settling time fo r the external circuit . . . . . . . . . . . . . . . . . . . . . . . 28-67 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 xxvi freescale semiconductor 28.9.7.2 error resulting from leakage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-67 28.10interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-68 28.10.1interrupt operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-68 28.10.2interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28-68 chapter 29 reset contro ller module 29.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1 29.2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-1 29.3 signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2 29.3.1 rsti . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2 29.3.2 rsto . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2 29.4 memory map and registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-2 29.4.1 reset control register (rcr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-3 29.4.2 reset status register (rsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-4 29.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 -5 29.5.1 reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-5 29.5.1.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6 29.5.1.2 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6 29.5.1.3 watchdog timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6 29.5.1.4 loss-of-clock reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6 29.5.1.5 loss-of-lock reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6 29.5.1.6 software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6 29.5.1.7 lvd reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-6 29.5.2 reset control flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-7 29.5.2.1 synchronous reset requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-9 29.5.2.2 internal reset request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-9 29.5.2.3 power-on reset/low-vol tage detect reset . . . . . . . . . . . . . . . . . . 29-9 29.5.3 concurrent resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-9 29.5.3.1 reset flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-9 29.5.3.2 reset status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29-10 chapter 30 debug support 30.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-1 30.2 signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-2 30.3 real-time trace support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-2 30.3.1 begin execution of taken branc h (pst = 0x5) . . . . . . . . . . . . . . . . . . . . . . . . 30-4 30.4 programming model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-5 30.4.1 revision a shared debug resource s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-7 30.4.2 address attribute trigger register (aatr) . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-7 30.4.3 address breakpoint registers (a blr, abhr) . . . . . . . . . . . . . . . . . . . . . . . . 30-9 30.4.4 configuration/status r egister (csr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-10 30.4.5 data breakpoint/mask regist ers (dbr, dbmr) . . . . . . . . . . . . . . . . . . . . . . 30-12 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor xxvii 30.4.6 program counter breakpoi nt/mask registers (pbr, pbmr) . . . . . . . . . . . . 30-13 30.4.7 trigger definition register (tdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-14 30.5 background debug mode (bdm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-16 30.5.1 cpu halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-16 30.5.2 bdm serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-18 30.5.2.1 receive packet format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-18 30.5.2.2 transmit packet format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-19 30.5.3 bdm command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-19 30.5.3.1 coldfire bdm command for mat . . . . . . . . . . . . . . . . . . . . . . . . . . 30-20 30.5.3.2 command sequence diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-21 30.5.3.3 command set descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-22 30.6 real-time debug support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-37 30.6.1 theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-37 30.6.1.1 emulator mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-38 30.6.2 concurrent bdm and processor o peration . . . . . . . . . . . . . . . . . . . . . . . . . 30-38 30.7 processor status, ddata definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-39 30.7.1 user instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-39 30.7.2 supervisor instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-43 30.8 freescale-recommended bdm pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30-45 chapter 31 ieee 1149.1 test access port (jtag) 31.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-2 31.2 modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 -2 31.3 external signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-2 31.3.1 detailed signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-2 31.3.1.1 jtag_en ? jtag enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-2 31.3.1.2 tclk ? test clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-3 31.3.1.3 tms/bkpt ? test mode select / breakpoint . . . . . . . . . . . . . . . . . 31-3 31.3.1.4 tdi/dsi ? test data in put / development serial in put . . . . . . . . . . 31-3 31.3.1.5 trst/dsclk ? test re set / development serial clock . . . . . . . . 31-3 31.3.1.6 tdo/dso ? test data output / development serial output . . . . . 31-4 31.4 memory map/register definiti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-4 31.4.1 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-4 31.4.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-4 31.4.2.1 instruction shift re gister (ir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-4 31.4.2.2 idcode register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-4 31.4.2.3 bypass register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-5 31.4.2.4 jtag_cfm_clkdiv register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-5 31.4.2.5 test_ctrl register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-5 31.4.2.6 boundary scan regi ster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-5 31.5 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 -5 31.5.1 jtag module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-5 31.5.2 tap controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-6 31.5.3 jtag instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-6 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 xxviii freescale semiconductor 31.5.3.1 external test instruction (extest) . . . . . . . . . . . . . . . . . . . . . . . . . 31-7 31.5.3.2 idcode instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-7 31.5.3.3 sample/preload instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-7 31.5.3.4 test_leakage instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-8 31.5.3.5 enable_test_ctrl instruction . . . . . . . . . . . . . . . . . . . . . . . . . . 31-8 31.5.3.6 highz instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-8 31.5.3.7 lockout_recovery instruction . . . . . . . . . . . . . . . . . . . . . . . . . 31-8 31.5.3.8 clamp instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-9 31.5.3.9 bypass instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-9 31.6 initialization/application in formation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-9 31.6.1 restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-9 31.6.2 nonscan chain operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31-9 chapter 32 mechanical data 32.1 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-1 32.2 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2-9 chapter 33 electrical characteristics 33.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 -1 33.2 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33- 2 33.3 dc electrical spec ifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-3 33.4 power consumption specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-4 33.5 phase lock loop electrical spec ifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-7 33.6 qadc electrical characterist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-8 33.7 flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-10 33.8 external interface timing characteri stics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-11 33.9 processor bus output timing specific ations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-12 33.10general purpose i/o timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-18 33.11reset and configuration override timi ng . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-19 33.12i 2 c input/output timing s pecifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-20 33.13fast ethernet ac timing specificati ons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-21 33.13.1mii receive signal timing (erxd[3:0 ], erxdv, erxer, and erxclk) . . 33-21 33.13.2mii transmit signal timi ng (etxd[3:0], etxen, etxer, etxclk) . . . . . 33-22 33.13.3mii async inputs signal timi ng (ecrs and ecol) . . . . . . . . . . . . . . . . . . 33-23 33.13.4mii serial management channel timing (emdio and emdc) . . . . . . . . . . 33-23 33.14dma timer module ac timi ng specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-24 33.15qspi electrical specif ications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-24 33.16jtag and boundary scan timi ng . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-25 33.17debug ac timing specificati ons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33-27 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor xxix appendix a register memory map appendix b revision history b.1 changes between rev. 0 and re v. 0.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-1 b.2 changes between rev. 0. 1 and rev. 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-2 b.3 changes between rev. 1 and re v. 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-5 b.4 changes between rev. 2 and re v. 2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-7 b.5 changes between rev. 2.1 and rev. 2.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-7 b.6 changes between rev. 2.2 and rev. 2.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-7 b.7 changes between rev. 2. 3 and rev. 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-8 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 xxx freescale semiconductor mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor xxxi about this book the primary objective of this user?s manual is to define the functionality of the mcf5282 processor for use by software and hardware developers. the information in this book, except for changes to the flash and ethernet functionality, also applies to the mcf5280, mcf5281, mcf5216, and mcf5214. the information in this book is subjec t to change without notic e, as described in the disclaimers on the title page. as with any technical documentation, it is the reader?s responsibil ity to be sure he is using the most recent version of the documentation. to locate any published errata or updates for th is document, refer to the world-wide web at http://www.freescale.com/coldfire . audience this manual is intended for system software and hardware developers and applications programmers who want to develop products with the mcf5282. it is assumed that the reader understands operating systems, microprocessor system design, basic principles of software and hard ware, and basic details of the coldfire ? architecture. suggested reading this section lists additional reading that provides bac kground for the information in this manual as well as general information about the coldfire architecture. general information the following documentation provides useful information about the cold fire architecture and computer architecture in general: ? coldfire programmers reference manual, r1.0 (mcf5200prm/ad) ? using microprocessors and microcomputers: the motorola family, william c. wray, ross bannatyne, joseph d. greenfield ? computer architecture: a quantitative approach , second edition, by john l. hennessy and david a. patterson. ? computer organization and design: the hardware/software interface , second edition, david a . patterson and john l. hennessy. coldfire documentation coldfire documentation is av ailable from the sources listed on the b ack cover of this manual, as well as our web site, http://www.freescale.com/coldfire . mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 xxxii freescale semiconductor ? user?s manuals ? these books provi de details about individual cold fire implementations and are intended to be used in conjunction with the coldfire programmers reference manual. ? data sheets ? data sheets provide specific da ta regarding pin-out diagrams, bus timing, signal behavior, and ac, dc, and thermal characteristi cs, as well as other design considerations. ? product briefs ? each device has a product brief th at provides an overview of its features. this document is roughly equivalent to the overview (chapter 1) of an device?s reference manual. ? application notes ? these short documents addres s specific design issues useful to programmers and engineers working with free scale semiconductor processors. additional literature is published as new processors become available. for a current list of coldfire documentation, refer to http://www.freescale.com/coldfire. conventions this document uses the following notational conventions: mnemonics in text, instruction mn emonics are shown in uppercase. mnemonics in code and tables, instruction mnemonics are shown in lowercase. italics italics indicate variable command parameters. book titles in text are set in italics. 0x0 prefix to denote hexadecimal number 0b0 prefix to denote binary number reg[field] abbreviations for regist ers are shown in uppercase. sp ecific bits, fields, or ranges appear in brackets. for example, rambar [ba] identifies the base address field in the ram base address register. nibble a 4-bit data unit byte an 8-bit data unit word a 16-bit data unit 1 longword a 32-bit data unit x in some contexts, such as signal encodings, x indicates a don?t care. n used to express an undefined numerical value ~ not logical operator & and logical operator | or logical operator 1 the only exceptions to this appear in the discussion of serial communication mo dules that support variable-length data transmission units. to simplify the discussion these un its are referred to as words regardless of length. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor 1-1 chapter 1 overview this chapter provides an overview of the micr oprocessor features, incl uding the major functional components. 1.1 key features a block diagram of the mcf528 x and mcf521 x is shown in figure 1-1 . the main features are as follows: ? static version 2 coldfire va riable-length risc processor ? static operation ? on-chip 32-bit address and data path ? processor core and bus frequency up to 80 mhz ? sixteen general-purpose 32-bit data and address registers ? coldfire isa_a with extensions to support th e user stack pointer re gister, and four new instructions for improved bit processing ? enhanced multiply-accumulate (emac) unit wi th four 48-bit accumulators to support 32-bit signal processing algorithms ? illegal instruction decode that allows for 68k emulation support ? system debug support ? real-time trace for determin ing dynamic execution path ? background debug mode (bdm) for in-circuit debugging ? real time debug support, with one user-visible hardware breakpoint register (pc and address with optional data) that can be configured into a 1- or 2-level trigger ? on-chip memories ? 2-kbyte cache, configurable as instruct ion-only, data-only, or split i-/d-cache ? 64-kbyte dual-ported sram on cpu internal bus, accessible by core a nd non-core bus masters (e.g., dma, fec) with standby power supply support ? 512 kbytes of interleaved flash memory supporting 2-1-1-1 accesses (256 kbytes on the mcf5281 a nd mcf5214, no flash on mcf5280) ? this product incorporates superfla sh? technology licensed from sst. ? power management ? fully-static operation with proces sor sleep and whole chip stop modes ? very rapid response to interrupts from the low-power sleep mode (wake-up feature) ? clock enable/disable for each peripheral when not used ? fast ethernet controller (fec) (not available on the mcf5214 and mcf5216) ? 10baset capability, half- or full-duplex ? 100baset capability, half- or limited-throughput full-duplex ? on-chip transmit and receive fifos ? built-in dedicated dma controller mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 overview 1-2 freescale semiconductor ? memory-based flexible descriptor rings ? media-independent interface (mii) to transceiver (phy) ? flexcan 2.0b module ? includes all existing features of the freescale toucan module ? full implementation of the can pr otocol specification version 2.0b ? standard data and remote fr ames (up to 109 bits long) ? extended data and remote fr ames (up to 127 bits long) ? 0?8 bytes data length ? programmable bit ra te up to 1 mbit/sec ? up to 16 message buffers (mbs) ? configurable as receive (rx) or transmit (tx) ? support standard and extended messages ? unused message buffer (mb) space can be used as general-purpose ram space ? listen-only mode capability ? content-related addressing ? no read/write semaphores ? three programmable mask registers ? global (for mbs 0-13) ? special for mb14 ? special for mb15 ? programmable transmit-first scheme: lowest id or lowest buffer number ? ?time stamp? based on 16-bit free-running timer ? global network time, synchr onized by a specific message ? programmable i/o modes ? maskable interrupts ? three universal asynchr onous/synchronous receiver tr ansmitters (uarts) ? 16-bit divider for clock generation ? interrupt control logic ? maskable interrupts ? dma support ? data formats can be 5, 6, 7, or 8 bits with even, odd, or no parity ? up to 2 stop bits in 1/16 increments ? error-detection capabilities ? modem support includes request-to-send (urts ) and clear-to-send (ucts ) lines for two uarts ? transmit and receive fifo buffers ?i 2 c module ? interchip bus interface for eeproms, lcd controllers, a/d converters, and keypads ? fully compatible with industry-standard i 2 c bus ? master or slave modes support multiple masters ? automatic interrupt genera tion with programmable level mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 overview freescale semiconductor 1-3 ? queued serial peripheral interface (qspi) ? full-duplex, three-wire synchronous transfers ? up to four chip selects available ? master mode operation only ? programmable master bit rates ? up to 16 pre-programmed transfers ? queued analog-to-digit al converter (qadc) ? 8 direct, or up to 18 multiplexed, analog input channels ? 10-bit resolution +/- 2 counts accuracy ? minimum 7 s conversion time ? internal sample and hold ? programmable input sample time for various source impedances ? two conversion command queues with a total of 64 entries ? sub-queues possible using pause mechanism ? queue complete and pause software interrupts available on both queues ? queue pointers indicate cu rrent location for each queue ? automated queue modes initiated by: ? external edge trigger and gated trigger ? periodic/interval timer, with in qadc module [queue 1 and 2] ? software command ? single-scan or continuous-scan of queues ? output data readable in three formats: ? right-justified unsigned ? left-justified signed ? left-justified unsigned ? unused analog channels ca n be used as digital i/o ? low pin-count conf iguration implemented ? four 32-bit dma timers ? 15-ns resolution at 80 mhz (66 mhz for mcf5214 and mcf5216) ? programmable sources for clock input, including an external clock option ? programmable prescaler ? input-capture capability with progr ammable trigger edge on input pin ? output-compare with programma ble mode for the output pin ? free run and restart modes ? maskable interrupts on input cap ture or reference-compare ? dma trigger capability on input capture or reference-compare ? two 4-channel general purpose timers ? four 16-bit input capture/output compare channels per timer ? 16-bit architecture ? programmable prescaler ? pulse widths variable fr om microseconds to seconds ? single 16-bit pulse accumulator mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 overview 1-4 freescale semiconductor ? toggle-on-overflow feature for pulse-w idth modulator (pwm) generation ? one dual-mode pulse accumulation channel per timer ? four periodic interrupt timers (pits) ? 16-bit counter ? selectable as free running or count down ? software watchdog timer ? 16-bit counter ? low-power mode support ? phase locked loop (pll) ? crystal or external oscillator reference ? 2- to 10-mhz reference frequency for normal pll mode ? 33- to 80-mhz (66 mhz for mcf5214/16) osci llator reference frequency for 1:1 mode ? low-power modes supported ? separate clock output pin ? two interrupt controllers ? support for up to 63 interrupt sources per interr upt controller (a total of 126), organized as follows: ? 56 fully-programmable interrupt sources ? 7 fixed-level interrupt sources ? seven external interrupt signals ? unique vector number fo r each interrupt source ? ability to mask any individual interrupt sour ce or all interrupt s ources (global mask-all) ? support for hardware and software interrupt acknowledge (iack) cycles ? combinatorial path to provide wake-up from lo w-power modes ? dma controller ? four fully programmable channels ? dual-address transfer support with 8-, 16- and 32-bit data capability along with support for 16-byte (4 x 32-bit) burst transfers ? source/destination address pointers that can increment or remain constant ? 24-bit byte transfer counter per channel ? auto-alignment transfers supporte d for efficient block movement ? bursting and cycle steal support ? software-programmable connections between th e 11 dma requesters in the uarts (3), 32-bit timers (4) plus external logi c (4) and the four dma channels ? external bus interface ? glueless connections to external memory devices (e.g., sram, flash, rom, etc.) ? sdram controller supports 8-, 16-, and 32-bit wide memory devices ? glueless interface to sram devices with or without byte strobe inputs ? programmable wait state generator ? 32-bit bidirectional data bus ? 24-bit address bus ? up to seven chip selects available ? byte/write enables (byte strobes) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 overview freescale semiconductor 1-5 ? ability to boot from internal fl ash memory or external memories that are 8, 16, or 32 bits wide ?reset ? separate reset in and reset out signals ? seven sources of reset: ? power-on reset (por) ? external ? software ? watchdog ? loss of clock ? loss of lock ? low-voltage detection (lvd) ? status flag indication of source of last reset ? chip integration module (cim) ? system configuration during reset ? support for single chip, master, and test modes ? selects one of four clock modes ? sets boot device and its data port width ? configures output pad drive strength ? unique part identification num ber and part revision number ? general purpose i/o interface ? up to 142 bits of genera l purpose i/o for mcf5280/1/2 ? up to 134 bits of general purpose i/o for mcf5214/6 ? coherent 32-bit control ? bit manipulation supporte d via set/clear functions ? unused peripheral pins may be used as extra gpio ? jtag support for system-level board testing mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 overview 1-6 freescale semiconductor figure 1-1. mcf528 x and mcf521 x block diagram interface chip uart1 serial i/o jtag port selects coldfire v2 core emac external te s t controller i 2 c module uart2 serial i/o dma timer modules dram controller 2-kbyte d-cache/i-cache debug module div clock module chip configuration reset controller power (pll) edgeport interrupt controller 0 interrupt controller 1 fec uart0 serial i/o dma controller watchdog timer general purpose timer a general purpose timer b qspi flexcan qadc pit timers (pit0? (dtim0? dtim3) management module ports module pit3) internal bus arbiter system control module (scm) flash module 64k sram note: not present on mcf5214 and mcf5216 note: not present on mcf5280 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 overview freescale semiconductor 1-7 1.1.1 version 2 coldfire core the processor core is comprised of two separate pipelines that are dec oupled by an instruction buffer. the two-stage instruction fetch pipeline (ifp) is responsible for instructi on-address generation and instruction fetch. the instruction buffer is a first- in-first-out (fifo) buff er that holds prefetched instructions awaiting execution in the operand execution pipeline (oep). the oep includes two pipeline stages. the first stage decodes instructions and select s operands (dsoc); the second stag e (agex) performs instruction execution and calculates operand effective addresses, if needed. the v2 core implements the coldfire instruction set architecture revision a with added support for a separate user stack pointer register and four new instructions to assist in bit processing. additionally, the mcf5282 core includes the enhanced multiply-accumu late unit (emac) for im proved signal processing capabilities. the emac implements a 4-stage exec ution pipeline, optimized for 32 x 32 bit operations, with support for four 48-bit accumulators. supported operands include 16- and 32-bit signed and unsigned integers, signed fractional operands, a nd a complete set of instructions to process these data types. the emac provides superb support for execution of dsp operations within the contex t of a single processor at a minimal hardware cost. 1.1.1.1 cache the 2-kbyte cache can be c onfigured into one of thr ee possible organizations: a 2-kbyte instruction cache, a 2-kbyte data cache or a split 1-kbyte instruction/1-kbyte da ta cache. the configuration is software-programmable by cont rol bits within the privileged cache c onfiguration register (cacr). in all configurations, the cache is a direct-mapped single-cy cle memory, organized as 128 lines, each containing 16 bytes of data. the memories cons ist of a 128-entry tag ar ray (containing addresses and control bits) and a 2-kbyte data array, organized as 512 x 32 bits. the tag and data arrays are accessed in parallel using the following address bits: if the desired address is mapped into the cache memory , the output of the data array is driven onto the coldfire core's local data bus, completing the access in a single cycle. if the data is not mapped into the tag memory, a cache miss occurs and the processor co re initiates a 16-byte line-sized fetch. the cache module includes a 16-byte line fill buf fer used as temporary storage dur ing miss processing. for all data cache configurations, the memory operates in write-thr ough mode and all opera nd writes generate an external bus cycle. 1.1.1.2 sram the sram module provides a general-purpose 64-kbyte me mory block that the coldfire core can access in a single cycle. the location of the memory bl ock can be set to any 64-kbyte boundary within the 4-gbyte address space. the memory is ideal for storing criti cal code or data structures, for use as the system stack, or for stor ing fec data buffers. beca use the sram module is phys ically connected to the processor's high-speed local bus, it can quickly service core-initiat ed accesses or memory-referencing commands from the debug module. table 1-1. cache configuration configuration tag address data array address 2 kbyte i-cache [10:4] [10:2] 2 kbyte d-cache [10:4] [10:2] split i-/d-cache 0 instruction fetches operand accesses 0, [9:4] 1, [9:4] 0, [9:2] 1, [9:2] mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 overview 1-8 freescale semiconductor the sram module is also accessible by non-core bus masters, for example the dma and/or the fec. the dual-ported nature of the sram ma kes it ideal for implem enting applications with double-buffer schemes, where the processor and a dma device operate in al ternate regions of the sram to maximize system performance. as an example, system performance can be in creased significantly if ethernet packets are moved from the fec into the sram (rather than external memory) prior to any processing. 1.1.1.3 flash this product incorporates superflash? technology lice nsed from sst. the cold fire flash module (cfm) is a non-volatile memory (nvm) module for integration with the proces sor core. the cfm is constructed with eight banks of 32k x 16-bit flash arrays to generate 512 kbytes of 32-bit flash memory note the cfm on the mcf5281 and mcf5214 is constructed with four banks of 32k x 16-bit flash arrays to generate 256 kbytes of 32-bit flash memory. the mcf5280 does not contain a cfm. these arrays serve as elect rically erasable and programmable, non-vo latile program and data memory. the flash memory is ideal for program and data storage for single-chip applications allowing for field reprogramming without requiring an external programming voltage s ource. the cfm interfaces to the v2 coldfire core through an optimiz ed read-only memory controller which supports interleaved accesses from the 2-cycle flash arrays. a ?b ackdoor? mapping of the flash memory is used for all program, erase, and verify operations. it also pr ovides a read datapath for non-core masters (for example, dma). 1.1.1.4 debug module the coldfire processor core debug interface is provided to support sy stem debugging in conjunction with low-cost debug and emulator deve lopment tools. through a standard debug interface, users can access real-time trace and debug information. this allows the processor and syst em to be debugge d at full speed without the need for costly in-circu it emulators. the debug interface is a superset of the bdm interface provided on freescale? s 683xx family of parts. the on-chip breakpoint resources incl ude a total of 6 progra mmable registers?a set of address registers (with two 32-bit registers), a set of data registers (w ith a 32-bit data register plus a 32-bi t data mask register), and one 32-bit pc register plus a 32-bit pc mask register. these regi sters can be accessed through the dedicated debug serial communi cation channel or from the processor?s supervisor mode programming model. the breakpoint registers can be configured to generate triggers by combining the address, data, and pc conditions in a variety of si ngle or dual-level definitions. the trigger event can be programmed to generate a processor halt or in itiate a debug interrupt exception. to support program trace, the version 2 debug modul e provides processor stat us (pst[3:0]) and debug data (ddata[3:0]) ports. these buses and the clkout output provi de execution status, captured operand data, and branch target a ddresses defining the dynamic execution path of the processor at the cpu?s clock rate. 1.1.2 system control module this section details the functi onality of the system control module (scm) which provides the programming model for the system ac cess control unit (sacu), the sy stem bus arbiter, a 32-bit core watchdog timer (cwt), and the syst em control registers and logic. specifically, the system control includes the internal peripheral system base addre ss register (ipsbar), the processor?s dual-port ram mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 overview freescale semiconductor 1-9 base address register (rambar), a nd system control registers that include low-power and core watchdog timer control. 1.1.3 external interface module (eim) the external interface module handles the transfer of information between the internal core and memory, peripherals, or other processing elemen ts in the external address space. programmable chip-select outputs provi de signals to enable external memory and peripheral circuits, providing all handshaking a nd timing signals for automatic wait-s tate insertion and data bus sizing. base memory address and block size are programmable, with some restrictions. for example, the starting address must be on a boundary that is a multiple of the block size. each chip select can be configured to provide read and write enable signals suitable for use with most popular static rams an d peripherals. data bus width (8-bit, 16-bit, or 32-bit) is programmable on all ch ip selects, and further decoding is available for protection from us er mode access or read-only access. 1.1.4 chip select programmable chip select outputs pr ovide a glueless connection to external memory and peripheral circuits, providing al l handshaking and timin g signals for automatic wait-state insertion and data bus sizing. 1.1.5 power management the mcf5282 incorporates several low-power modes of operation which are entered under program control and exited by several extern al trigger events. an integrated power-on reset (por) circuit monitors the input supply and forces an mcu reset as the supply volta ge rises. the lo w voltage detect (lvd) section monitors the supply voltage and is confi gurable to force a reset or interrupt condition if it falls below the lvd trip point. the ram standby switch provides power to ram when the supply voltage is higher than the standby voltage. if the supply voltage to chip falls below the standby battery voltage, the ram is switched over to the standby supply. 1.1.6 general input/output ports all of the pins associated with the external bus inte rface may be used for several different functions. their primary function is to provide an external memory interf ace to access off-chip resources. when not used for this function, all of th e pins may be used as general-purpose digita l i/o pins. in some cases, the pin function is set by the operating mode, and the alternate pin functions are not supported. the digital i/o pins on the mcf5282 are grouped into 8- bit ports. some ports do not use all eight bits. each port has registers that configure, monitor, and control the port pins. 1.1.7 interrupt cont rollers (intc0/intc1) there are two interrupt controller s on the mcf5282, each of which can support up to 63 in terrupt sources for a total of 126. each interrupt contro ller is organized as 7 levels with 9 interrupt sources per level. each interrupt source has a unique interr upt vector, and 56 of the 63 sources of a given controller provide a programmable level [1-7] and priority within the level. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 overview 1-10 freescale semiconductor 1.1.8 sdram controller the sdram controller prov ides all required signals for glue less interfacing to a variety of jedec-compliant sdram devices. sras/scas addre ss multiplexing is softwa re configurable for different page sizes. to maintain refresh capability wit hout conflicting with c oncurrent accesses on the address and data buses, sras , scas , dramw , sdram_cs [1:0], and scke ar e dedicated sdram signals. 1.1.9 test access port the mcf5282 supports circuit board te st strategies based on the test technology committee of ieee and the joint test action group (jtag). the test logic in cludes a test access port (tap) consisting of a 16-state controller, an instruction register , and three test regist ers (a 1-bit bypass register, a 256-bit boundary-scan register, and a 32-bit id re gister). the boundary scan regi ster links the device?s pins into one shift register. test logic, implemented using st atic logic design, is independen t of the device system logic. the mcf5282 implementation supports the following: ? perform boundary-scan operations to test circuit board electrical continuity ? sample mcf5282 system pins during operation and transparently shift out the result in the boundary scan register ? bypass the mcf5282 for a given circuit board test by effectively reducing the boundary-scan register to a single bit ? disable the output drive to pi ns during circuit-board testing ? drive output pins to stable levels 1.1.10 uart modules the mcf5282 contains three full- duplex uarts that function indepe ndently. the three uarts can be clocked by the system clock, eliminati ng the need for an external crystal. each uart has the following features: ? each can be clocked by the syst em clock, eliminating a need for an external uart clock ? full-duplex asynchronous/synchronous receiver/transmitter channel ? quadruple-buffered receiver ? double-buffered transmitter ? independently programmable receiver and transmitter clock sources ? programmable data format: ? 5?8 data bits plus parity ? odd, even, no parity, or force parity ? one, one-and-a-half, or two stop bits ? each channel programmable to normal (full-duplex ), automatic echo, local loop-back, or remote loop-back mode ? automatic wake-up mode for multidrop applications ? four maskable interrupt conditions ? all three uarts have dma request capability ? parity, framing, and overrun error detection ? false-start bit detection ? line-break detection and generation mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 overview freescale semiconductor 1-11 ? detection of breaks originating in the middle of a character ? start/end break interrupt/status 1.1.11 dma timers (dtim0-dtim3) there are four independent, dma-transfer-gener ating 32-bit timers (dtim0, dtim1, dtim2, dtim3) on the mcf5282. each timer module in corporates a 32-bit timer with a separate register set for configuration and control. the timers can be configured to operate from the system clock or from an external clock source using one of the dtinx signals. if the system clock is selected, it can be divided by 16 or 1. the selected cloc k is further divided by a user-programma ble 8-bit prescaler which clocks the actual timer count er register (tcr n). each of these timers can be confi gured for input capture or reference compare mode. by configuring the inte rnal registers, each timer may be configured to assert an external signal, generate an interrupt on a partic ular event, or cause a dma transfer. 1.1.12 general-purpose timers (gpta/gptb) the two general-purpose tim ers (gpta and gptb) are 4- channel timer modules. each timer consists of a 16-bit programmable counter driven by a 7-stage programmable prescaler. each of th e four channels for each timer can be configured for input capture or output compare. additionally, one of the channels, channel 3, can be configured as a pulse accumulator. a timer overflow function allows so ftware to extend the timing capability of the system beyond the 16-bit range of the counter. the input cap ture and output compare functions allow simultaneous input waveform measurements and output wa veform generation. the input capture function can capture the time of a selected transition edge. the output compare functi on can generate output wave forms and timer software delays. the 16-bit pulse ac cumulator can operate as a simple event counter or a gated time accumulator. 1.1.13 periodic interrupt timers (pit0-pit3) the four periodic interrupt timers (pit0, pit1, pit2, pi t3) are 16-bit timers that provide precise interrupts at regular intervals with minimal processor intervention. each timer can either count down from the value written in its pit modulus register, or it can be a free-running down-counter. 1.1.14 software watchdog timer the watchdog timer is a 16-bit timer that facilitates recovery fro m runaway code. the watchdog counter is a free-running down-counter that generates a reset on underflow. to prevent a reset, software must periodically restart the countdown. 1.1.15 phase locked loop (pll) the clock module contains a crystal oscillator (osc), phase-locked loop (pll), reduced frequency divider (rfd), status/control registers, a nd control logic. to improve noise im munity, the pll and osc have their own power supply inputs, vddpll and vsspll. all other ci rcuits are powered by the normal supply pins, vdd and vss. 1.1.16 dma controller the direct memory access (dma) c ontroller module provides an efficien t way to move blocks of data with minimal processor interacti on. the dma module provides four ch annels (dma0?dma 3) that allow mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 overview 1-12 freescale semiconductor byte, word, longword or 16-byt e burst line transfers. these transfers are triggered by software, explicitly setting a dcr n [start] bit or the occurrence of a hardwa re event from one of the on-chip peripheral devices, such as a capture event or an out put reference event in a dma timer (dtim n ) for each channel. the dma controller supports dual-a ddress mode to on-chip devices. 1.1.17 reset the reset controller is provided to determine the cause of reset, assert the appropr iate reset signals to the system, and keep track of what cau sed the last reset. the power mana gement registers for the internal low-voltage detect (lvd) circuit ar e implemented in the reset module. there are seven sources of reset: ? external ? power-on reset (por) ? watchdog timer ? phase-locked loop (pll) loss of lock ? pll loss of clock ? software ? low-voltage dete ction (lvd) reset external reset on the rsto pin is software-assertable independent of chip re set state. there are also software-readable status flags indicating the cause of the last reset, and lvd control and status bits for setup and use of lvd reset or interrupt. 1.2 mcf5282-specific features 1.2.1 fast ethernet controller (fec) the mcf5282?s integrated fast ethe rnet controller (fec) performs the full set of ieee 802.3/ethernet csma/cd media access control a nd channel interface functions. the fec supports connection and functionality for the 10/100 mbps 802.3 media independent interface (mii). it requires an external transceiver (phy) to complete the interface to the media. note the mcf5214 and mcf5216 devices do not contain an fec module. 1.2.2 flexcan the flexcan module is a communicat ion controller implementing the can protocol. th e can protocol can be used as an industrial cont rol serial data bus, meeting the sp ecific requirements of real-time processing, reliable operation in a harsh emi environment, cost-effect iveness, and required bandwidth. flexcan contains 16 message buffers. 1.2.3 i 2 c bus the i 2 c bus is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange, minimizing the in terconnection between devices. this bus is suitable for appl ications requiring occasional communications over a short distance between many devices. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 overview freescale semiconductor 1-13 1.2.4 queued serial peripheral interface (qspi) the queued serial peripheral interf ace module provides a s ynchronous serial periph eral interface with queued transfer capability. it allows up to 16 transfers to be queued at once, eliminating cpu intervention between transfers. 1.2.5 queued analog-to-digital converter (qadc) the qadc is a 10-bit, unipolar, successive approxima tion converter. a maxi mum of 8 analog input channels can be supported using internal multiplexi ng. a maximum of 18 input channels can be supported in the internal/external multiplexed mode. the qadc consists of an analog front-end and a digital control subs ystem. the analog section includes input pins, an analog multiplexer, and sample and hold analog circuits. the anal og conversion is performed by the digital-to-analog converter (dac) resistor-capacitor arra y and a high-gain comparator. the digital control s ection contains queue contro l logic to sequence the conve rsion process and interrupt generation logic. also incl uded are the periodic/interval timer, cont rol and status regi sters, the 64-entry conversion command word (ccw) tabl e, and the 64-entry result table. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 overview 1-14 freescale semiconductor mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor 2-1 chapter 2 coldfire core 2.1 introduction this section describes the organiza tion of the version 2 (v2) coldfire ? processor core and an overview of the program-visible registers. fo r detailed information on instructions , see the isa_a+ definition in the coldfire family programmer?s reference manual . 2.1.1 overview as with all coldfire cores, the v2 coldfire core is comprised of tw o separate pipelines decoupled by an instruction buffer. figure 2-1. v2 coldfire core pipelines the instruction fetch pipeline (ifp) is a two-stage pi peline for prefetching inst ructions. the prefetched instruction stream is then gated into the two-stag e operand execution pipeline (oep), which decodes the instruction instruction fifo decode & select, address iag ic ib dsoc agex instruction buffer address generation fetch cycle generation, execute operand fetch instruction operand pipeline execution fetch pipeline address [ :0] 31 read data[31:0] write data[31:0] mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire core 2-2 freescale semiconductor instruction, fetches the required operands and then executes the required function. because the ifp and oep pipelines are decoupled by an inst ruction buffer serving as a fifo que ue, the ifp is able to prefetch instructions in advance of their actual use by the oep thereby minimizing time stalled waiting for instructions. the v2 coldfire core pipeline stages include the following: ? two-stage instruction fetch pipeline (ifp ) (plus optional instruction buffer stage) ? instruction address genera tion (iag) ? calculates th e next prefetch address ? instruction fetch cycle (i c)?initiates prefetch on the processor?s local bus ? instruction buffer (ib) ? optional buffer stage minimizes fetch latenc y effects using fifo queue ? two-stage operand execution pipeline (oep) ? decode and select/operand fetch cycle (dsoc)?decodes instructions and fetches the required components for eff ective address calculation, or the operand fetch cycle ? address generation/execute cycle (agex)?cal culates operand addre ss or executes the instruction when the instruction buffer is empty, opcodes are lo aded directly from the ic cycle into the operand execution pipeline. if the buffer is not empty, the ifp stores the contents of the fetched instruction in the ib until it is required by the oep. for register-to-register and register-to-memory store operations , the instruction passes through both oep stages once. for memory-to-register and read-modi fy-write memory operations, an instruction is effectively staged through the oep twice: the first time to calculate the effectiv e address and initiate the operand fetch on the processor?s local bus, and the se cond time to complete the operand reference and perform the required function defined by the instruction. the resulting pipeline and local bus structure allow the v2 coldfire core to deliver sustained high performance across a variety of demanding embedded applications. 2.2 memory map/register description the following sections describe the processor registers in the user and supervisor programming models. the programming model is selected ba sed on the processor privilege level (user mode or supervisor mode) as defined by the s bit of the status register (sr). table 2-1 lists the processor registers. the user-programming model consis ts of the following registers: ? 16 general-purpose 32-bi t registers (d0?d7, a0?a7) ? 32-bit program counter (pc) ? 8-bit condition code register (ccr) ? emac registers : ? four 48-bit accumulator regist ers partitioned as follows: ? four 32-bit accumulators (acc0?acc3) ? eight 8-bit accumulator extension bytes (two per accumulator). these are grouped into two 32-bit values for load and store op erations (accext01 and accext23). (described fully in chapter 3, ?enhanced multipl y-accumulate unit (emac mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire core freescale semiconductor 2-3 accumulators and extension bytes can be loade d, copied, and stored, a nd results from emac arithmetic operations ge nerally affect the entire 48-bit destination. ? one 16-bit mask register (mask) ? one 32-bit status register (macsr) includi ng four indicator bits signaling product or accumulation overflow (one for each accumulator: pav0?pav3) the supervisor programming model is to be used only by system control software to implement restricted operating system functions, i/o control, and memory management. all accesses that af fect the control features of coldfire pro cessors are in the supervisor programmi ng model, which consists of registers available in user mode as well as the following control registers: ? 16-bit status register (sr) ? 32-bit supervisor stack pointer (ssp) ? 32-bit vector base register (vbr) ? 32-bit cache control register (cacr) ? 32-bit access control re gisters (acr0, acr1) table 2-1. coldfire core programming model bdm 1 register width (bits) access reset value written with movec section/page supervisor/user access registers load: 0x080 store: 0x180 data register 0 (d0) 32 r/w 0xcf20_6080 no 2.2.1/2-4 load: 0x081 store: 0x181 data register 1 (d1) 32 r/w 0x13b0_1080 no 2.2.1/2-4 load: 0x082?7 store: 0x182?7 data register 2?7 (d2?d7) 32 r/w undefined no 2.2.1/2-4 load: 0x088?8e store: 0x188?8e address register 0?6 (a0?a6) 32 r/w undefined no 2.2.2/2-4 load: 0x08f store: 0x18f supervisor/user a7 stack pointer (a7) 32 r/w undefined no 2.2.3/2-5 0x804 mac status register (macsr) 32 r/w 0x0000_0000 no 3.2.1/3-3 0x805 mac address mask regist er (mask) 32 r/w 0xffff_ffff no 3.2.2/3-5 0x806, 0x809, 0x80a, 0x80b mac accumulators 0?3 (acc0?3) 32 r/w undefined no 3.2.3/3-6 0x807 mac accumulator 0,1 extension bytes (accext01) 32 r/w undefined no 3.2.4/3-7 0x808 mac accumulator 2,3 extension bytes (accext23) 32 r/w undefined no 3.2.4/3-7 0x80e condition code register (ccr) 8 r/w undefined no 2.2.4/2-6 ? two 32-bit memory base addre ss registers (rambar, flashbar) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire core 2-4 freescale semiconductor 2.2.1 data registers (d0?d7) d0?d7 data registers ar e for bit (1-bit), byte (8-bit ), word (16-bit) and longwor d (32-bit) operations; they can also be used as index registers. note registers d0 and d1 contai n hardware configuration details after reset. see section 2.3.4.15, ?reset exception? for more details. 2.2.2 address registers (a0?a6) these registers can be used as softwa re stack pointers, index registers, or base address regi sters. they can also be used for word and longword operations. 0x80f program counter (pc) 32 r/w contents of location 0x0000_0004 no 2.2.5/2-7 supervisor access only registers 0x002 cache control register (cacr) 32 r/w 0x0000_0000 yes 2.2.6/2-7 0x004?5 access control register 0?1 (acr0?1) 32 r/w see section yes 2.2.7/2-7 0x800 user/supervisor a7 stack pointer (other_a7) 32 r/w contents of location 0x0000_0000 no 2.2.3/2-5 0x801 vector base register (vbr) 32 r/w 0x0000_0000 yes 2.2.8/2-7 0x80e status register (sr) 16 r/w 0x27-- no 2.2.9/2-8 0xc04 flash base address register (flashbar) 32 r/w 0x0000_0000 yes 2.2.10/2-8 0xc05 ram base address regist er (rambar) 32 r/w see section yes 2.2.10/2-8 1 the values listed in this column represent the rc field used when accessing the core registers via the bdm port. for more information see chapter 30, ?debug support? . bdm: load: 0x080 + n; n = 0-7 (d n ) store: 0x180 + n; n = 0-7 (d n ) access: user read/write bdm read/write 313029282726252423222120191817161514131211109876543210 r data w reset (d2-d7) ???????????????????????????????? reset (d0, d1) see section 2.3.4.15, ?reset exception? figure 2-2. data registers (d0?d7) table 2-1. coldfire core programming model (continued) bdm 1 register width (bits) access reset value written with movec section/page mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire core freescale semiconductor 2-5 2.2.3 supervisor/user stack pointers (a7 and other_a7) this coldfire architecture supports two independent stack pointer (a7) registers?the supervisor stack pointer (ssp) and the user stac k pointer (usp). the hardware implementation of these two program-visible 32-bit registers does not identify one as the ssp and the other as the usp. instead, the hardware uses one 32-bit register as the active a7 and the other as other_a7. thus, the register contents are a function of the processor operat ion mode, as shown in the following: if sr[s] = 1 then a7 = supervisor stack pointer other_a7 = user stack pointer else a7 = user stack pointer other_a7 = supervisor stack pointer the bdm programming model supports direct reads and writes to a7 and other_a7. it is the responsibility of the extern al development system to determine, ba sed on the setting of sr[s], the mapping of a7 and other_a7 to the two program-visible definitions (ssp and usp) . this functionality is enabled by setting the enable user st ack pointer bit, cacr[eu sp]. if this bit is cl eared, only a single stack pointer (a7), defined for coldfire isa_a, is available. eusp is cleared at reset. to support dual stack pointers, the following two supervisor instructions are included in the coldfire instruction set architectur e to load/store the usp: move.l ay,usp;move to usp move.l usp,ax;move from usp these instructions ar e described in the coldfire family programmer?s reference manual . all other instruction references to the stack pointer, expl icit or implicit, access th e active a7 register. note the ssp is loaded during reset exception processing with the contents of location 0x0000_0000. bdm: load: 0x088 + n; n =0?6 (a n ) store: 0x188 + n; n =0?6 (a n ) access: user read/write bdm read/write 313029282726252423222120191817161514131211109876543210 r address w reset???????????????????????????????? figure 2-3. address registers (a0?a6) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire core 2-6 freescale semiconductor 2.2.4 condition code register (ccr) the ccr is the lsb of the processor status register (sr). bits 4?0 act as indicator flags for results generated by processor operations. th e extend bit (x) is also an input operand during multiprecision arithmetic computations. the ccr register must be explicitly loaded after reset and before any compare (cmp), bcc, or scc instructions are executed. bdm: load: 0x08f (a7) store: 0x18f (a7) 0x800 (other_a7) access: a7: user or bdm read/write other_a7: supervisor or bdm read/write 313029282726252423222120191817161514131211109876543210 r address w reset???????????????????????????????? figure 2-4. stack pointer registers (a7 and other_a7) bdm: lsb of status register (sr) access: user read/write bdm read/write 76543210 r 0 0 0 x n z v c w r e s e t :0 0 0 ????? figure 2-5. condition code register (ccr) table 2-2. ccr field descriptions field description 7?5 reserved, must be cleared. 4 x extend condition code bit. set to the c-bit value for arithmetic operations; otherwise not affected or set to a specified result. 3 n negative condition code bit. set if most signific ant bit of the result is set; otherwise cleared. 2 z zero condition code bit. set if resu lt equals zero; otherwise cleared. 1 v overflow condition code bit. set if an ar ithmetic overflow occurs implying the result cannot be represented in operand size; otherwise cleared. 0 c carry condition code bit. set if a carry out of the oper and msb occurs for an addition or if a borrow occurs in a subtraction; otherwise cleared. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire core freescale semiconductor 2-7 2.2.5 program counter (pc) the pc contains the currently exec uting instruction address. during instruction execution and exception processing, the processor automatically increments contents of the pc or places a new value in the pc, as appropriate. the pc is a base address for pc-relative operand addressing. the pc is initially loaded during reset exception processing with the contents of location 0x0000_0004. 2.2.6 cache control register (cacr) the cacr controls operation of the instruction/data cache memories. it includes bits for enabling, freezing, and invalidating cache contents. it also incl udes bits for defining the default cache mode and write-protect fields. th e cacr is described in section 4.2.1, ?cache control register (cacr).? 2.2.7 access control registers (acr n ) the access control registers define attributes for user -defined memory regions. these attributes include the definition of cache mode, write protect, and buffer write enables. the acrs are described in section 4.2.2, ?access control regi sters (acr0, acr1).? 2.2.8 vector base register (vbr) the vbr contains the base address of the exception vector table in memory. to access the vector table, the displacement of an exception vector is added to the value in vbr. the lower 20 bits of the vbr are not implemented by coldfire processo rs. they are assumed to be zero, forcing the table to be aligned on a 1 mb boundary. bdm: 0x80f (pc) access: user read/write bdm read/write 313029282726252423222120191817161514131211109876543210 r address w reset???????????????????????????????? figure 2-6. program counter register (pc) bdm: 0x801 (vbr) access: supervisor read/write bdm read/write 313029282726252423222120191817161514131211109876543210 r base address 0 0 0 0 0 00000000 0 00 0 0 00 w reset00000000000000000000000000000000 figure 2-7. vector base register (vbr) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire core 2-8 freescale semiconductor 2.2.9 status register (sr) the sr stores the processor status and includes the ccr, the interrupt priority mask, and other control bits. in supervisor mode, software can access the enti re sr. in user mode, only the lower 8 bits (ccr) are accessible. the control bits indicate the following states for the proces sor: trace mode (t bit), supervisor or user mode (s bit), and ma ster or interrupt state (m bit). all defined bits in th e sr have read/write access when in supervisor mode. the lower byte of the sr (t he ccr) must be loaded explicitly after reset and before any compare (cmp), bcc, or scc instructions execute. bdm: 0x80e (sr) access: supervisor read/write bdm read/write system byte condition code register (ccr) 1514131211109876543210 r t 0 s m 0 i 000 x n zvc w reset00100111000 ????? figure 2-8. status register (sr) table 2-3. sr field descriptions field description 15 t trace enable. when set, the processor performs a trace exception after every instruction. 14 reserved, must be cleared. 13 s supervisor/user state. 0user mode 1 supervisor mode 12 m master/interrupt state. bit is cleared by an interrupt except ion and software can set it during execution of the rte or move to sr instructions. 11 reserved, must be cleared. 10?8 i interrupt level mask. defines current interrupt level. interrupt requests are inhibited for all priority levels less than or equal to current level, except edge-sensitiv e level 7 requests, which cannot be masked. 7?0 ccr refer to section 2.2.4, ?condition code register (ccr)? . 2.2.10 memory base address registers (rambar, flashbar) the memory base address registers are used to specify the base address of the internal sram and flash modules and indicate the types of re ferences mapped to each. each base address register includes a base address, write-protect bit, address space mask bits, and an enable bit. flashbar determines the base address of the on-chip flash, and ra mbar determines the base addre ss of the on-chip ram. for more information, refer to section 5.3.1, ?sram base address register (rambar)? and section 6.3.2, ?flash base address register (flashbar)? . mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire core freescale semiconductor 2-9 2.3 functional description 2.3.1 version 2 coldfire microarchitecture from the block diagram in figure 2-1 , the non-harvard architecture of th e processor is readily apparent. the processor interfaces to the local memory subsys tem via a single 32-bit addr ess and two unidirectional 32-bit data buses. this structure minimizes the core size without compromising performance to a large degree. a more detailed view of the hardware struct ure within the two pipelines is presented in figure 2-9 and figure 2-10 below. in these diagrams, the internal struct ure of the instruction fetch and operand execution pipelines is shown: figure 2-9. version 2 coldfire processor instruction fetch pipeline diagram iag ic ib core bus address core bus read data opword extension 1 extension 2 fifo ib +4 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire core 2-10 freescale semiconductor figure 2-10. version 2 coldfire processor operand execution pipeline diagram the instruction fetch pipeline prefet ches instructions from local memory using a two-stage structure. for sequential prefetches, the next instruction address is generated by adding four to the last prefetch address. this function is performed during th e iag stage and the resulting prefet ch address gated onto the core bus (if there are no pending operand memory accesses assigne d a higher priority). afte r the prefetch address is driven onto the core bus, the instruction fetch cy cle accesses the appropriate local memory and returns the instruction read data back to the ifp during the cycle. if the accessed data is not present in a local memory (e.g., an instruction cache miss, or an external access cycle is required), the ifp is stalled in the ic stage until the referenced data is available. as the pr efetch data arrives in the if p, it can be loaded into the fifo instruction buffer or gated directly into the oep. the v2 design uses a simple static conditional branch prediction algorithm (forward-assumed as not-taken, backward-assumed as take n), and all change-of-flow operations are calculated by the oep and the target instruction address fed back to the ifp. the ifp and oep are decoupled by the fifo instruction buffer, allowing instruction prefetching to occur with the available core bus bandwidth not used fo r operand memory accesses. for the v2 design, the instruction buffer contains three 32-bit locations. consider the operation of the oep for three basic classes of non-br anch instructions: ? register-to-register: op ry,rx ? embedded load: op coldfire core freescale semiconductor 2-11 instruction execution is performed in the second stage (ex) in one of the execute engines (e.g., alu, barrel shifter, divider, emac). there are no operand memory accesses associated with this class of instructions, and the execution time is typically a single machine cycle. see figure 2-11 . figure 2-11. v2 oep register-to-register for memory-to-register (embedded-load) instructions , the instruction is effectively staged through the oep twice with a basic execution time of three cycles. first, the instruction is decoded and the components of the operand address (base register from the rg f and displacement) are selected (ds). second, the operand effective address is generated using the al u execute engine (ag). third, the memory read operand is fetched from the core bus, while any required register operand is simultaneously fetched (oc) from the rgf. finally, in the fourth cycle, the inst ruction is executed (ex). the heavily-used 32-bit load instruction ( move.l coldfire core 2-12 freescale semiconductor figure 2-12. v2 oep embedded-load part 1 figure 2-13. v2 oep embedded-load part 2 for register-to-memory (store) opera tions, the stage functions (ds/oc, ag/ex) are effectively performed simultaneously allowing single-cycle execution. see figure 2-14 where the effective address is of the form coldfire core freescale semiconductor 2-13 for read-modify-write instructions, the pipeline ef fectively combines an em bedded-load with a store operation for a three-cycle execution time. figure 2-14. v2 oep register-to-memory the pipeline timing diagrams of figure 2-15 depict the execution template s for these three classes of instructions. in these diagrams, the x-axis represents time, and the various instruct ion operations are shown progressing down the operand execution pipeline. operand execution pipeline dsoc agex opword extension 1 extension 2 core bus read data core bus address core bus write rgf data ax d16 ry coldfire core 2-14 freescale semiconductor figure 2-15. v2 oep pipe line execution templates 2.3.2 instruction set architecture (isa_a+) the original coldfire instructi on set architecture (isa _a) was derived from the m68000 family opcodes based on extensive analysis of em bedded application code. the isa was optimized for code compiled from high-level languages where the dominant opera nd size was the 32-bit integer declaration. this approach minimized processor comp lexity and cost, while providing ex cellent performance for compiled applications. after the initial coldfire compilers were created, deve lopers noted there were ce rtain isa additions that would enhance code density and overa ll performance. additi onally, as users implem ented coldfire-based designs into a wide range of embedded systems, they found certain frequently-used instruction sequences that could be improved by the creat ion of additional instructions. the original isa definition minimize d support for instructions referencing byte- a nd word-sized operands. full support for the move byte and move word in structions was provided, but the only other opcodes supporting these data types are clr (c lear) and tst (test). a set of in struction enhancements has been implemented in subsequent isa re visions, isa_b and isa_c. the new opcodes primarily addressed three areas: 1. enhanced support for byte and word-sized operands 2. enhanced support for position-independent code 3. miscellaneous instruction additi ons to address new functionality core clock register-to-register core bus embedded-load core bus register-to-memory op read core bus op write oep.dsoc oc next oep.agex ex oep.dsoc ds oc next oep.agex ex ag oep.dsoc dsoc next oep.agex agex (store) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire core freescale semiconductor 2-15 table 2-4 summarizes the instructions a dded to revision isa_a to form revision isa_a+. for more details see the coldfire family programmer?s reference manual . 2.3.3 exception processing overview exception processing for coldfire pr ocessors is streamlined for perfor mance. the coldfire processors differ from the m68000 family because they include: ? a simplified exception vector table ? reduced relocation capabilities using the vector-base register ? a single exception stack frame format ? use of separate system stack point ers for user and supervisor modes. all coldfire processors use an instruction rest art exception model. however, version 2 coldfire processors require more software support to recover from certain access errors. see section 2.3.4.1, ?access error exception ? for details. exception processing includes all actions from fault condition detection to the initiation of fetch for first handler instruction. exception processing is comprised of four major steps: 1. the processor makes an internal copy of the sr and then enters supervisor mode by setting the s bit and disabling trace mode by clearing the t bit. the interrupt exception also forces the m bit to be cleared and the interrupt priority mask to set to cu rrent interrupt request level. table 2-4. instruction enhancements over revision isa_a instruction description bitrev the contents of the destinati on data register are bit-reversed; new dn[31] equals old dn[0], new dn[30] equals old dn[1],..., new dn[0] equals old dn[31]. byterev the contents of the destination data regist er are byte-reversed; new dn[31:24] equals old dn[7:0],..., new dn[7:0] equals old dn[31:24]. ff1 the data register, dn, is scanned, beginning fr om the most-significant bit (dn[31]) and ending with the least-significant bit (dn[0]), searching for the first set bit. the data register is then loaded with the offset count from bi t 31 where the first set bit appears. move from usp usp destination register move to usp source register usp stldsr pushes the contents of the status register on to the stack and then reloads the status register with the immediate data value. 2. the processor determines the exception vector number. for all faults except interrupts, the processor performs this calcu lation based on exception type. for interrupts, the processor performs an interrupt-acknowledge (iack) bus cycle to obtain the vector number from the interrupt controller. the iack cycle is mapped to special locations within the interrupt controller?s address space with the in terrupt level encoded in the address. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire core 2-16 freescale semiconductor 3. the processor saves the current context by creating an exception stack frame on the system stack. the exception stack frame is crea ted at a 0-modulo-4 addr ess on top of the system stack pointed to by the supervisor stack pointer (ssp). as shown in figure 2-16 , the processor uses a simplified fixed-length stack frame for all exceptions. the exception type determines whether the program counter placed in the exception stack frame define s the location of the faulting instruction (fault) or the address of the next inst ruction to be executed (next). 4. the processor calculates the addr ess of the first instruction of the exception handler. by definition, the exception vector tabl e is aligned on a 1 mb boundary. this instruction addres s is generated by fetching an exception vector from the table located at the address defined in th e vector base register. the index into the exception table is calculated as (4 vector number). after the exception vector has been fetched, the vector contents determine th e address of the first in struction of the desired handler. after the instruction fetch for the firs t opcode of the handler has initiated, exception processing terminates and normal instruct ion processing continues in the handler. the table contains 256 exception vectors; the first 64 are defined for the core and the remaining 192 are device-specific pe ripheral interrupt vectors. see chapter 10, ?interrupt controller modules? for details on the device-specific interrupt sources. table 2-5. exception vector assignments vector number(s) vector offset (hex) stacked program counter assignment 0 0x000 ? initial supervisor stack pointer 1 0x004 ? initial program counter 2 0x008 fault access error 3 0x00c fault address error 4 0x010 fault illegal instruction 5 0x014 fault divide by zero 6?7 0x018?0x01c ? reserved 8 0x020 fault privilege violation 9 0x024 next trace 10 0x028 fault unimplemented line-a opcode 11 0x02c fault unimplemented line-f opcode 12 0x030 next debug interrupt 13 0x034 ? reserved 14 0x038 fault format error 15?23 0x03c?0x05c ? reserved 24 0x060 next spurious interrupt 25?31 0x064?0x07c ? reserved all coldfire processors support a 1024-byte vector table aligned on any 1 mbyte a ddress boundary (see table 2-5 ). mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire core freescale semiconductor 2-17 all coldfire processors inhibit interrupt sampling dur ing the first instruction of all exception handlers. this allows any handler to disable interrupts effectiv ely, if necessary, by raisi ng the interrupt mask level contained in the status re gister. in addition, the isa_a+ architec ture includes an instruction (stldsr) that stores the current interrupt mask level and loads a value into the sr. this instruction is specifically intended for use as the first instruction of an interr upt service routine that services multiple interrupt requests with different interrupt levels. for more details, see coldfire family programmer?s reference manual . 2.3.3.1 exception stack frame definition figure 2-16 shows exception stack frame. the first longword contains the 16-bit format/vector word (f/v) and the 16-bit status register, and the second longword contains the 32-bit program counter address. the 16-bit format/vector word contains three unique fields: ? a 4-bit format field at the top of the system stack is always written with a value of 4, 5, 6, or 7 by the processor, indicating a two-longword frame format. see table 2-6 . ? there is a 4-bit fault st atus field, fs[3:0], at the top of the system stack. th is field is defined for access and address errors only and written as zeros for all other exceptions. see table 2-7 . 32?47 0x080?0x0bc next trap # 0-15 instructions 48?63 0x0c0?0x0fc ? reserved 64?255 0x100?0x3fc next device-specific interrupts 1 fault refers to the pc of the instruction that caused the exception. next refers to the pc of the instruction that follows th e instruction that caused the fault. 313029282726252423222120191817161514131211109876543210 ssp format fs[3:2] vector fs[1:0] status register + 0x4 program counter figure 2-16. exception stack frame form table 2-6. format field encodings original ssp @ time of exception, bits 1:0 ssp @ 1st instruction of handler format field 00 original ssp - 8 0100 01 original ssp - 9 0101 10 original ssp - 10 0110 11 original ssp - 11 0111 table 2-5. exception vector assignments (continued) vector number(s) vector offset (hex) stacked program counter assignment mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire core 2-18 freescale semiconductor ? the 8-bit vector number, vector[7 :0], defines the exception type a nd is calculated by the processor for all internal faults and represents the value supplied by the interrupt controller in case of an interrupt. see table 2-5 . 2.3.4 processor exceptions 2.3.4.1 access error exception the exact processor response to an access error de pends on the memory reference being performed. for an instruction fetch, the processor pos tpones the error reporting until the faulted reference is needed by an instruction for execution. therefore, faults during instruction prefetches followed by a change of instruction flow do not generate an exception. when th e processor attempts to ex ecute an instruction with a faulted opword and/or extension word s, the access error is signaled a nd the instruction aborted. for this type of exception, the programming m odel has not been altered by the instruction generating the access error. if the access error occurs on an operand read, the proc essor immediately aborts the current instruction?s execution and initiates exception proces sing. in this situation, any address register upda tes attributable to the auto-addressing modes, (for example, (an)+,-(an )), have already been performed, so the programming model contains the updated an value. in addition, if an access error occurs during a movem instruction loading from memory, any registers already updated be fore the fault occurs contain the operands from memory. the v2 coldfire processor uses an imprecise repor ting mechanism for access errors on operand writes. because the actual write cycle may be decoupled from the processo r?s issuing of the operation, the signaling of an access error appears to be decoupled from the instruction that generated the write. accordingly, the pc contai ned in the exception stack frame merely represents the location in the program when the access error was signaled. al l programming model updates associat ed with the write instruction are completed. the nop instruction can collect access errors for writes. this instruction delays its table 2-7. fault status encodings fs[3:0] definition 00 xx reserved 0100 error on instruction fetch 0101 reserved 011x reserved 1000 error on operand write 1001 attempted write to write-protected space 101x reserved 1100 error on operand read 1101 reserved 111x reserved mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire core freescale semiconductor 2-19 execution until all previous operations, including all pending write operations, are complete. if any previous write terminates with an access error, it is guaranteed to be reported on the nop instruction. 2.3.4.2 address error exception any attempted execution tran sferring control to an odd instruction addr ess (if bit 0 of the target address is set) results in an address error exception. any attempted use of a word-sized i ndex register (xn.w) or a scale factor of eight on an indexed effective addressing mode generates an address error, as does an attempted execution of a full-format indexed addressing mode, which is defined by bit 8 of extension word 1 being set. if an address error occurs on a jsr instruction, the version 2 coldfire processor calculates the target address then the return address is pushed onto the stac k. if an address error occurs on an rts instruction, the version 2 coldfire processor overwrites the faul ting return pc with the address error stack frame. 2.3.4.3 illegal instruction exception the coldfire variable-length instruct ion set architecture supports three instruction sizes: 16, 32, or 48 bits. the first instruction word is known as the operation word (or opword), while the optional words are known as extension word 1 and extension word 2. the opword is further subdivided into three sections: the upper four bits segment the entire isa into 16 instructi on lines, the next 6 bits define the operation mode (opmode), and the low-order 6 bits define the effective address. see figure 2-17 . the opword line definition is shown in table 2-8 . figure 2-17. coldfire instruction operation word (opword) format 1514131211109876543210 line opmode effective address mode register table 2-8. coldfire opword line definition opword[line] instruction class 0x0 bit manipulation, arithmetic and logical immediate 0x1 move byte 0x2 move long 0x3 move word 0x4 miscellaneous 0x5 add (addq) and subtract quick (subq), set according to condition codes (scc) 0x6 pc-relative change-of-flow instructions conditional (bcc) and unconditional (bra) branches, subroutine calls (bsr) 0x7 move quick (moveq), move with sign extension (mvs) and zero fill (mvz) 0x8 logical or (or) 0x9 subtract (sub), subtract extended (subx) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire core 2-20 freescale semiconductor in the original m68000 isa definition, lines a and f were effe ctively reserved for user-defined operations (line a) and co-processor instructions (line f). accordingly, there are two unique exception vectors associated with illegal opw ords in these two lines. any attempted execution of an illegal 16-bit opcode (e xcept for line-a and line-f opcodes) generates an illegal instruction excepti on (vector 4). additionally, any attempted execution of any non-mac line-a and most line-f opcodes generate their unique excepti on types, vector numbers 10 and 11, respectively. coldfire cores do not provide illegal instruction de tection on the extension wo rds on any instruction, including movec. 2.3.4.4 divide-by-zero attempting to divide by zero causes an exception (vector 5, offset equal 0x014). 2.3.4.5 privilege violation the attempted execution of a supervisor mode instruction while in user mode generates a privilege violation exception. see coldfire programmer?s reference manual for a list of supervisor-mode instructions. there is one special case involvi ng the halt instruction. normally, th is opcode is a supervisor mode instruction, but if the debug module's csr[uhe] is set, then this instruction can be also be executed in user mode for debugging purposes. 2.3.4.6 trace exception to aid in program development, all coldfire proce ssors provide an instruction-by-instruction tracing capability. while in trace mode, indicated by setting of the sr[t] bit, the completion of an instruction execution (for all but the stop instruction) signals a trace exception. this func tionality allows a debugger to monitor program execution. the stop instruction has the following effects: 1. the instruction before th e stop executes and then generates a trace exception. in the exception stack frame, the pc points to the stop opcode. 2. when the trace handler is exited, the stop instru ction executes, loading th e sr with the immediate operand from the instruction. 0xa emac, move 3-bit quick (mov3q) 0xb compare (cmp), exclusive-or (eor) 0xc logical and (and), multiply word (mul) 0xd add (add), add extended (addx) 0xe arithmetic and logical shifts (asl, asr, lsl, lsr) 0xf cache push (cpushl), write ddata (wddata), write debug (wdebug) table 2-8. coldfire opword line definition (continued) opword[line] instruction class mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire core freescale semiconductor 2-21 3. the processor then generates a trace exception. the pc in the exce ption stack frame points to the instruction after the stop, and the sr reflects the value loaded in the previous step. if the processor is not in trace mode and execute s a stop instruction where the immediate operand sets sr[t], hardware loads the sr and generates a trace exception. the pc in the exception stack frame points to the instruction after the stop, and the sr reflects the value loaded in step 2. because coldfire processors do not support any hardware stacking of multiple exceptions, it is the responsibility of the operating system to check for tr ace mode after processing ot her exception types. as an example, consider a trap instruction execution wh ile in trace mode. the processor initiates the trap exception and then passes control to the corresponding ha ndler. if the system require s that a trace exception be processed, it is the res ponsibility of the trap except ion handler to check for th is condition (sr[t] in the exception stack frame set) and pass control to the trace handler before returning from the original exception. 2.3.4.7 unimplemented line-a opcode a line-a opcode is defined when bits 15-12 of the opwor d are 0b1010. this excepti on is generated by the attempted execution of an undefined line-a opcode. 2.3.4.8 unimplemented line-f opcode a line-f opcode is defined when bits 15-12 of the op word are 0b1111. this exception is generated when attempting to execute an undefined line-f opcode. 2.3.4.9 debug interrupt see chapter 30, ?debug support ,? for a detailed explanation of this exception, which is generated in response to a hardware breakpoint register trigger. the processor does not generate an iack cycle, but rather calculates the vector numbe r internally (vector num ber 12). additionally, sr [m,i] are unaffected by the interrupt. 2.3.4.10 rte and format error exception when an rte instruction is executed, the processor first examines the 4-bit format field to validate the frame type. for a coldfire core, any attempted rte execution (where the format is not equal to {4,5,6,7}) generates a format error. the exception stack frame for the format error is created without disturbing the original rte frame and the stacked pc pointing to the rte instruction. the selection of the format value provides some limited debug support for porting code from m68000 applications. on m68000 family proc essors, the sr was located at the top of the stack. on those processors, bit 30 of the longword addressed by the syst em stack pointer is typical ly zero. thus, if an rte is attempted using this old format, it generates a format error on a coldfire processor. if the format field defines a valid type, the processor: (1) reloads the sr operand, (2) fetches the second longword operand, (3) adjusts the stack pointer by adding the format value to the auto-incremented address after the fetch of the firs t longword, and then (4) transfers control to the instruction address defined by the second longword operand within the stack frame. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire core 2-22 freescale semiconductor 2.3.4.11 trap instruction exception the trap #n instruction always forces an exception as part of its execution and is useful for implementing system calls. the trap instruction may be used to change from user to supervisor mode. 2.3.4.12 unsupported instruction exception if execution of a valid instruction is attempted but the required hardware is not present in the processor, an unsupported instruction excepti on is generated. the instru ction functionality can th en be emulated in the exception handler, if desired. all coldfire cores record the processor hardware configuration in the d0 register immediately after the negation of reset . see section 2.3.4.15, ?reset exception,? for details. 2.3.4.13 interrupt exception interrupt exception processing includes interrupt recognition and the fetch of the appropriate vector from the interrupt controller using an iack cycle. see ,? for details on the interrupt controller. 2.3.4.14 fault-on-fault halt if a coldfire processor encounters a ny type of fault during the exception processing of another fault, the processor immediately halt s execution with the catast rophic fault-on-fault condition. a reset is required to to exit this state. 2.3.4.15 reset exception asserting the reset input signal (reset ) to the processor causes a reset exception. the reset exception has the highest priority of any excepti on; it provides for system initiali zation and recovery from catastrophic failure. reset also aborts any processing in progress when the re set input is recognized. processing cannot be recovered. the reset exception places the processor in the supe rvisor mode by setting th e sr[s] bit and disables tracing by clearing the sr[t] bit. th is exception also clears the sr[m] bit and sets the processor?s sr[i] field to the highest level (level 7, 0b111). next, the vbr is initialized to zero (0x0000_0000). the control registers specifying the operation of any memories (e.g., cache and/or ram modules) connected directly to the processor are disabled. note other implementation-specific registers are also affected. refer to each module in this reference manual for details on these registers. after the processor is granted the bus, it performs two longword read-bus cycl es. the first longword at address 0x0000_0000 is loaded into the supervisor st ack pointer and the second longword at address 0x0000_0004 is loaded into the program counter. after the initial instruction is fetched from memory, program execution begins at the address in the pc. if an access error or a ddress error occurs before the first instruction is executed, the proces sor enters the fault-on-fault state. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire core freescale semiconductor 2-23 coldfire processors load hardware configurati on information into the d0 and d1 general-purpose registers after system reset. the hardware configuration information is loaded immediately after the reset-in signal is negated. this allows an emulator to read out the cont ents of these registers via the bdm to determine the hardware configuration. information loaded into d0 defines the proc essor hardware configuration as shown in figure 2-18 . bdm: load: 0x080 (d0) store: 0x180 (d0) access: user read-only bdm read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r pf ver rev w reset1100111100100000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r mac divemacfpu0000 isa debug w reset0110000010000000 figure 2-18. d0 hardware configuration info table 2-9. d0 hardware configuration info field description field description 31?24 pf processor family. this field is fixed to a hex value of 0xcf indicating a coldfire core is present. 23?20 ver coldfire core version nu mber. defines the hardware microarchi tecture version of coldfire core. 0001 v1 coldfire core 0010 v2 coldfire core (this is the value used for this device.) 0011 v3 coldfire core 0100 v4 coldfire core 0101 v5 coldfire core else reserved for future use 19?16 rev processor revision number. the default is 0b0000. 15 mac mac present. this bit signals if the optional multiply-accu mulate (mac) execution engine is present in processor core. 0 mac execute engine not present in core. (this is the value used for this device.) 1 mac execute engine is present in core. 14 div divide present. this bit signals if the hardware divider (div) is present in the processor core. 0 divide execute engine not present in core. 1 divide execute engine is present in core. 13 emac emac present. this bit signals if the optional enhanced mu ltiply-accumulate (emac) execution engine is present in processor core. 0 emac execute engine not present in core. 1 emac execute engine is present in core. (this is the value used for this device.) 12 fpu fpu present. this bit signals if the optional floating-poi nt (fpu) execution engine is present in processor core. 0 fpu execute engine not present in core. (this is the value used for this device.) 1 fpu execute engine is present in core. (this is the value used for this device.) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire core 2-24 freescale semiconductor information loaded into d1 defines the local memory hardware configuration as shown in the figure below. 11?8 reserved. 7?4 isa isa revision. defines the instruction-se t architecture (isa) revision level implemented in coldfire processor core. 0000 isa_a 0001 isa_b 0010 isa_c 1000 isa_a+ (this is the value used for this device.) else reserved 3?0 debug debug module revision number. defines revision level of the debug module used in the coldfire processor core. 0000 debug_a 0001 debug_b 0010 debug_c 0011 debug_d 0100 debug_e 1001 debug_b+ 1011 debug_d+ 1111 debug_d+pst buffer else reserved bdm: load: 0x1 (d1) store: 0x1 (d1) access: user read-only bdm read-only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r clsz ccas ccsz flashsz 0 0 0 w reset0001001110110000 1514131211109876543210 rmbsz ucas 0000 sramsz 000 w reset0001000010000000 figure 2-19. d1 hardware configuration info table 2-10. d1 hardware configuration information field description field description 31?30 clsz cache line size. this field is fixed to a hex value of 0x0 indicating a 16-byte cache line size. 29?28 ccas configurable cache associativity. 00 four-way 01 direct mapped (this is the value used for this device) else reserved for future use table 2-9. d0 hardware configuration info field description (continued) field description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire core freescale semiconductor 2-25 2.3.5 instruction execution timing this section presents processor in struction execution times in terms of processor-core clock cycles. the number of operand references for eac h instruction is enclosed in parentheses following the number of processor clock cycles. each timing en try is presented as c(r/w) where: ?c is the number of processor cloc k cycles, including all applicable operand fetches and writes, and all internal core cycles required to complete the instruction execution. 27?24 ccsz configurable cache size. indicates the amount of inst ruction/data cache. the cache configuration options available are 50% instruction/50% data, 100% instruction, or 100% data, and are specified in the cacr register. 0000 no configurable cache 0001 512b configurable cache 0010 1kb configurable cache 0011 2kb configurable cache (this is the value used for this device) 0100 4kb configurable cache 0101 8kb configurable cache 0110 16kb configurable cache 0111 32kb configurable cache else reserved 23?19 flashsz flash bank size. 0000-0111 no flash 1000 64-kb flash 1001 128-kb flash 1010 256-kb flash 1011 512-kb flash (this is the value used for this device) else reserved for future use. 18?16 reserved 15?14 mbsz bus size. defines the width of the coldfire master bus datapath. 00 32-bit system bus datapath (this is the value used for this device) 01 64-bit system bus datapath else reserved 13?8 reserved, resets to 0b010000 7?3 sramsz sram bank size. 00000 no sram 00010 512 bytes 00100 1 kb 00110 2 kb 01000 4 kb 01010 8 kb 01100 16 kb 01110 32 kb 10000 64 kb (this is the value used for this device) 10010 128 kb else reserved for future use 2?0 reserved. table 2-10. d1 hardware configuration information field description (continued) field description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire core 2-26 freescale semiconductor ? r/w is the number of operand reads (r) and writ es (w) required by the in struction. an operation performing a read-modify-write function is denoted as (1/1). this section includes the assumptions concerning the timing values and the execution time details. 2.3.5.1 timing assumptions for the timing data presented in this section, these assumptions apply: 1. the oep is loaded with the opword and all requ ired extension words at the beginning of each instruction execution. this implie s that the oep does not wait for the ifp to supply opwords and/or extension words. 2. the oep does not experience any sequence-related pipeline stalls. the most common example of stall involves consecutive st ore operations, excluding the move m instruction. for all store operations (except movem), certain hardware resources within the processor are marked as busy for two clock cycles after the final decode and select/operand fetch cycle (dsoc) of the store instruction. if a subsequent store instruction is encountered within this 2-cycle window, it is stalled until the resource again becomes available. thus, the maximum pipeline stall involving consecutive store operations is two cycles. th e movem instruction uses a different set of resources and this stall does not apply. 3. the oep completes all memory acc esses without any stall conditions caused by the memory itself. thus, the timing details provided in this section assume that an infi nite zero-wait state memory is attached to the processor core. 4. all operand data accesses are al igned on the same byte boundary as the operand size; for example, 16-bit operands aligned on 0-modulo-2 addre sses, 32-bit operands aligned on 0-modulo-4 addresses. the processor core decomposes mi saligned operand references into a series of aligned accesses as shown in table 2-11 . 2.3.5.2 move instruction execution times table 2-12 lists execution times for move.{b,w} instructions; table 2-13 lists timings for move.l. note for all tables in this section, the execution time of a ny instruction using the pc-relative effective addressing modes is the same for the comparable an-relative mode. table 2-11. misaligned operand references address[1:0] size bus operations additional c(r/w) 01 or 11 word byte, byte 2(1/0) if read 1(0/1) if write 01 or 11 long byte, word, byte 3(2/0) if read 2(0/2) if write 10 long word, word 2(1/0) if read 1(0/1) if write mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire core freescale semiconductor 2-27 the nomenclature xxx.wl refers to both forms of absolute addressing, xxx.w and xxx.l. et with { coldfire core 2-28 freescale semiconductor 2.3.5.3 standard one operand instruction execution times 2.3.5.4 standard two operand instruction execution times table 2-14. one operand instruction execution times opcode coldfire core freescale semiconductor 2-29 asl.l coldfire core 2-30 freescale semiconductor 2.3.5.5 miscellaneous instruction execution times table 2-16. miscellaneous instruction execution times opcode coldfire core freescale semiconductor 2-31 2.3.5.6 emac instruction execution times table 2-17. emac instruction execution times opcode coldfire core 2-32 freescale semiconductor note the execution times for moving the c ontents of the racc, raccext[01,23], macsr, or rmask into a destination location freescale semiconductor 3-1 chapter 3 enhanced multiply-accumulate unit (emac) 3.1 introduction this chapter describes the func tionality, microarchitecture, a nd performance of the enhanced multiply-accumulate (emac) unit in th e coldfire family of processors. 3.1.1 overview the emac design provides a set of dsp operations that can improve the performanc e of embedded code while supporting the integer multiply instructi ons of the baseline coldfire architecture. the mac provides functionality in three related areas: 1. signed and unsigned integer multiplication 2. multiply-accumulate op erations supporting signed and unsigned integer operands as well as signed, fixed-point, and fractional operands 3. miscellaneous register operations the coldfire family supports two mac implementations with different performance levels and capabilities. the original mac features a three-stage execution pipeline optimized for 16-bit operands, with a 16x16 multiply array and a single 32-bit accumula tor. the emac features a four-stage pipeline optimized for 32-bit operands, with a fully pipelined 32 32 multiply array and f our 48-bit accumulators. the first coldfire mac supported signed and unsigned in teger operands and was optimized for 16x16 operations, such as those found in applications including servo control and image compression. as coldfire-based systems proliferated, the desire for more precision on input operands increased. the result was an improved coldfire mac with user-programmable control to opt ionally enable use of fractional input operands. emac improvements target three primary areas: ? improved performance of 32 32 multiply operation. ? addition of three more accumulators to mini mize mac pipeline sta lls caused by exchanges between the accumulator and the pipeline?s general-purpose registers ? a 48-bit accumulation data path to allow a 40-bit product, plus 8 extension bits increase the dynamic number range when implemen ting signal processing algorithms the three areas of functionality are addressed in detail in following sect ions. the logic required to support this functionality is contained in a mac module ( figure 3-1 ). mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 enhanced multiply-accumulate unit (emac) 3-2 freescale semiconductor figure 3-1. multiply-accumulate functionality diagram 3.1.1.1 introduction to the mac the mac is an extension of the basic multiplier in most microprocessors. it is typically implemented in hardware within an architecture and supports rapid execution of signa l processing algor ithms in fewer cycles than comparable non-mac architectures. for example, small di gital filters can tolerate some variance in an algorithm?s execution time, but larg er, more complicated algorithms such as orthogonal transforms may have more demanding speed requirements beyond scope of any processor architecture and may require full dsp implementation. to balance speed, size, and functionali ty, the coldfire mac is optimized for a small set of operations that involve multiplication and cumula tive additions. specifically, the mu ltiplier array is optimized for single-cycle pipelined operations with a possible accu mulation after product gene ration. this functionality is common in many signal processing ap plications. the coldfire core architecture is also modified to allow an operand to be fetched in parallel with a multiply, increasing overall performance for certain dsp operations. consider a typical filtering operation where the filter is defined as in equation 3-1 . eqn. 3-1 here, the output y(i) is determined by past output values and past input values. this is the general form of an infinite impulse response (iir) fi lter. a finite impulse response (fir) filter can be obtained by setting coefficients a(k) to zero. in either case, the operations involved in computing such a filter are multiplies and product summing. to show this point, reduce equation 3-1 to a simple, four-tap fir filter, shown in equation 3-2 , in which the accumulated sum is a past data values and coefficients sum. eqn. 3-2 x + / - operand y operand x shift 0,1,-1 accumulator(s) yi () ak () yi k ? () k1 = n1 ? bk () xi k ? () k0 = n1 ? + = yi () bk () xi k ? () k0 = 3 b0 () xi () b1 () xi 1 ? () b2 () xi 2 ? () b3 () xi 3 ? () +++ == mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 enhanced multiply-accumulate unit (emac) freescale semiconductor 3-3 3.2 memory map/register definition the following table and sectio ns explain the mac registers: 3.2.1 mac status register (macsr) the mac status register (macsr ) contains a 4-bit operational mode field and condition flags. operational mode bits control whet her operands are signed or unsigne d and whether they are treated as integers or fractions. these bits also control the overflow/saturation mode and the way in which rounding is performed. negative, zero, and multiple overflow condition flags are also provided. table 3-1. emac memory map bdm 1 register width (bits) access reset value section/page 0x804 mac status register (macsr) 32 r/w 0x0000_0000 3.2.1/3-3 0x805 mac address mask regi ster (mask) 32 r/w 0xffff_ffff 3.2.2/3-5 0x806 mac accumulator 0 (acc0) 32 r/w undefined 3.2.3/3-6 0x807 mac accumulator 0,1 extension bytes (accext01) 32 r/w undefined 3.2.4/3-7 0x808 mac accumulator 2,3 extension bytes (accext23) 32 r/w undefined 3.2.4/3-7 0x809 mac accumulator 1 (acc1) 32 r/w undefined 3.2.3/3-6 0x80a mac accumulator 2 (acc2) 32 r/w undefined 3.2.3/3-6 0x80b mac accumulator 3 (acc3) 32 r/w undefined 3.2.3/3-6 1 the values listed in this column represen t the rc field used when accessing the core registers via the bdm port. for more information see chapter 43, ?debug module.? bdm: 0x804 (macsr) access: supervisor read/write bdm read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 pav n omc s/u f/i r/t n z vev w reset000000000000000000000000 0 0 0 0 0 0 0 0 figure 3-2. mac status register (macsr) table 3-2. macsr field descriptions field description 31?12 reserved, must be cleared. 11?8 pav n product/accumulation overflow flags. contains four flag s, one per accumulator, that indicate if past mac or msac instructions generated an overflow during pr oduct calculation or the 48-bit accumulation. when a mac or msac instruction is executed, the pav n flag associated with the destination accumulator forms the general overflow flag, macsr[v]. once set, each flag remains set until v is cleared by a move.l, macsr instruction or the accumulator is loaded directly. bit 11: accumulator 3 ... bit 8: accumulator 0 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 enhanced multiply-accumulate unit (emac) 3-4 freescale semiconductor 7 omc overflow saturation mode. enables or disables satura tion mode on overflow. if se t, the accumulator is set to the appropriate constant (see s/u field description) on any operation that overflows the accumulator. after saturation, the accumulator remains unaffected by any other mac or msac instructions until the overflow bit is cleared or the accumulator is directly loaded. 6 s/u signed/unsigned operations. in integer mode: s/u determines whether operations performed are sig ned or unsigned. it also determines the accumulator value during saturation, if enabled. 0 signed numbers. on overflow, if omc is enabled, an accumulator saturates to the most positive (0x7fff_ffff) or the most negative (0x8000_0000) number, depending on the instruction and the product value that overflowed. 1 unsigned numbers. on overflow, if omc is enabled, an accumulator saturates to the smallest value (0x0000_0000) or the largest value (0xfff f_ffff), depending on the instruction. in fractional mode: s/u controls rounding while storing an accumulator to a general-purpose register. 0 move accumulator without rounding to a 16-bit value. accumulator is moved to a general-purpose register as a 32-bit value. 1 the accumulator is rounded to a 16-bit value using the round-to-nearest (even) method when moved to a general-purpose register. see section 3.3.1.1, ?rounding? . the resulting 16-bit value is stored in the lower word of the destination register. the upper wo rd is zero-filled. this rounding procedure does not affect the accumulator value. 5 f/i fractional/integer mode. determines whether input operands are treated as fractions or integers. 0 integers can be represented in signed or un signed notation, depending on the value of s/u. 1 fractions are represented in signed, fixed-point, tw o?s complement notation. values range from -1 to 1-2 -15 for 16-bit fractions and -1 to 1 - 2 -31 for 32-bit fractions. see section 3.3.4, ?data representation ." 4 r/t round/truncate mode. controls rounding procedure for move.l accx,rx , or msac.l instructions when in fractional mode. 0 truncate. the product?s lsbs are dropped before it is combined with the accumulator. additionally, when a store accumulator instruction is executed ( move.l accx,rx ), the 8 lsbs of the 48-bit accumulator logic are truncated. 1 round-to-nearest (even). the 64-bit product of two 32-bit, fractional op erands is rounded to the nearest 40-bit value. if the low-order 24 bits equal 0x80_0000, the upper 40 bits are rounded to the nearest even (lsb = 0) value. see section 3.3.1.1, ?rounding? . additionally, when a store accumulator instruction is executed ( move.l accx,rx ), the lsbs of the 48-bit accumulator logic round the resulting 16- or 32-bit value. if macsr[s/u] is cleared and macsr[r/t] is set, the low-order 8 bits are used to round the resulting 32-bit fraction. if macsr[s/u] is set, the low-order 24 bits are used to round the resulting 16-bit fraction. 3 n negative. set if the msb of the result is set, other wise cleared. n is affected only by mac, msac, and load operations; it is not affected by muls and mulu instructions. 2 z zero. set if the result equals zero, otherwise cleared. this bit is affected only by mac, msac, and load operations; it is not affected by muls and mulu instructions. table 3-2. macsr field descriptions (continued) field description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 enhanced multiply-accumulate unit (emac) freescale semiconductor 3-5 table 3-3 summarizes the interaction of th e macsr[s/u,f/i,r/t] control bits. 3.2.2 mask register (mask) the 32-bit mask implements the low-order 16 bits to minimize the alignmen t complications involved with loading and storing only 16 bits. when the mask is loaded, the low-order 16 bits of the source operand are actually loaded into the register. when it is stored, the upper 16 bits are all forced to ones. this register performs a simple and with the operand address for mac instructions. the processor calculates the normal ope rand address and, if enabled, that address is then anded with {0xffff, mask[15:0]} to form the final addr ess. therefore, with certain mask bits cleared, the operand address can be constrained to a certain memo ry region. this is used primarily to implement circular queues with the (an)+ addressing mode. this minimizes the addressing suppor t required for filtering, convolution, or any routine that implements a data array as a circular queue . for mac + move operations, the mask contents can optionally be included in all memory effective address calculations. the synt ax is as follows: mac.sz ry,rxsf, enhanced multiply-accumulate unit (emac) 3-6 freescale semiconductor the and operator enables the mask use and causes bi t 5 of the extension word to be set. the exact algorithm for the use of mask is: if extension word, bit [5] = 1, the mask bit, then if enhanced multiply-accumulate unit (emac) freescale semiconductor 3-7 figure 3-4. accumulator registers (acc0?3) 3.2.4 accumulator extension registers (accext01, accext23) each pair of 8-bit accumulator extension fields are concatenated with the corresponding 32-bit accumulator register to form the 48-bit accumulator. for more information, see section 3.3, ?functional description.? figure 3-5. accumulator extension register (accext01) bdm: 0x806 (acc0) 0x809 (acc1) 0x80a (acc2) 0x80b (acc3) access: user read/write bdm read/write 313029282726252423222120191817161514131211109876543210 r accumulator w reset???????????????????????????????? table 3-5. acc0?3 field descriptions field description 31?0 accumulator store 32-bits of the result of the mac operation. bdm: 0x807 (accext01) access: user read/write bdm read/write 313029282726252423222120191817161514131211109876543210 r acc0u acc0l acc1u acc1l w reset???????????????????????????????? table 3-6. accext01 field descriptions field description 31?24 acc0u accumulator 0 upper extension byte 23?16 acc0l accumulator 0 lower extension byte 15?8 acc1u accumulator 1 upper extension byte 7?0 acc1l accumulator 1 lower extension byte mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 enhanced multiply-accumulate unit (emac) 3-8 freescale semiconductor figure 3-6. accumulator extension register (accext23) 3.3 functional description the mac speeds execution of coldfire integer-mu ltiply instructions (muls and mulu) and provides additional functionality for multiply-accumulate ope rations. by executing muls and mulu in the mac, execution times are minimized and deterministic compared to the 2-bit/cycle algorithm with early termination that the oep normally us es if no mac hardware is present. the added mac instructions to the coldfire isa pr ovide for the multiplicati on of two numbers, followed by the addition or subtraction of the product to or from the value in an accumulator. optionally, the product may be shifted left or right by 1 bit before addi tion or subtraction. hardwa re support for saturation arithmetic can be enable d to minimize software overh ead when dealing with potential overflow conditions. multiply-accumulate operations support 16- or 32-bit input operands in these formats: ? signed integers ? unsigned integers ? signed, fixed-point, fractional numbers the emac is opti mized for single-cy cle, pipelined 32 32 multiplications. for word- and longword-sized integer input operands, the low-order 40 bits of the product are formed and used with the destination accumulator. for fractio nal operands, the entire 64-bit produc t is calculated and truncated or rounded to the most-significant 40-bit result using the round-to-nearest (even) method before it is combined with the de stination accumulator. for all operations, the resulting 40-bit product is ex tended to a 48-bit value (u sing sign-extension for signed integer and fractional operands , zero-fill for unsigned integer operands) before being combined with the 48-bit destination accumulator. bdm: 0x808 (accext23) access: user read/write bdm read/write 313029282726252423222120191817161514131211109876543210 r acc2u acc2l acc3u acc3l w reset???????????????????????????????? table 3-7. accext23 field descriptions field description 31?24 acc2u accumulator 2 upper extension byte 23?16 acc2l accumulator 2 lower extension byte 15?8 acc3u accumulator 3 upper extension byte 7?0 acc3l accumulator 3 lower extension byte mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 enhanced multiply-accumulate unit (emac) freescale semiconductor 3-9 figure 3-7 and figure 3-8 show relative alignment of input opera nds, the full 64-bit product, the resulting 40-bit product used for accumulation, and 48-bit accumulator formats. figure 3-7. fractional alignment figure 3-8. signed and unsigned integer alignment therefore, the 48-bit accumulator de finition is a function of the emac operating mode. given that each 48-bit accumulator is the con catenation of 16-bit accumulato r extension register (accext n) contents and 32-bit accn contents, the specific definitions are: if macsr[6:5] == 00 /* signed integer mode */ complete accumulator[47:0] = {accext n [15:0], acc n [31:0]} if macsr[6:5] == 01 or 11 /* signed fractional mode */ complete accumulator [47:0] = {accext n [15:8], acc n [31:0], accext n [7:0]} if macsr[6:5] == 10 /* unsigned integer mode */ complete accumulator[47:0] = {accext n [15:0], acc n [31:0]} the four accumulators are re presented as an array, acc n , where n selects the register. x operandy operandx product extended product accumulator 8 extension byte upper [7:0] + 0 32 40 40 8 40 extension byte lower [7:0] 32 23 8 accumulator [31:0] x operandy operandx product extended product accumulator 32 32 32 32 32 8 8 8 24 8 8 + extension byte upper [7:0] extension byte lower [7:0] accumulator [31:0] mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 enhanced multiply-accumulate unit (emac) 3-10 freescale semiconductor although the multiplier array is implemented in a four-stage pipeline, all arithmetic mac instructions have an effective issue rate of 1 cycle, regardless of input operand size or type. all arithmetic operations use register-based input operands, and summed values are stored in an accumulator. therefore, an additional move instruct ion is needed to store data in a general-purpose register. one new feature in emac instructions is the ability to choose the upper or lower word of a register as a 16-bit input operand. this is useful in filtering op erations if one data register is loaded with the input data and another is loaded with the co efficient. two 16-bit multiply accumulates can be performed without fetching additiona l operands between inst ructions by alternating word choice during calculations. the emac has four accumul ator registers versus th e mac?s single accumulator. the additional registers improve the performance of some al gorithms by minimizing pipeline stalls needed to store an accumulator value back to general-purpose regist ers. many algorithms require multiple calculations on a given data set. by applying different accumulators to these calculati ons, it is often possible to store one accumulator without any stalls while perf orming operations involving a diff erent destination accumulator. the need to move large amounts of data presents an obstacle to obtaining high throughput rates in dsp engines. existing coldfire instru ctions can accommodate these requi rements. a movem instruction can efficiently move large data blocks by generating line-s ized burst references. the ability to load an operand simultaneously from memory into a register and ex ecute a mac instruction makes some dsp operations such as filtering and convolution more manageable. the programming model includes a mask register (mask), which can optio nally be used to generate an operand address during mac + move instructions. the register app lication with auto-increment addressing mode supports effici ent implementation of circular data queues for memory operands. 3.3.1 fractional operation mode this section describes behavior when the fr actional mode is used (macsr[f/i] is set). 3.3.1.1 rounding when the processor is in fractional mode, ther e are two operations during which rounding can occur: 1. execution of a store accumulator instruction ( move.l accx,rx ). the lsbs of the 48-bit accumulator logic are used to round the resulti ng 16- or 32-bit value. if macs r[s/u] is cleared, the low-order 8 bits round the resulting 32-bit fraction. if macsr[s/ u] is set, the low-order 24 bits are used to round the resulting 16-bit fraction. 2. execution of a mac (or msac) instruction wi th 32-bit operands. if macsr[r/t] is zero, multiplying two 32-bit num bers creates a 64-bit pr oduct truncated to the upper 40 bits; otherwise, it is rounded using round-to-nearest (even) method. to understand the round-to-nearest-even method, cons ider the following example involving the rounding of a 32-bit number, r0, to a 16-bit number. using this method, the 32-bit number is rounded to the closest 16-bit number possible. let the high-order 16 bits of r0 be named r0.u and the low-order 16 bits be r0.l. ? if r0.l is less than 0x8000, the result is truncated to the value of r0.u. ? if r0.l is greater than 0x8000, the up per word is incremented (rounded up). mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 enhanced multiply-accumulate unit (emac) freescale semiconductor 3-11 ? if r0.l is 0x8000, r0 is half-way between two 16- bit numbers. in this ca se, rounding is based on the lsb of r0.u, so the result is always even (lsb = 0). ? if the lsb of r0.u equals 1 and r 0.l equals 0x8000, the number is rounded up. ? if the lsb of r0.u equals 0 and r 0.l equals 0x8000, the number is rounded down. this method minimizes rounding bias and creates as statistically correct an answer as possible. the rounding algorithm is summarized in the following pseudocode: if r0.l < 0x8000 then result = r0.u else if r0.l > 0x8000 then result = r0.u + 1 else if lsb of r0.u = 0 /* r0.l = 0x8000 */ then result = r0.u else result = r0.u + 1 the round-to-nearest-even technique is also known as convergent rounding. 3.3.1.2 saving and restoring the emac programming model the presence of rounding logic in th e emac output datapath requires special care during the emac?s save/restore process. in particular , any result rounding modes must be disabled during the save/restore process so the exact bit-wise contents of the emac registers are accessed. consider the memory structure containing the emac programming model: struct macstate { int acc0; int acc1; int acc2; int acc3; int accext01; int accext02; int mask; int macsr; } macstate; the following assembly language r outine shows the proper sequence for a correct emac st ate save. this code assumes all dn and an register s are available for use, and the memory location of the state save is defined by a7. emac_state_save: move.l macsr,d7 ; save the macsr clr.l d0 ; zero the register to ... move.l d0,macsr ; disable rounding in the macsr move.l acc0,d0 ; save the accumulators move.l acc1,d1 move.l acc2,d2 move.l acc3,d3 move.l accext01,d4 ; save the accumulator extensions move.l accext23,d5 move.l mask,d6 ; save the address mask movem.l #0x00ff,(a7) ; move the state to memory this code performs the emac state restore: emac_state_restore: mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 enhanced multiply-accumulate unit (emac) 3-12 freescale semiconductor movem.l (a7),#0x00ff ; restore the state from memory move.l #0,macsr ; disable rounding in the macsr move.l d0,acc0 ; restore the accumulators move.l d1,acc1 move.l d2,acc2 move.l d3,acc3 move.l d4,accext01 ; restore the accumulator extensions move.l d5,accext23 move.l d6,mask ; restore the address mask move.l d7,macsr ; restore the macsr executing this sequence type can correctly save and restore the ex act state of the emac programming model. 3.3.1.3 muls/mulu muls and mulu are unaffected by fr actional-mode operation; operands re main assumed to be integers. 3.3.1.4 scale factor in mac or msac instructions the scale factor is ignored whil e the mac is in fractional mode. 3.3.2 emac instruction set summary table 3-8 summarizes emac unit instructions. table 3-8. emac instruction summary command mnemonic description multiply signed muls enhanced multiply-accumulate unit (emac) freescale semiconductor 3-13 3.3.3 emac instruction execution times the instruction execution times for the emac can be found in section 2.3.5.6, ?emac instruction execution times? . the emac execution pipeline overlaps the agex stage of the oep (the first stag e of the emac pipeline is the last stage of the basic oe p). emac units are designed for su stained, fully-pipelined operation on accumulator load, copy, and multiply-accumulate instructions. however, instructions that store contents of the multiply-accumulate programmi ng model can generate oep stalls that expose the emac execution pipeline depth: mac.w ry, rx, acc0 move.l acc0, rz the move.l instruction that stores the accumulato r to an integer register (rz) stalls until the program-visible copy of the accumulator is available. figure 3-9 shows emac timing. figure 3-9. emac-specific oep sequence stall in figure 3-9 , the oep stalls the store-accumulator instruct ion for three cycles: th e emac pipleline depth minus 1. the minus 1 factor is needed because the oep and emac pipelines overlap by a cycle, the agex stage. as the store-accumulator instructi on reaches the agex stage where the operation is performed, the recently updated accu mulator 0 value is available. load accumulator extensions 23 move.l {ry,#imm},accext23 loads the accumulator 2,3 extension bytes with a 32-bit operand store accumulator extensions 01 move.l accext01,rx writes the contents of accumula tor 0,1 extension bytes into a cpu register store accumulator extensions 23 move.l accext23,rx writes the contents of accumula tor 2,3 extension bytes into a cpu register table 3-8. emac instruction summary (continued) command mnemonic description dsoc agex mac mac emac ex1 emac ex2 emac ex3 emac ex4 mac mac mac move move move move three-cycle regbusy stall accumulator 0 old new mac mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 enhanced multiply-accumulate unit (emac) 3-14 freescale semiconductor as with change or use stalls between accumulators and general-purpose register s, introducing intervening instructions that do not reference the busy register can reduce or eliminate sequence-related store-mac instruction stalls. a major benefit of the emac is th e addition of three accumulators to minimize stalls caused by exchanges between accumulat or(s) and general-purpose registers. 3.3.4 data representation macsr[s/u,f/i] selects one of the following three modes, where each mode defines a unique operand type: 1. two?s complement signed integer: in this form at, an n-bit operand value lies in the range -2 (n-1) < operand < 2 (n-1) - 1. the binary point is right of the lsb. 2. unsigned integer: in this format, an n-bit operand value lies in the range 0 < operand < 2 n - 1. the binary point is right of the lsb. 3. two?s complement, signed fractiona l: in an n-bit number, the first bit is the sign bi t. the remaining bits signify the first n-1 bits after th e binary point. given an n-bit number, a n-1 a n-2 a n-3 ... a 2 a 1 a 0 , its value is given by the equation in equation 3-3 . eqn. 3-3 this format can represent numbers in the range -1 < operand < 1-2 (n-1) . for words and longwords, the largest negative number that can be represented is -1, whose internal representation is 0x8000 and 0x8000_0000, respectively. the largest positive word is 0x7fff or (1 - 2 -15 ); the most positive longword is 0x7fff_ffff or (1 - 2 -31 ). 3.3.5 mac opcodes mac opcodes are described in the coldfire programmer?s reference manual . remember the following: ? unless otherwise noted, the value of macsr[n,z] is based on the re sult of the final operation that involves the product and the accumulator. ? the overflow (v) flag is managed differently. it is set if the complete product cannot be represented as a 40-bit value (t his applies to 32 32 integer operations only) or if the combination of the product with an accumulator cannot be represented in the given number of bits. the emac design includes an additional product/accumulation overflow bi t for each accumulator that are treated as sticky indicators and are used to calculate the v bit on each mac or msac instruction. see section 3.2.1, ?mac status register (macsr)? . ? for the mac design, the assembler syntax of the mac (multiply and a dd to accumulator) and msac (multiply and subtract from accumulator) instructions does not include a reference to the single accumulator. for the emac, assemblers support this syntax and no explic it reference to an accumulator is interpreted as a reference to acc0. assemblers also support syntaxes where the destination accumulator is explicitly defined. value 1 a n1 ? ? () ?2 i1n ?+ () ? ai ? i0 = n2 ? + = mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 enhanced multiply-accumulate unit (emac) freescale semiconductor 3-15 ? the optional 1-bit shift of the product is specified using the notation {<< | >>} sf, where <<1 indicates a left shift and >>1 indicates a right shift. the shift is performed before the product is added to or subtracted from the accumulator. without this operator, the product is not shifted. if the emac is in fractional mode (mac sr[f/i] is set), sf is ignored and no shift is performed. because a product can overflow, the follow ing guidelines are implemented: ? for unsigned word and longword operations, a zer o is shifted into the product on right shifts. ? for signed, word operations, the sign bit is shif ted into the product on right shifts unless the product is zero. for signed, longwor d operations, the sign bit is sh ifted into the product unless an overflow occurs or the product is zero, in which case a zero is shifted in. ? for all left shifts, a zero is inserted into the lsb position. the following pseudocode explains basic mac or msac instruction functionality. this example is presented as a case statement covering the three ba sic operating modes with signed integers, unsigned integers, and signed fractionals. throughout this example, a comma-separated list in curly brackets, {}, indicates a concatenation operation. switch (macsr[6:5]) /* macsr[s/u, f/i] */ { case 0: /* signed integers */ if (macsr.omc == 0 || macsr.pavn == 0) then { macsr.pavn = 0 /* select the input operands */ if (sz == word) then {if (u/ly == 1) then operandy[31:0] = {sign-extended ry[31], ry[31:16]} else operandy[31:0] = {sign-extended ry[15], ry[15:0]} if (u/lx == 1) then operandx[31:0] = {sign-extended rx[31], rx[31:16]} else operandx[31:0] = {sign-extended rx[15], rx[15:0]} } else {operandy[31:0] = ry[31:0] operandx[31:0] = rx[31:0] } /* perform the multiply */ product[63:0] = operandy[31:0] * operandx[31:0] /* check for product overflow */ if ((product[63:39] != 0x0000_00_0) and and (product[63:39] != 0xffff_ff_1)) then { /* product overflow */ macsr.pavn = 1 macsr.v = 1 if (inst == msac and and macsr.omc == 1) then if (product[63] == 1) then result[47:0] = 0x0000_7fff_ffff else result[47:0] = 0xffff_8000_0000 else if (macsr.omc == 1) then /* overflowed mac, saturationmode enabled */ if (product[63] == 1) then result[47:0] = 0xffff_8000_0000 else result[47:0] = 0x0000_7fff_ffff } mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 enhanced multiply-accumulate unit (emac) 3-16 freescale semiconductor /* sign-extend to 48 bits before performing any scaling */ product[47:40] = {8{product[39]}} /* sign-extend */ /* scale product before combining with accumulator */ switch (sf) /* 2-bit scale factor */ { case 0: /* no scaling specified */ break; case 1: /* sf = ?<< 1? */ product[40:0] = {product[39:0], 0} break; case 2: /* reserved encoding */ break; case 3: /* sf = ?>> 1? */ product[39:0] = {product[39], product[39:1]} break; } if (macsr.pavn == 0) then {if (inst == msac) then result[47:0] = accx[47:0] - product[47:0] else result[47:0] = accx[47:0] + product[47:0] } /* check for accumulation overflow */ if (accumulationoverflow == 1) then {macsr.pavn = 1 macsr.v = 1 if (macsr.omc == 1) then /* accumulation overflow, saturationmode enabled */ if (result[47] == 1) then result[47:0] = 0x0000_7fff_ffff else result[47:0] = 0xffff_8000_0000 } /* transfer the result to the accumulator */ accx[47:0] = result[47:0] } macsr.v = macsr.pavn macsr.n = accx[47] if (accx[47:0] == 0x0000_0000_0000) then macsr.z = 1 else macsr.z = 0 if ((accx[47:31] == 0x0000_0) || (accx[47:31] == 0xffff_1)) then macsr.ev = 0 else macsr.ev = 1 break; case 1,3: /* signed fractionals */ if (macsr.omc == 0 || macsr.pavn == 0) then { macsr.pavn = 0 if (sz == word) then {if (u/ly == 1) then operandy[31:0] = {ry[31:16], 0x0000} else operandy[31:0] = {ry[15:0], 0x0000} if (u/lx == 1) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 enhanced multiply-accumulate unit (emac) freescale semiconductor 3-17 then operandx[31:0] = {rx[31:16], 0x0000} else operandx[31:0] = {rx[15:0], 0x0000} } else {operandy[31:0] = ry[31:0] operandx[31:0] = rx[31:0] } /* perform the multiply */ product[63:0] = (operandy[31:0] * operandx[31:0]) << 1 /* check for product rounding */ if (macsr.r/t == 1) then { /* perform convergent rounding */ if (product[23:0] > 0x80_0000) then product[63:24] = product[63:24] + 1 else if ((product[23:0] == 0x80_0000) and and (product[24] == 1)) then product[63:24] = product[63:24] + 1 } /* sign-extend to 48 bits and combine with accumulator */ /* check for the -1 * -1 overflow case */ if ((operandy[31:0] == 0x8000_0000) and and (operandx[31:0] == 0x8000_0000)) then product[71:64] = 0x00 /* zero-fill */ else product[71:64] = {8{product[63]}} /* sign-extend */ if (inst == msac) then result[47:0] = accx[47:0] - product[71:24] else result[47:0] = accx[47:0] + product[71:24] /* check for accumulation overflow */ if (accumulationoverflow == 1) then {macsr.pavn = 1 macsr.v = 1 if (macsr.omc == 1) then /* accumulation overflow, saturationmode enabled */ if (result[47] == 1) then result[47:0] = 0x007f_ffff_ff00 else result[47:0] = 0xff80_0000_0000 } /* transfer the result to the accumulator */ accx[47:0] = result[47:0] } macsr.v = macsr.pavn macsr.n = accx[47] if (accx[47:0] == 0x0000_0000_0000) then macsr.z = 1 else macsr.z = 0 if ((accx[47:39] == 0x00_0) || (accx[47:39] == 0xff_1)) then macsr.ev = 0 else macsr.ev = 1 break; case 2: /* unsigned integers */ if (macsr.omc == 0 || macsr.pavn == 0) then { macsr.pavn = 0 /* select the input operands */ if (sz == word) then {if (u/ly == 1) then operandy[31:0] = {0x0000, ry[31:16]} else operandy[31:0] = {0x0000, ry[15:0]} if (u/lx == 1) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 enhanced multiply-accumulate unit (emac) 3-18 freescale semiconductor then operandx[31:0] = {0x0000, rx[31:16]} else operandx[31:0] = {0x0000, rx[15:0]} } else {operandy[31:0] = ry[31:0] operandx[31:0] = rx[31:0] } /* perform the multiply */ product[63:0] = operandy[31:0] * operandx[31:0] /* check for product overflow */ if (product[63:40] != 0x0000_00) then { /* product overflow */ macsr.pavn = 1 macsr.v = 1 if (inst == msac and and macsr.omc == 1) then result[47:0] = 0x0000_0000_0000 else if (macsr.omc == 1) then /* overflowed mac, saturationmode enabled */ result[47:0] = 0xffff_ffff_ffff } /* zero-fill to 48 bits before performing any scaling */ product[47:40] = 0 /* zero-fill upper byte */ /* scale product before combining with accumulator */ switch (sf) /* 2-bit scale factor */ { case 0: /* no scaling specified */ break; case 1: /* sf = ?<< 1? */ product[40:0] = {product[39:0], 0} break; case 2: /* reserved encoding */ break; case 3: /* sf = ?>> 1? */ product[39:0] = {0, product[39:1]} break; } /* combine with accumulator */ if (macsr.pavn == 0) then {if (inst == msac) then result[47:0] = accx[47:0] - product[47:0] else result[47:0] = accx[47:0] + product[47:0] } /* check for accumulation overflow */ if (accumulationoverflow == 1) then {macsr.pavn = 1 macsr.v = 1 if (inst == msac and and macsr.omc == 1) then result[47:0] = 0x0000_0000_0000 else if (macsr.omc == 1) then /* overflowed mac, saturationmode enabled */ mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 enhanced multiply-accumulate unit (emac) freescale semiconductor 3-19 result[47:0] = 0xffff_ffff_ffff } /* transfer the result to the accumulator */ accx[47:0] = result[47:0] } macsr.v = macsr.pavn macsr.n = accx[47] if (accx[47:0] == 0x0000_0000_0000) then macsr.z = 1 else macsr.z = 0 if (accx[47:32] == 0x0000) then macsr.ev = 0 else macsr.ev = 1 break; } mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 enhanced multiply-accumulate unit (emac) 3-20 freescale semiconductor mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor 4-1 chapter 4 cache 4.1 introduction this chapter describes cache operation on the coldfire processor. 4.1.1 features features include the following: ? configurable as instruction, data, or split instruction/data cache ? 2 -kbyte direct-mapped cache ? single-cycle access on cache hits ? physically located on the coldfire core's high-speed local bus ? nonblocking design to maximize performance ? separate instruction and data 16-byte line-fill buffers ? configurable instruction cache miss-fetch algorithm 4.1.2 introduction the cache is a direct-mapped, single- cycle memory. it may be configur ed as an instruction cache, a write-through data cache, or a sp lit instruction/data cache. the cache storage is organized as 128 lines, each containing 16 bytes. the me mory storage consists of a 128 -entry tag array (cont aining addresses and a valid bit), and a data array containing 2 kbytes, organized as 512 32 bits. cache configuration is controlled by bits in the cach e control register (cacr), detailed later in this chapter. for the instruction or data -only configurations, only the associat ed instruction or data line-fill buffer is used. for the split cache configuration, one-h alf of the tag and storage arrays is used for an instruction cache and one-hal f is used for a data cach e. the split cache configur ation uses the instruction and the data line-fill buffers. the core?s local bus is a unified bus used for instruction and data fetches. therefore, the cache can have only one fetc h, instruction or data, active at one time. for the instruction- or data-only c onfigurations, the cache tag and stor age arrays are acce ssed in parallel: fetch address bits [ 10 :4] addressing the tag array, and fetch address bits [ 10 :2] addressing the storage array. for the split cache configuration, the cache tag and storage arrays are a ccessed in parallel. the msb of the tag array address is set for instruction fetches and cleared for operand fetches; fetch address bits [ 9 :4] provide the rest of the tag array address. the ta g array outputs the address mapped to the given cache location along with the valid bit for the line. th is address field is compared to bits [31: 11 ] for instruction- or data-only configura tions and to bits [31: 10 ] for a split configuration of the fetch address from the local bus to determine if a cache hit has occurred. if the desired address is mapped into the cache memory, the mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 cache 4-2 freescale semiconductor output of the storage array is driven onto the coldfire core's local data bus, thereby completing the access in a single cycle. the tag array maintains a single valid bit per line entry. accordingly, onl y entire 16-byte lines are loaded into the cache. the cache also contains separate 16-byte instruction and data line-fil l buffers that provide temporary storage for the last line fetched in response to a cache miss. with each fetch, the co ntents of the associated line fill buffer are exa mined. thus, each fetch address examines the tag memory array and the associated line fill buffer to see if the desi red address is mapped into either ha rdware resource. a cache hit in the memory array or the associated line-fill buffer is serviced in a single cycle. because the line fill buffer maintains valid bits on a longword basis, hits in the buffer can be se rviced immediately without waiting for the entire line to be fetched. if the referenced address is not contained in the memory array or th e associated line-fill buffer, the cache initiates the required external fetch operation. in mo st situations, this is a 16-byte line-sized burst reference. the hardware implementation is a n onblocking design, meaning the coldfire core's local bus is released after the initial access of a miss. thus, the cache or the sram module can se rvice subsequent requests while the remainder of the line is being fetched and loaded into the fill buffer. figure 4-1. 2-kbyte cache block diagram 4.2 memory map/register definition three supervisor registers define the operation of the cache and local bus controller: the cache control register (cacr) and two access co ntrol registers (acr0, acr1). table 4-1 below shows the memory map 31 43 0 12 31 4 = = 31 31 0 0 0 local address bus i or d line buffer address external data[31:0] i or d line buffer storage mux data mux fill hit tag valid local data bus ta g h i t 127 511 11 10 tag index data index mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 cache freescale semiconductor 4-3 of these registers. the cacr and acrs can only be accessed in supervisor mode using the movec instruction with an rc value of 0x002, 0x004 and 0x005, respectively. 4.2.1 cache control register (cacr) the cacr controls the operation of the cache. th e cacr provides a set of default memory access attributes used when a refere nce address does not map into the spaces defined by the acrs. the cacr is a 32-bit, writ e-only supervisor control register. it is accessed in the cpu address space via the movec instruction with an rc encoding of 0x002. the cacr can be read when in background debug mode (bdm). therefore, the register diagram, figure 4-2 , is shown as read/write . at system reset, the entire register is cleared. table 4-1. cache memory map bdm 1 1 the values listed in this column represent the rc field used when accessing the core registers via the bdm port. for more information see chapter 30, ?debug support.? register width (bits) access 2 2 readable through debug. reset value section/page 0x002 cache control register (cacr) 32 w 0x0000_0000 4.2.1/4-3 0x004 access control register 0 (acr0) 32 w see section 4.2.2/4-6 0x005 access control register 1 (acr1) 32 w see section 4.2.2/4-6 bdm: 0x002 (cacr) access: supervisor write-only debug read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r cenb 0 0 cpd cfrz 00 cinv disi disd invi invd 0 000 w reset0000000 0 000000 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0 0000 ceib dcm dbwe 0 0 dwp eusp 0 0 clnf w reset0000000 0 000000 0 0 figure 4-2. cache control register (cacr) table 4-2. cacr field descriptions field description 31 cenb cache enable. the memory array of the cache is enabled only if ce nb is asserted. this bit, along with the disi (disable instruction caching) and disd (disable da ta caching) bits, control the cache configuration. 0 cache disabled 1 cache enabled ta bl e 4 - 3 describes cache configuration. 30?29 reserved, must be cleared. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 cache 4-4 freescale semiconductor 28 cpdi disable cpushl invalidation. when the privileged cpushl in struction is executed, the cache entry defined by bits [10:4] of the address is invalidat ed if cpdi is cleared. if cpdi is set, no operation is performed. 0 enable invalidation 1 disable invalidation 27 cfrz cache freeze. this field allows the user to freeze the co ntents of the cache. when cfrz is asserted line fetches can be initiated and loaded into the line-fill buffer, but a valid cache entry can not be overwritt en. if a given cache location is invalid, the contents of t he line-fill buffer can be written into the memory array while cfrz is asserted. 0 normal operation 1 freeze valid cache lines 26?25 reserved, must be cleared. 24 cinv cache invalidate. the cache invalidate operation is not a function of the cenb state (this operation is independent of the cache being enabled or disabled). setting this bit forc es the cache to invalidate all, half, or none of the tag array entries depending on the state of the disi, disd, invi, and invd bits. the invalidation process requires several cycles of overhead plus 128 machine cycles to clear all tag array entries and 64 cycles to clear half of the tag array entries, with a single cache entry clear ed per machine cycle. the state of this bit is always read as a zero. after a hardware reset, the cache must be invalidated before it is enabled. 0 no operation 1 invalidate all cache locations ta bl e 4 - 4 describes how to set the cache invalidate all bit. 23 disi disable instruction caching. when set, this bit disables in struction caching. this bit, along with the cenb (cache enable) and disd (disable data caching) bits, control the cache configuration. see the cenb definition for a detailed description. 0 enable instruction caching 1 disable instruction caching ta bl e 4 - 3 describes cache configuration and ta b l e 4 - 4 describes how to set the cache invalidate all bit. 22 disd disable data caching. when set, this bit disables data caching. this bit, along with the cenb (cache enable) and disi (disable instruction caching) bits, control the cache configuration. see the cenb definition for a detailed description. 0 enable data caching 1 disable data caching ta bl e 4 - 3 describes cache configuration and ta b l e 4 - 4 describes how to set the cache invalidate all bit. 21 invi cinv instruction cache only. this bit can not be set unless the cache configuration is split (disi and disd cleared). for instruction or data cache configurations this bit is a don?t-care. for the split cache configuration, this bit is part of the control for the invalidate a ll operation. see the cinv defin ition for a detailed description ta bl e 4 - 4 describes how to set the cache invalidate all bit. 20 invd cinv data cache only. this bit can not be set unless the cache configuration is split (d isi and disd cleared). for instruction or data cache configurations this bit is a don?t-care. for the split cache configuration, this bit is part of the control for the invalidate all operation. see the cinv definition for a detailed description ta bl e 4 - 4 describes how to set the cache invalidate all bit. 19?11 reserved, must be cleared. 10 ceib cache enable non-cacheable instruction bursting. setting this bit enables the line-fill buffer to be loaded with burst transfers under control of clnf[1:0] for non-cacheable accesses. non-cacheable accesses are never written into the memory array. see ta b l e 4 - 7 . 0 disable burst fetches on non-cacheable accesses 1 enable burst fetches on non-cacheable accesses table 4-2. cacr field descriptions (continued) field description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 cache freescale semiconductor 4-5 table 4-3 shows the relationship between cacr[cenb, disi, & disd] bits and the cache configuration. table 4-4 shows the relationship between cacr[disi, disd, invi, & invd] and setting the cache invalidate all bit (cacr[cinv]). 9 dcm default cache mode. this bit defines the default cache mode. for more information on the selection of the effective memory attributes, see section 4.3.2, ?memory reference attributes . 0 caching enabled 1 caching disabled 8 dbwe default buffered write enable. this bit defines the defaul t value for enabling buffered writes. if dbwe = 0, the termination of an operand write cycle on the processor's local bus is delayed until the external bus cycle is completed. if dbwe = 1, the write cycle on the local bus is terminat ed immediately and the o peration buffered in the bus controller. in this mode, operand write cycles are effectively decoupled between the processor's local bus and the external bus. generally, enabled buffered writes pr ovide higher system performance but recovery from access errors can be more difficult. for the coldfire core, reporting access errors on operand writes is always imprecise and enabling buffered writes further decouples the write instruction and the signaling of the fault 0 disable buffered writes 1 enable buffered writes 7?6 reserved, must be cleared. 5 dwp default write protection 0 read and write accesses permitted 1 only read accesses permitted 4 eusp enable user stack pointer. see section 2.2.3, ?supervisor/user stack pointers (a7 and other_a7)? for more information on the dual stack pointer implementation. 0 disable the processor?s use of the user stack pointer 1 enable the processor?s use of the user stack pointer 3?2 reserved, must be cleared. 1?0 clnf cache line fill. these bits control the si ze of the memory request the cache issues to the bus controller for different initial instruction line access offsets. see ta b l e 4 - 6 for external fetch size based on miss address and clnf. table 4-3. cache configuration as defined by cacr cacr [cenb] cacr [disi] cacr [disd] configuration description 0 x x n/a cache is completely disabled 1 0 0 split instruction/ data cache 1 kbyte direct-mapped instruction cache (uses upper half of tag and storage arrays) and 1 kbyte direct-mapped write-through data cache (uses lower half of tag and storage arrays) 1 0 1 instruction cache 2 kbyte direct-m apped instruction cache (uses all of tag and storage arrays) 1 1 0 data cache 2 kbyte direct-mapped write-through data cache (uses all of tag and storage arrays) table 4-2. cacr field descriptions (continued) field description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 cache 4-6 freescale semiconductor 4.2.2 access control registers (acr0, acr1) the acrs provide a definition of me mory reference attributes for tw o memory regions (one per acr). this set of effective attributes is defined for every memory reference us ing the acrs or the set of default attributes contained in the cacr. the acrs are examined fo r every processor memory reference not mapped to the flash or sram memories. the acrs are 32-bit, write-only supervisor control re gister. they are accessed in the cpu address space via the movec instruction with an rc encoding of 0x004 and 0x005. the acrs can be read when in background debug mode (bdm). theref ore, the register diagram, figure 4-3 , is shown as read/write. at system reset, both registers are disabled with acr n[en] cleared. note ipsbar space should not be cache d. the combination of the cacr defaults and the two acr n registers must define the non-cacheable attribute for this address space. table 4-4. cache invalidate all as defined by cacr cacr [disi] cacr [disd] cacr [invi] cacr [invd] configuration operation 0000split instruction/ data cache invalidate all entries in 1-kbyte instruction cache and 1-kbyte data cache 0001split instruction/ data cache invalidate only 1 kbyte data cache 0010split instruction data cache invalidate only 1 kbyte instruction cache 0011split instruction/ data cache no invalidate 1 0 x x instruction cache invalidat e 2 kbyte instruction cache 0 1 x x data cache invalidate 2 kbyte data cache bdm: 0x004 (acr0) 0x005 (acr1) access: supervisor write-only bdm read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r ab am en sm 000000 cm bwe 0 0 wp 0 0 w reset???????????????? 0 ? ? 0 0 0 0 0 0 ? ? 0 0 ? 0 0 figure 4-3. access control registers (acr n ) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 cache freescale semiconductor 4-7 4.3 functional description the cache is physically connected to the coldfire core's local bus, allowing it to service all fetches from the coldfire core and certain me mory fetches initiated by the debug module. typically, the debug module's memory references appear as supervisor data accesses but the unit can be programmed to generate user-mode accesses and/or instruction fetches. the cache processe s any fetch access in the normal manner. 4.3.1 interaction with other modules because the cache and high-speed sram module are connected to the coldfire core's local data bus, certain user-defined config urations can result in si multaneous fetch processing. table 4-5. acr n field descriptions field description 31?24 ab address base. this 8-bit field is compared to address bits [31:24] from the processor's local bus under control of the acr address mask. if the address matches, the attributes fo r the memory reference are sourced from the given acr. 23?16 am address mask. masks any ab bit. if a bit in the am field is set, th e corresponding bit of t he address field comparison is ignored. 15 en acr enable. hardware reset clears this bit, disabling the acr. 0acr disabled 1 acr enabled 14?13 sm supervisor mode. allows the given acr to be applied to references based on operating privilege mode of the coldfire processor. the field uses the acr for user refer ences only, supervisor references only, or all accesses. 00 match if user mode 01 match if supervisor mode 1 x match always?ignore user/supervisor mode 12?7 reserved, must be cleared. 6 cm cache mode. 0 caching enabled 1 caching disabled 5 bwe buffered write enable. defines the value for enabling buffered writes. if bwe is cleared, the termination of an operand write cycle on the processor's local bu s is delayed until the system bus cycle is completed. settin g bwe terminates the write cycle on the local bus immediatel y and the operation is t hen buffered in the bus controller. in this mode, operand write cycles are ef fectively decoupl ed between the processor's lo cal bus and the system bus. generally, the enabling of buffered writes provides higher system performance but recovery from access errors may be more difficult. for the v2 coldfire core, the reporting of access errors on operand writes is always imprecise, and enabling buffered writes simply decouples the write instruction from the signaling of the fault even more. 0 writes are not buffered. 1 writes are buffered. 4?3 reserved, must be cleared. 2 wp write protect. defines the writ e-protection attribute. if the effective memory attributes for a given access select the wp bit, an access error terminates any attempted write with this bit set. 0 read and write accesses permitted 1 only read accesses permitted 1?0 reserved, must be cleared. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 cache 4-8 freescale semiconductor if the referenced address is mapped into the sram module, that module services the request in a single cycle. in this case, data accessed from the cache is simply discarded and no external memory references are generated. if the address is not mapped into the sram space, the cache handles the request in the normal fashion. 4.3.2 memory reference attributes for every memory reference the coldfi re core or the debug module generate s, a set of effective attributes is determined based on the address a nd the access control registers (acrs) . this set of at tributes includes the cacheable/non-cacheable definition, the precise /imprecise handling of operand write, and the write-protect capability. in particular, each address is compar ed to the values programmed in th e acrs. if the address matches one of the acr values, the access attribut es from that acr are applied to the reference. if the address does not match either acr, then the default value defined in the cache control register (cacr) is used. the specific algorithm is as follows: if (address == acr0_address including mask) effective attributes = acr0 attributes else if (address == acr1_address including mask) effective attributes = acr1 attributes else effective attributes = cacr default attributes 4.3.3 cache coherency and invalidation the cache does not monitor data refere nces for accesses to cached instructions. therefore, software must maintain instruction cache coherency by invalidating the appropriate cache entries after modifying code segments if instructions are cached. the cache invalidation can be performed in several ways . for the instruction- or data-only configurations, setting cacr[cinv] forces the entire cache to be marked as invali d. the invalidation operation requires 128 cycles because the cache sequences through the entire tag array, clear ing a single location each cycle. for the split configuration, cacr[i nvi] and cacr[invd] can be used in addition to cacr[cinv] to clear the entire cache, only the inst ruction half, or only the data half . any subsequent fetch accesses are postponed until the invalidation sequence is complete. the privileged cpushl instruction can invalidate a single cache line. when this instruction is executed, the cache entry de fined by bits [ 10 :4] of the source addre ss register is invalida ted, provided cacr[cpdi] is cleared. for the split data/i nstruction cache config uration, software dir ectly controls bit 10 that selects whether an instruction cache or da ta cache line is being accessed. these invalidation operations can be initiated from the coldfire core or the debug module. 4.3.4 reset a hardware reset clears the cacr and disables the cach e. the contents of the tag array are not affected by the reset. accordingly, the system startup code mu st explicitly perform a cac he invalidation by setting cacr[cinv] before the cache can be enabled. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 cache freescale semiconductor 4-9 4.3.5 cache miss fetch algorithm/line fills as discussed in section 4.1.2, ?introduction ,? the cache hardware includes a 16-byte, line-fill buffer for providing temporary storage fo r the last fetched line. with the cache enabled as defined by cacr[cenb], a cacheable fetch th at misses in the tag memory and the line-fill buffer generates an external fetch. for data misses, the si ze of the external fetch is always 16 bytes. for instruction misses, the size of the external fetch is determined by the value contained in the 2-bit clnf field of the cacr and the miss address. table 4-6 shows the relationship between the clnf bits, the miss address, and the size of the external fetch. depending on the runtime characteristics of the a pplication and the memory response speed, overall performance may be increased by programming the clnf bits to values 00 or 01. for all cases of a line-sized fetch, the critical longword defined by bits [3:2] of th e miss address is accessed first followed by the remaining three longwords th at are accessed by incremen ting the longword address in a modulo-16 fashion as shown below: if miss address[3:2] = 00 fetch sequence = 0x0, 0x4, 0x8, 0xc if miss address[3:2] = 01 fetch sequence = 0x4, 0x8, 0xc, 0x0 if miss address[3:2] = 10 fetch sequence = 0x8, 0xc, 0x0, 0x4 if miss address[3:2] = 11 fetch sequence = 0xc, 0x0, 0x4, 0x8 after an external fetch has been init iated and the data is loaded into the line-fill buffer, the cache maintains a special most-recently-used indicator that tracks the contents of the asso ciated line-fill buffer versus its corresponding cache location. at the time of the miss, the hardware indicator is set, marking the line-fill buffer as most recently used. if a subsequent access occurs to th e cache location defined by bits [ 10 :4] (or bits [ 9 :4] for split configurations of the fill buffer addres s), the data in the cache memory array is now most recently used, so the hardware indicator is cleared. in all cases, the indicator de fines whether the contents of the line-fill buffer or the memory data array are mo st recently used. at the tim e of the next cache miss, the contents of the line-fill buffer are written into the memory array if the entire line is present, and the line-fill buffer data is mo st recently used compared to the memory array. generally, longword references are used for sequential in struction fetches. if the processor branches to an odd word address, a word-sized instruction fetch is generated. table 4-6. initial fetch offset vs. clnf bits clnf[1:0] longword address bits[3:2] 00 01 10 11 00 line line line longword 01 line line longword longword 1x line line line line mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 cache 4-10 freescale semiconductor for instruction fetches, the fill buffer can also be used as temporary storage for line-sized bursts of non-cacheable references under contro l of cacr[ceib]. with this bit set, a non-cacheable instruction fetch is processed, as defined by table 4-7 . for this condition, the line-fill buffer is loaded and subsequent references can hit in the buffe r, but the data is never loaded into the memory array. table 4-7 shows the relationship between cacr bits cenb and ceib and the type of instruction fetch. table 4-7. instruction cache operation as defined by cacr cacr [cenb] cacr [ceib] type of instruction fetch description 0 0 n/a cache is completely disabled; all instruction fetches are word or longword in size. 0 1 n/a all instruction fetches are word or longword in size 1 x cacheable fetch size is defined by ta bl e 4 - 6 and contents of the line-fill buffer can be written into the memory array 1 0 non-cacheable all instruction fetches are word or longword in size, and not loaded into the line-fill buffer 1 1 non-cacheable instruction fetch size is defined by ta bl e 4 - 6 and loaded into the line-fill buffer, but are never written into the memory array. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor 5-1 chapter 5 static ram (sram) 5.1 sram features ? one 64-kbyte sram ? single-cycle access ? physically located on processor's high-speed local bus ? memory location programmable on any 0-modulo-64 kbyte address ? byte, word, longword address capabilities 5.2 sram operation the sram module provides a general-purpose memory block that the coldfire processo r can access in a single cycle. the location of the memory block can be specified to any 0-modul o-64k address within the 4-gbyte address space. the memory is ideal for storing critical code or data structures or for use as the system stack. because the sram m odule is physically connected to the processor's high-speed local bus, it can service processor-initiated access or me mory-referencing commands from the debug module. depending on configuration information, instruction fe tches may be sent to bot h the cache and the sram block simultaneously. if the reference is mappe d into the region defined by the sram, the sram provides the data back to the pro cessor, and the cache data discar ded. accesses from the sram module are not cached. the sram is dual-ported to provide dma access. th e sram is partitioned into two physical memory arrays to allow simultaneous access to both arrays by the processor core and another bus master. see chapter 8, ?system control module (scm) ? for more information. 5.3 sram programming model the sram programming model include s a description of the sram ba se address register (rambar), sram initialization, a nd power management. 5.3.1 sram base address register (rambar) the configuration information in the sram base address register (rambar) controls the operation of the sram module. ? the rambar holds the base ad dress of the sram. the movec instruction provides write-only access to this register. ? the rambar can be read or written from the debug module in a similar manner. ? all undefined bits in the register are reserved. these bits are ignor ed during writes to the rambar, and return zeroes when read from the debug module. ? the rambar valid bit is cleared by reset, di sabling the sram module. all other bits are unaffected. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 static ram (sram) 5-2 freescale semiconductor the rambar contains several control fields. these fields are shown in figure 5-1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 field ba31 ba30 ba29 ba28 ba27 ba26 ba25 ba2 4 ba23 ba22 ba21 ba20 ba19 ba18 ba17 ba16 reset undefined r/w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field ? pri1 pri2 spv wp ? c/i sc sd uc ud v reset undefined 0 r/w w address cpu + 0xc05 figure 5-1. sram base address register (rambar) table 5-1. sram base address register bits name description 31?16 ba base address. defines the 0-modulo-64k base address of the sram module. by programming this field, the sram may be located on any 64-kbyte boundary within the processor?s 4-gbyte address space. 15?12 ? reserved, should be cleared. 11?10 pri1, pri2 priority bit. pri1 determines if dma or cpu has priority in upper 32k bank of memory. pri2 determines if dma or cpu has priority in lower 32k bank of memory. if bit is set, cpu has priority. if bit is cleared, dma has priority. priority is determined according to the following table. note: the freescale-recommended setting for the priority bits is 00. 9 spv secondary port valid. allows access by dma 0 dma access to memory is disabled. 1 dma access to memory is enabled. note: the bde bit in the second rambar register must also be set to allow dual port access to the sram. for more information, see section 8.4.2, ?memo ry base address register (rambar) .? 8 wp write protect. allows only read accesses to the sram. when this bit is set, any attempted write access will generate an access error exception to the coldfire processor core. 0 allows read and write accesses to the sram module 1 allows only read accesses to the sram module 7?6 ? reserved, should be cleared. pri[1:2] upper bank priority lower bank priority 00 dma accesses dma accesses 01 dma accesses cpu accesses 10 cpu accesses dma accesses 11 cpu accesses cpu accesses mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 static ram (sram) freescale semiconductor 5-3 5.3.2 sram initialization after a hardware reset, the cont ents of the sram module are undefi ned. the valid bit of the rambar is cleared, disabling the module. if the sram requires init ialization with instructions or data, the following steps should be performed: 1. load the rambar mapping the sram module to the desired location within the address space. 2. read the source data and write it to the sram . there are various instructions to support this function, including memory-to- memory move instructions, or the movem opcode. the movem instruction is optimized to generate line -sized burst fetches on 0-modulo-16 addresses, so this opcode generally pr ovides maximum performance. 3. after the data has been loaded into the sram, it may be appropriate to load a revised value into the rambar with a new set of attributes. thes e attributes consist of the write-protect and address space mask fields. the coldfire processor or an exte rnal emulator using the debug module can perform these initialization functions. 5.3.3 sram initialization code the following code segment describes how to initiali ze the sram. the code sets the base address of the sram at 0x20000000 and then initi alizes the sram to zeros. rambase equ $20000000 ;set this variable to $20000000 ramvalid equ $00000001 move.l #rambase+ramvalid,d0 ;load rambase + valid bit into d0. movec.l d0, rambar ;load rambar and enable sram 5?1 c/i, sc, sd, uc, ud address space masks (asn) these five bit fields allow certain types of accesses to be ?masked,? or inhibited from accessing the sram module. the address space mask bits are: c/i = cpu space/interrupt acknowledge cycle mask sc = supervisor code address space mask sd = supervisor data address space mask uc = user code address space mask ud = user data address space mask for each address space bit: 0 an access to the sram module can occur for this address space 1 disable this address space from the sram module. if a reference using this address space is made, it is inhibited from accessing the sram module, and is processed like any other non-sram reference. these bits are useful for po wer management as detailed in section 5.3.4, ?power management .? 0 v valid. a hardware reset clears this bit. w hen set, this bit enables the sram module; otherwise, the module is disabled. 0 contents of rambar are not valid 1 contents of rambar are valid table 5-1. sram base address register (continued) bits name description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 static ram (sram) 5-4 freescale semiconductor the following loop initializes the entire sram to zero lea.l rambase,a0 ;load pointer to sram move.l #16384,d0 ;load loop counter into d0 sram_init_loop: clr.l (a0)+) ;clear 4 bytes of sram subq.l #1,d0 ;decrement loop counter bne.b sram_init_loop ;if done, then exit; else continue looping 5.3.4 power management as noted previously, depending on the configuration defined by the rambar, instruction fetch and operand read accesses may be sent to the sram and cache simultaneously . if the access is mapped to the sram module, it sources the read data and the unified cache access is discarded. if the sram is used only for data operands, asserting the asn bits associated with instru ction fetches can decrease power dissipation. additionally, if the sr am contains only instructions, ma sking operand accesses can reduce power dissipation. table 5-2 shows some examples of typical rambar settings. table 5-2. typical rambar setting examples data contained in sram rambar[7:0] code only 0x2b data only 0x35 both code and data 0x21 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor 6-1 chapter 6 coldfire flash module (cfm) the mcf5282 incorporates superflash? technology licensed from sst. the coldfi re flash module (cfm) is constructed with eight banks of 32k x 16-bit flash to generate a 512-kbyte, 32-bit wide electrically erasable and programmable read-onl y memory array. the cfm is ideal for program and data storage for single-chip applicati ons and allows for field reprogramming without external high-voltage sources. the voltage required to program and erase the flash is generated internally by on-chip charge pumps. program and erase operations are pe rformed under cpu control through a command-driven interface to an internal state m achine. all flash physical bl ocks can be programmed or erased at the same time; however, it is not possible to read from a flash phy sical block while the same block is being programmed or erased. the array used makes it possible to program or er ase one pair of flash physical blocks under the control of software routines executing out of another pair. note the mcf5281 and mcf5214 implements only 256 kbytes of flash; half that of the mcf5282 and mcf5216. the mcf5280 does not contain a flash module. 6.1 features features of the cfm include: ? 512-kbytes of flash memory on the mcf5282 and mcf5216 ? 256-kbytes of flash memory on the mcf5281 and mcf5214 ? basic flash access time of 2 cl ock cycles. optimized processor fl ash interface reduces basic flash access time through interleaving and speculative reads. ? automated program and erase operation ? concurrent verify, program, and erase of all array blocks ? read-while-write capability ? optional interrupt on command completion ? flexible scheme for protection against accidental program or erase operations ? access restriction controls for both superv isor/user and data/pr ogram space operations ? security for single- chip applications ? single power supply (system v dd ) used for all module operations ? auto-sense amplifier timeout for low-power, low-freque ncy read operations note enabling flash security will disable bdm communications. note when flash security is enabled, the chip will boot in single-chip mode regardless of the extern al reset configuration. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire flash module (cfm) 6-2 freescale semiconductor 6.2 block diagram the cfm module shown in figure 6-1 contains the flash physical bloc ks, the coldfire flash bus and ip bus interfaces, flash interface, regist er blocks, and the bist engine. each 128-kbyte flash physical bloc k is arranged as two 32,768-word (16 bits) memory arrays. each of these memory arrays is designated as x h or x l, where x represents one of the f our flash physical blocks (0?3) and h/l represents th e high or low 16 bits of each longword of logical memory. ea ch of these words may be read as either individua l bytes or aligned words. ali gned longword acces s is provided by concatenating the outputs of the each of the two memory arrays within the flash physical block. simple reads of bytes, aligned words, and aligned longwords require two 66-mhz clock cycles, although the processor?s flash interface includes logic that reduces the effective access time through two-way longword interleaving and speculative reads. flash physical blocks are interleaved on longword (4-byte) boundaries . therefore, all flash program, erase, and verify commands operate on adjacent flash physical blocks and are initiated with a single aligned 32-bit write to the appropr iate array location. any other write operation will cause a cycle termination transfer error. page erase operates simu ltaneously on two interleavi ng erase pages in adjacent flash physical blocks. each flash phys ical block is organized as 1024 rows of 128 bytes with a single erase page consisting of 8 rows (1024 bytes). since page erase operates simultaneous ly on two interleaving and adjacent physical fl ash blocks, each erase row is comprised of four 16-bit entries in each of two memory arrays within each of two flash phys ical blocks. the first row of flash is made up of 0h_0l_1h_1l [0] through 0h_0l_1h_1l [31], where each [ n ] represents four 16-bit words from each memory array in each of two physical bl ocks, for a total of 256 bytes. since a single erase page consists of 8 rows of 256 bytes, or 2048 bytes, the first erase page is physically located at 0h_0l_1h_1l [0] through 0h_0l_1h_1l [255]. mass erase operates simultan eously on two adjacent flash physica l blocks in their entirety and erases a total of 256 kbytes of flash space. theref ore, it takes two mass er ase operations, one on mass erase block 0 and one on mass eras e block 1, to erase th e full 512k cfm flash on the mcf5282 and mcf5216. an erased flash bit reads 1 and a programmed flash bit reads 0. the cfm features a sense amplifier timeout (sato) block that automatically reduces cu rrent consumption during reads at low system clock frequencies. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire flash module (cfm) freescale semiconductor 6-3 figure 6-1. cfm block diagram flash interface ? ? ? sato sato sato sato bist engine internal bus memory array backdoor access flash control registers block 0h 32k x 16 memory array block 0l 32k x 16 memory array block 3h 32k x 16 memory array block 3l 32k x 16 flash physical block 0 flash physical block 3 note: mass erase block 0 (256 kbytes) = flash physical block 0 and flash physical block 1. mass erase block 1 (256 kbytes) = flash physical block 2 and flash physical block 3 ( mcf5282 and mcf5216 only) v ddf v ssf mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire flash module (cfm) 6-4 freescale semiconductor 6.3 memory map figure 6-2 shows the memory map for the cfm array. the cfm array can reside anywhere in the memory space of the mcu. the starting address of the array is determined by the cfm array base address which must reside on a natural si ze boundary; that is, the cf m array base address must be an integer multiple of the array size. the cfm re gister space must reside on a 64 byte boundary as determined by the cfm register base address. figure 6-2 shows how multiple 32,768 by 16-bit fl ash physical blocks interleave to form a contiguous non-vol atile memory space. each pair of 32-bit blocks (eve n and odd) inte rleave every 4 bytes to form a 256-kbyte section of memory. note the cfm on the mcf5281 and mcf5214 is constructed with four banks of 32k x 16-bit flash arrays to generate 256 kbytes of 32-bit flash memory. figure 6-2. cfm array memory map the cfm module has hardware interlocks to prot ect data from accidental corruption. the < coldfire flash module (cfm) freescale semiconductor 6-5 6.3.1 cfm configuration field the cfm configuration field compri ses 24 bytes of reserved array me mory space that determines the module protection and access re strictions out of reset. data to secure the flas h from unauthorized access is also stored in the cfm configuration field. table 6-1 describes each byte used in this field. 6.3.2 flash base address register (flashbar) the configuration informa tion in the flash base a ddress register (flashbar) controls the operation of the flash module. ? the flashbar holds the base address of the flash. the movec instruction provides write-only access to this register. ? the flashbar can be read or written from the debug module in a similar manner. ? all undefined bits in the register are reserved. these bits are ignor ed during writes to the flashbar, and return zeroes when read from the debug module. ? the back door enable bit, flashb ar[bde], is cleared at reset, di sabling back door access to the flash. ? the flashbar valid bit is pr ogrammed according to the chip mode selected at reset (see chapter 27, ?chip configuration module (ccm) ? for more details). all other bits are unaffected. the flashbar register contains several control fields. these fields are shown in figure 6-3 note the default value of the flashb ar is determined by the chip configuration select ed at reset (see chapter 27, ?chip configuration module (ccm)? for more information). if ex ternal boot mode is used, then the flashbar located in the processo r?s cpu space will be invalid and it must be initialized with the valid bi t set before the cpu (or modules) can access the on-chip flash. table 6-1. cfm configuration field address offset (from array base address) size in bytes description 0x0000_0400?0x0000_0407 8 back door comparison key 0x0000_0408?0x0000_040b 4 flash prog ram/erase sector protection blocks 0h/0l (see section 6.3.4.4, ?cfm protection register (cfmprot) ?) 0x0000_040c?0x0000_040f 4 flash supervisor/user space restrictions blocks 0h/0l (see section 6.3.4.5, ?cfm supervisor access register (cfmsacc) ?) 0x0000_0410?0x0000_0413 4 flash program/data space restrictions blocks 0h/0l (see section 6.3.4.6, ?cfm da ta access register (cfmdacc) ?) 0x0000_0414?0x0000_0417 4 flash security longword (see section 6.3.4.3, ?cfm security register (cfmsec) ?) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire flash module (cfm) 6-6 freescale semiconductor note flash accesses (reads/writ es) by a bus master othe r than the core, (dma controller or fast ethernet controller), or writes to flash by the core during programming must use the backdoor fl ash address of ipsbar plus an offset of 0x0400_0000. for example, for a dma transfer from the first location of flash when ipsbar is still at its de fault location of 0x4000_0000, the source register would be loaded with 0x4400_0000. backdoor access to flash for reads ca n be made by the bus master, but it takes 2 cycles longer than a direct read of the flash if using its flashbar address. note the flash is marked as valid on reset based on the rcon (reset configuration) pin state. flash space is valid on reset when booting in single chip mode (rcon pin asserted and d[ 26]/d[17]/d[16] set to 110), or when booting internally in master mode (rcon asserted and d[26]/d[17]/d[16] are set to 111 and d[18] and d[19] are set to 00). see chapter 27, ?chip configuration module (ccm) ? for more details. when the default reset configuration is not overriden, the device (by default) boots in single chip mode and the flash space will be mark ed as valid at address 0x0. the flash configuration field is checked during th e reset sequence to see if the flash is secured. if it is the part will always boot from internal flash, since it will be marked as valid, regardless of what is done for chip configuration. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 16 field ba31 ba30 ba29 ba28 ba27 ba26 ba25 ba24 ba23 ba22 ba21 ba20 ba19 ? reset 0000_0000_0000_0000 r/w r/w 15 9876543210 field ? wp ? c/i sc sd uc ud v reset 0000_0001_0010_000 see note r/w r r/w address cpu + 0xc04 note: the reset value for the valid bit is determined by the chip mode selected at reset (see chapter 27, ?chip configuration module (ccm) ?). figure 6-3. flash base address register (flashbar) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire flash module (cfm) freescale semiconductor 6-7 6.3.3 cfm registers the cfm module also contains a set of control and st atus registers. the memory map for these registers and their accessibility in supervisor and user modes is shown in table 6-3 . table 6-2. flashbar field descriptions bits name description 31?19 ba[31:18] base address field. defines the 0-modulo-512k base address of the flash module. by programming this field, the flash may be located on any 512kbyte boundary within the processor?s four gigabyte address space. 18?9 ? reserved, should be cleared. 8 wp write protect. read only. allows only read accesses to the flash. this bit is always set and any attempted write access will generate an access error exception to the coldfire processor core. 0 allows read and write accesses to the flash module 1 allows only read accesses to the flash module 7?6 ? reserved, should be cleared. 5?1 c/i, sc, sd, uc, ud address space masks (asn). these five bit fields allow certain types of accesses to be ?masked,? or inhibited from accessing the flash module. the address space mask bits are: c/i cpu space/interrupt acknowledge cycle mask sc supervisor code address space mask sd supervisor data address space mask uc user code address space mask ud user data address space mask for each address space bit: 0 an access to the flash module can occur for this address space 1 disable this address space from the flash module. if a reference using this address space is made, it is inhibited from accessing the flash module, and is processed like any other non-flash reference. these bits are useful for po wer management as detailed in chapter 7, ?power management .? 0 v valid. when set, this bit enables the flash module; otherwise, the module is disabled. 0 contents of flashbar are not valid 1 contents of flashbar are valid table 6-3. cfm register address map ipsbar offset bits 31?24 bits 23?16 bits 15?8 bits 7?0 access 1 0x1d_0000 cfmmcr cfmclkd reserved 2 s 0x1d_0004 reserved 2 s 0x1d_0008 cfmsec s 0x1d_000c reserved 2 s 0x1d_0010 cfmprot s mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire flash module (cfm) 6-8 freescale semiconductor 6.3.4 register descriptions the flash registers are desc ribed in this subsection. 6.3.4.1 cfm configuration register (cfmcr) the cfmcr is used to configure and control the operation of the cfm array. bits 10 -5 in the cfmcr register are r eadable and writable with restrictions. 0x1d_0014 cfmsacc s 0x1d_0018 cfmdacc s 0x1d_001c reserved 2 s 0x1d_0020 cfmustat reserved 2 s 0x1d_0024 cfmcmd reserved 2 s 1 s = supervisor access only. user mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error. 2 addresses not assigned to a register and undefined register bits are reserved for expansion. write accesses to these reserved address spaces and reserved register bits have no effect. 15 11 10 9 8 7 6 5 4 0 field ? lock pvie aeie cbeie ccie keyacc ? reset 0000_0000_0000_0000 r/w r/w address ipsbar + 0x1d_0000 figure 6-4. cfm module confi guration register (cfmcr) table 6-4. cfmcr field descriptions bits name description 15?11 ? reserved, should be cleared. 10 lock write lock control. the lock bi t is always readable and is set once. 1 cfmprot, cmfsacc, and cfmdacc register are write-locked. 0 cfmprot, cmfsacc, and cfmdacc register are writable. 9 pvie protection violation interrupt enable. the pvie bit is readable and writable. the pvie bit enables an interrupt in case the protection violation flag, pviol, is set. 1 an interrupt will be requested whenever the pviol flag is set. 0 pviol interrupts disabled. 8 aeie access error interrupt enable. the aeie bit is readable and writable. the aeie bit enables an interrupt in case the access error flag, accerr, is set. 1 an interrupt will be requested whenever the accerr flag is set. 0 accerr interrupts disabled. table 6-3. cfm register address map ipsbar offset bits 31?24 bits 23?16 bits 15?8 bits 7?0 access 1 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire flash module (cfm) freescale semiconductor 6-9 6.3.4.2 cfm clock divider register (cfmclkd) the cfmclkd is used to set the frequency of the clock used for timed events in program and erase algorithms. all bits in cfmclkd are readable. bit 7 is a read-only status bit, while bits 6?0 can only be written once. 7 cbeie command buffer empty interrupt enable. the cbeie bit is readable and writable. cbeie enables an interrupt request when the command buffer for the flash physical blocks is empty. 1 request an interrupt whenever the cbeif flag is set. 0 command buffer empty interrupts disabled 6 ccie command complete interrupt enable. the ccie bit is readable and writable. ccie enables an interrupt when the command executing for the flash is complete. 1 request an interrupt whenever the ccif flag is set. 0 command complete interrupts disabled 5 keyacc enable security key writing. the keyacc bit is readable and only writable if the keyen bit in the cfmsec register is set. 1 writes to the flash array are interpreted as keys to open the back door. 0 writes to the flash array are interpreted as the start of a program, erase, or verify sequence. 4?0 ? reserved, should be cleared. 765 0 field divld prdiv8 div reset 0000_0000 r/w r r/w address ipsbar + 0x1d_0002 figure 6-5. cfm clock divider register (cfmclkd) table 6-5. cfmclkd field descriptions bits name description 7 divld clock divider loaded 1 cfmclkd has been written since the last reset. 0 cfmclkd has not been written. 6 prdiv8 enable prescaler divide by 8 1 enables a prescaler that divides the cfm clock by 8 before it enters the cfmclkd divider. 0 the cfm clock is fed directly into the cfmclkd divider. 5?0 div clock divider field. the combination of prdiv8 and div[ 5:0] effectively divides the cfm input clock down to a frequency between 150 khz and 200 khz. the frequency range of the cfm clock is 150 khz to 102.4 mhz. table 6-4. cfmcr field descriptions bits name description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire flash module (cfm) 6-10 freescale semiconductor note cfmclkd must be written with an appropriate value before programming or erasing the flash array. refer to section 6.4.3.1, ?setting the cfmclkd register .? 6.3.4.3 cfm security register (cfmsec) the cfmsec controls the flash security features. note enabling flash security will disable bdm communications. note when flash security is enabled, the chip will boot in single-chip mode regardless of the extern al reset configuration. 31 30 29 16 field keyen secstat ? reset see note r/w r 15 0 field sec reset see note r/w r address ipsbar + 0x1d_0008 note: the secstat bit reset value is determined by the security state of the flash. all ot her bits in the register are loaded at reset from the flash security l ongword stored at the array base address + 0x0000_0414. figure 6-6. cfm security register (cfmsec) table 6-6. cfmsec field descriptions bits name description 31 keyen enable back door key to security 1 back door to flash is enabled. 0 back door to flash is disabled. 30 secstat flash security status 1 flash security is enabled 0 flash security is disabled mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire flash module (cfm) freescale semiconductor 6-11 the security features of the cfm are described in section 6.5, ?flash security operation .? 29?16 ? reserved. should be cleared. 15?0 sec[15:0] security field. the sec bits defin e the security state of the device; see below. table 6-6. cfmsec field descriptions bits name description sec[15:0] description 0x4ac8 flash secured 1 1 the 0x4ac8 value was chosen because it represents the coldfire halt instruction, making it unlikely that compiled code accidentally programmed at the security longword in the flash configuration field location would unintentionally secure the device. all other combinations flash unsecured mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire flash module (cfm) 6-12 freescale semiconductor 6.3.4.4 cfm protection register (cfmprot) the cfmprot specifies which flash logical sectors are pr otected from program and erase operations. the cfmprot register is always readable and only writeable when lock = 0. to change which logical sectors are protecte d on a temporary basis, write cfmprot wi th a new value after the lock bit in cfmcr has been cleared. to change the value of cfmprot that will be loaded on reset, the protection byte in the flash configuration fiel d must first be temporarily unprotect ed using the met hod just described before reprogramming the protection bytes. then the flash protection longwor d at offset 0x1d_0400 must be written with the desired value. the cfmprot controls the protection of thirty-two 16-kbyte flash logical sectors in the 512-kbyte flash array. figure 6-8 shows the association between each bi t in the cfmprot and its corresponding logical sector. note since the mcf5281 and mcf5214 devi ces contain a 256-kbyte flash, only cfmprot[15:0] is used. 31 16 field prot reset see note r/w r/w 15 0 field prot reset see note r/w r/w address ipsbar + 0x1d_0010 note: the cfmprot register is loaded at reset from t he flash program/erase sector protection longword stored at the array base address + 0x0000_0400. figure 6-7. cfm protection register (cfmprot) table 6-7. cfmprot field descriptions bits name description 31?0 prot[31:0] sector protection. each flash logical sector can be protected from program and erase operations by setting its corresponding prot bit. 1 logical sector is protected. 0 logical sector is not protected. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire flash module (cfm) freescale semiconductor 6-13 figure 6-8. cfmprot protection diagram 6.3.4.5 cfm supervisor access register (cfmsacc) the cfmsacc specifies the supervisor/user ac cess permissions of fl ash logical sectors. 31 16 field supv reset see note r/w r/w 15 0 field supv reset see note r/w r/w address ipsbar + 0x1d_0014 note: the cfmprot register is loaded at reset from the flash supervisor/user space restrictions longword stored at the array base address + 0x0000_040c. figure 6-9. cfm supervisor access register (cfmsacc) (array_base + 0x0000_0000) } 16kbyte sector (array_base + 0x0007_ffff) ? ? ? sector 0 sector 1 sector 2 sector 31 (array_base + 0x0000_4000) (array_base + 0x0000_8000) protect[31] protect[2] protected flash logical sectors as defined by cfmprot register (array_base + 0x0007_c000) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire flash module (cfm) 6-14 freescale semiconductor 6.3.4.6 cfm data access register (cfmdacc) the cfmdacc specifies the data/program a ccess permissions of fl ash logical sectors. table 6-8. cfmsacc field descriptions bits name description 31?0 supv[31:0] supervisor address space assignment. the supv[31:0] bits are always readable and only writable when lock = 0. each flash logical sector can be mapped into supervisor or unrestricted address space. cfmsacc uses the same correspondence between logical sectors and register bits as does cfmprot. see figure 6-8 for details. when a logical sector is mapped into supervisor address space, only cpu supervisor accesses will be allowed. a cpu user access to a location in supervisor address space will result in a cycle termination transfer error. when a logical sector is mapped into unrestricted address space both supervisor and user accesses are allowed. 1 logical sector is mapped in supervisor address space. 0 logical sector is mapped in unrestricted address space. 31 16 field data reset see note r/w r/w 15 0 field data reset see note r/w r/w address ipsbar + 0x1d_0018 note: the cfmprot register is loaded at reset from the flash program/data space restrictions longword stored at the array base address + 0x0000_0410. figure 6-10. cfm data access register (cfmdacc) table 6-9. cfmdacc field descriptions bits name description 31?0 data[31:0] data address space assignment. the data[31:0] bits are always readable and only writable when lock = 0. each flash logical sector can be mapped into data or both data and program address space. cfmdacc uses the same correspondence between logical sectors and register bits as does cfmprot. see figure 6-8 for details. when a logical sector is mapped into data address space, only cpu data accesses will be allowed. a cpu program access to a location in data address space will result in a cycle termination transfer error. when an array sector is mapped into both data and program address space both data and program accesses are allowed. 1 logical sector is mapped in data address space. 0 logical sector is mapped in data and program address space . mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire flash module (cfm) freescale semiconductor 6-15 6.3.4.7 cfm user status register (cfmustat) the cfmustat reports flash state machine command status, array access errors , protection violations, and blank check status. note only one cfmustat bit should be cleared at a time. 765 1 0 field cbeif ccif pviol accerr ? blank ? reset 1100_0000 r/w r/w r r/w address ipsbar + 0x1d_0020 figure 6-11. cfm user status register (cfmustat) table 6-10. cfmustat field descriptions bits name description 7 cbeif command buffer empty interrupt flag. th e cbeif flag indicates that the command buffer for the interleaved flash physical blocks is empty and that a new command sequence can be started. clear cbeif by wr iting it to 1. writing a 0 to cbeif has no effect but can be used to abort a command sequence. the cbeif bit can trigger an interrupt request if the cbeie bit is set in cfmmcr. while cbeif is clear, the cfmcmd register is not writable. 1 command buffer is ready to accept a new command. 0 command buffer is full. 6 ccif command complete interrupt flag. the ccif flag indicates that no commands are pending for the flash physical blocks. ccif is set and cleared automatically upon start and completion of a command. writin g to ccif has no effect. the ccif bit can trigger an interrupt request if the ccie bit is set in cfmcr. 1 all commands are completed 0 command in progress 5 pviol protection violation flag. the pviol flag indicates an attempt was made to initiate a program or erase operation in a flash logical sector denoted as protected by cfmprot. clear pviol by writing it to 1. writing a 0 to pviol has no effect. while pviol is set in any this register, it is not possible to launch another command. 1 a protection violation has occurred 0 no failure 4 accerr access error flag. the accerr flag in dicates an illegal access to the cfm array or registers caused by a bad program or erase sequence. accerr is cleared by writing it to 1. writing a 0 to accerr has no effect. while accerr is set in this register, it is not possible to launch another command. see section 6.4.3.4, ?flash user mode illegal operations ,? for details on what sets the accerr flag. 1 access error has occurred 0 no failure 3 ? reserved, should be cleared. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire flash module (cfm) 6-16 freescale semiconductor 6.3.4.8 cfm command register (cfmcmd) the cfmcmd is the register to which flash pr ogram, erase, and verify commands are written. cfmcmd is readable and writable in all modes. wr ites to bit 7 have no ef fect and reads return 0. 6.4 cfm operation the cfm registers, subject to the restrictions previously noted, can generally be read and written (see section 6.3.4, ?register descriptions ? for details). reads of the cf m array occur nor mally and writes behave according to the sett ing of the keyacc bit in cfmcr. progr am, erase, and verify operations are 2 blank erase verified flag. the blank flag indicates that the erase verify command (rdary1) has checked the two interleaved flash physical blocks and found them to be blank. clear blank by writing it to 1. writing a 0 has no effect. 1 flash physical blocks verify as erased. 0 if an erase verify command has been requested, and the ccif flag is set, then the selected flash physical blocks are not blank. 1?0 ? reserved, should be cleared. 76 0 field ? cmd reset 0000_0000 r/w r/w address ipsbar + 0x1d_0024 figure 6-12. cfm command register (cfmcmd) table 6-11. cfmcmd field descriptions bits name description 7 ? reserved, should be cleared. 6?0 cmd[6:0] command. valid flash us er mode commands are shown in ta b l e 6 - 1 2 . writing a command in user mode other than those listed in ta bl e 6 - 1 2 will set the accerr flag in cfmustat. table 6-12. cfmcmd user mode commands command name description 0x05 rdary1 erase verify (all 1s) 0x20 pgm longword program 0x40 pgers page erase 0x41 masers mass erase 0x06 pgersver page erase verify table 6-10. cfmustat field descriptions bits name description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire flash module (cfm) freescale semiconductor 6-17 initiated by the cpu. special cases of user mode apply when the cp u is in low-power or debug modes and when the mcu boots in mast er mode or emulation mode. 6.4.1 read operations a valid read operation occurs whenever a transfer reque st is initiated by the coldfire core, the address is equal to an address within the vali d range of the cfm memory space, a nd the read/write control indicates a read cycle. in order to reduce power at low sy stem clock frequencies, the sens e amplifier timeout (sato) block minimizes the time during which the sense amplifiers are enabled for r ead operations. the sense amplifier enable signals to the flash ti meout after approximately 50 ns. 6.4.2 write operations a valid write operation occurs whenever a transfer reque st is initiated by the coldfire core, the address is equal to an address within the vali d range of the cfm memory space, a nd the read/write control indicates a write cycle. the action taken on a valid cfm array write depends on th e subsequent user comma nd issued as part of a valid command sequence. only ali gned 32-bit write operations are allowed to the cfm array. byte and word write operations will result in a cycle termination transfer error. 6.4.3 program and erase operations read and write operations are both us ed for the program and erase algorit hms described in this subsection. these algorithms are controlled by a state machine w hose timebase is derived from the cfm module clock via a programmable counter. the command register and associated address and data buffers operate as a two stage fifo so that a new command along with the necessary addre ss and data can be stored while the previous command is still in progress. this pipelining speeds when programming mo re than one longword on a specific row, as the charge pumps can be kept on in between two programmi ng commands, thus savi ng the overhead needed to set up the charge pumps. buffer empty and comman d completion are indicated by flags in the cfm user status register. interrupts wi ll be requested if enabled. 6.4.3.1 setting the cfmclkd register prior to issuing any program or erase commands, cfmclkd must be written to set the flash state machine clock (fclk). the cfm module runs at the system clock frequency 2, but fclk must be divided down from this frequency to a frequency between 150 khz and 200 khz. use the following procedure to set the prdiv8 a nd div[5:0] bits in cfmclkd: 1. if f sys 2 is greater than 12.8 mhz, prdiv8 = 1; otherwise prdiv8 = 0. 2. determine div[5:0] by using the following equation. keep only th e integer portion of the result and discard any fraction. do not round the result. 3. thus the flash state machine clock will be: f sys 2 x 200khz x (1 + (prdiv8 x 7)) div[5:0] = mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire flash module (cfm) 6-18 freescale semiconductor consider the following example for f sys = 66 mhz: so, for f sys = 66 mhz, writing 0x54 to cfmclkd will set f clk to 196.43 khz which is a valid frequency for the timing of program and erase operations. warning for proper program and erase opera tions, it is critical to set f clk between 150 khz and 200 khz. array damage due to overstress can occur when f clk is less than 150 khz. incomplete programming and eras ure can occur when f clk is greater than 200 khz. note command execution time increases proportionally with the period of f clk . when cfmclkd is written, the divld bit is set automatically. if divld is 0, cfmclkd has not been written since the last reset. program and erase commands will not exec ute if this regi ster has not been written (see section 6.4.3.4, ?flash user mode illegal operations ?). 6.4.3.2 program, erase, and verify sequences a command state machine is used to supervise the write sequencin g of program, er ase, and verify commands. to prepare for a command, the cfmustat[cbeif] flag should be tested to ensure that the address, data, and command buffers are empty. if cbeif is set, the command write sequence can be started. this three-step command write seque nce must be strictly followed. no intermediate writes to the cfm module are permitted between these three steps. the command write sequence is: 1. write the 32-bit longword to be programmed to it s location in the cfm arra y. the address and data will be stored in internal buffers. all address bits are valid for program commands. the value of the data written for verify and er ase commands is ignored. for mass erase or verify, the address can be any location in the cfm array. for page erase, address bits [9:0] are ignored. f sys 2 x (div[5:0] + 1) x (1 + (prdiv8 x 7)) f clk = f sys 2 x 200khz x (1 + (prdiv8 x 7)) div[5:0] = 66 mhz 400 khz x (1 + (1 x 7)) = = 20 f sys 2 x (div[5:0] + 1) x (1 + (prdiv8 x 7)) f clk = 66 mhz 2 x (20 + 1) x (1 + (1 x 7)) = = 196.43 khz mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire flash module (cfm) freescale semiconductor 6-19 note the page erase command operates simu ltaneously on adjacent erase pages in two interleaved flas h physical blocks. thus, a single erase page is effectively 2 kbyte. 2. write the program, erase, or verify command to cfmcmd , the command buffer. see section 6.4.3.3, ?flash valid commands .? 3. launch the command by writing a 1 to the cbeif flag. this clears cbeif. when command execution is complete, the flash state machine se ts the ccif flag. the cbeif flag is also set again, indicating that the address, data, and command buffers are ready for a new command sequence to begin. the flash state machine flags erro rs in command write sequences by means of the accerr and pviol flags in the cfmustat register . an erroneous command write sequence self-a borts and sets the appropriate flag. the acce rr or pviol flags must be cleared before commencing another command write sequence. note by writing a 0 to cbeif, a command sequence can be aborted after the longword write to the cf m array or the command write to the cfmcmd and before the command is launched. the accerr flag will be set on aborted commands and must be cl eared before a new command write sequence. a summary of the programmi ng algorithm is shown in figure 6-13 . the flow is simila r for the erase and verify algorithms with the exce ptions noted in step 1 above. 6.4.3.3 flash valid commands table 6-13 summarizes the valid flash user commands. table 6-13. flash user commands cfmcmd meaning description 0x05 erase verify verify that all 256 kbytes of flash from two interleaving physical blocks are erased. if both blocks are erased, the blank bit will be set in the cfmustat register upon command completion. 0x20 program program a 32-bit longword. 0x40 page erase erase 2 kbyte of flash. two 1024- byte pages from interleaving physical blocks are erased in this operation. 0x41 mass erase erase all 256 kbytes of flash from two interleaving physical blocks. a mass erase is only possible when no protect bits are set for that block. 0x06 page erase verify verify that the two 1024-byte pages are erased. if both pages are erased, the blank bit will be set in the cfmustat register upon command completion. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire flash module (cfm) 6-20 freescale semiconductor figure 6-13. example program algorithm write cfmclkd read cfmclkd divld set? write program data write program command 0x20 to cfmcmd write 0x80 to clear cfmustat yes no cbeif bit yes clock register written check 1. 2. 3. cfmustat accerr bit write 0x10 to clear no yes no protection violation check access error check read cfmustat no no address, data, command buffer empty check next write? yes no to array address cfmustat pviol bit write 0x20 to clear yes bit polling for command completion check read cfmustat yes note: command sequence aborted by writing 0x00 to cfmustat note: command sequence aborted by writing 0x00 to cfmustat exit read cfmustat no start yes cbeif set? pviol set? accerr set? cbeif set? ccif set? mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire flash module (cfm) freescale semiconductor 6-21 6.4.3.4 flash user mode illegal operations the accerr flag will be set during a command write sequence if any of the il legal operations below are performed. such operations will cause the command sequence to immediately abort. 1. writing to the cfm array before initializing cfmclkd. 2. writing to the cfm array while in emulation mode. 3. writing a byte or a word to the cfm array. only 32-bit longword programming is allowed. 4. writing to the cfm array while cbeif is not set. 5. writing an invalid user command to the cfmcmd. 6. writing to any cfm other than cfmcmd after writing a longword to the cfm array. 7. writing a second command to cfmcmd before executing the previously written command. 8. writing to any cfm register other than cfmu stat (to clear cbeif) after writing to the command register. 9. entering stop mode while a program or erase comma nd is in progress. 10. aborting a command sequence by writing a 0 to cbeif after the longword write to the cfm array or after writing a command to cfmcmd and before launching it. the pviol flag will be set duri ng a command write sequence after th e longword write to the cfm array if any of the illegal operations be low are performed. such operations will cause the command sequence to immediately abort. 1. writing to an address in a protected area of the cfm array. 2. writing a mass erase command to cfmcmd wh ile any logical sector is protected (see section 6.3.4.4, ?cfm protecti on register (cfmprot) ?). if a flash physical block is read during a program or erase operati on on that block (cfmustat bit ccif = 0), the read will return non-valid data and the accerr flag will not be set. 6.4.4 stop mode if a command is active (ccif = 0) when the mc u enters stop mode, the command sequence monitor performs the following: 1. the command in progress aborts 2. the flash high voltage circuitry switches off and any pending command (cbeif = 0) does not executed when the mcu exits stop mode. 3. the ccif and accerr flags are set if a comma nd is active when the mcu enters stop mode. note the state of any longwor d(s) being programmed or any erase pages/physical blocks being erased is not guaranteed if the mcu enters stop mode with a command in progress. warning active commands are immediately aborted when the mcu enters stop mode. do not execute the stop in struction during program and erase operations. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire flash module (cfm) 6-22 freescale semiconductor 6.4.5 master mode if the mcu is booted in master mode with an extern al memory selected as th e boot device, the cfm will not respond to the first transfer request out of reset. this will allow the external boot device to provide the reset vector and terminate the bus cycle. 6.5 flash security operation the cfm array provides secu rity information to the integration module and the rest of the mcu. a longword in the flash configuration fi eld stores this information. this l ongword is read automatically after each reset and is stored in the cfmsec register. note enabling flash security will disable bdm communications. note when flash security is enabled, the chip will boot in single chip mode regardless of the extern al reset configuration. in user mode, security can be bypa ssed via a back door access sche me using an 8-byte long key. upon successful completion of the back door access sequence, the module output signal a nd status bit indicating that the chip is secure are cleared. the cfm may be unsecured via one of two methods: 1. executing a back door access scheme. 2. passing an erase verify check. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire flash module (cfm) freescale semiconductor 6-23 6.5.1 back door access if the keyen bit is set, security can be bypassed by: 1. setting the keyacc bit in the cf m configuration re gister (cfmmcr). 2. writing the correct 8-byte back door compar ison key to the cfm ar ray at addresses 0x0000_0400 to 0x0000_0407. this operation must consist of two 32-bit writes to address 0x0000_0400 and 0x0000_0404 in that order. the two back door writ e cycles can be separated by any number of bus cycles. 3. clearing the keyacc bit. 4. if all 8 bytes written match the array contents at addresses 0x0000_0400 to 0x0000_0407, then security is bypassed until the next reset. note the security of the flash as define d by the flash secu rity longword at address 0x0000_0414 is not changed by the back door method of unsecuring the device. after the next reset the de vice is again secured and the same back door key remains in effect unless changed by program or erase operations. the back door method of unsecuring the device has no effect on the program and erase protections defined by the cfm protection regi ster (cfmprot). 6.5.2 erase verify check security can be disabled by verifying that the cfm array is blank. if requir ed, the mass erase command can be executed for each pair of flas h physical blocks that comprise th e array. the eras e verify command must then be executed for all flash physical blocks within the array. the cfm will be unsecured if the erase verify command determines that the entire array is bl ank. after the next reset, the security state of the cfm will be determined by the flash securi ty longword, which, after being erased, will read 0xffff_ffff, thus unsecuring the module. 6.6 reset the cfm array is not accessible for a ny operations via the address and da ta buses during reset. if a reset occurs while any command is in prog ress that command will immediatel y abort. the stat e of any longword being programmed or any erase pages/physical blocks bei ng erased is not guaranteed. 6.7 interrupts the cfm module can request an interrupt when all co mmands are completed or when the address, data, and command buffers are empty. table 6-14 shows the cfm interrupt mechanism. table 6-14. cfm interrupt sources interrupt source interrupt flag local enable command, data and address buffers empty cbeif (cfmustat) cbeie (cfmcr) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 coldfire flash module (cfm) 6-24 freescale semiconductor all commands are completed ccif (cfmustat) ccie (cfmcr) access error accerr (cfmustat) aeie (cfmcr) table 6-14. cfm interrupt sources (continued) interrupt source interrupt flag local enable mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor 7-1 chapter 7 power management the power management module (pmm) cont rols the device?s low-power operation. 7.1 features the following features support low-power operation. ? four modes of operation: ? run ?wait ? doze ?stop ? ability to shut down most peripherals independently ? ability to shut down the external clkout pin 7.2 memory map and registers this subsection provides a description of the memory map and registers. 7.2.1 programming model the pmm programming model c onsists of one register: ? the low-power control register (lpcr) specifies the low-power mode entered when the stop instruction is issued, and controls cl ock activity in this low-power mode. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 power management 7-2 freescale semiconductor 7.2.2 memory map 7.2.3 register descriptions the following subsection describes the pmm registers. 7.2.3.1 low-power interrupt control register (lpicr) implementation of low-power stop mode and exit from a low-power mode vi a an interrupt require communication between the cpu and logi c associated with the interrupt c ontroller. the lpicr is an 8-bit register that enables entry into lo w-power stop mode, and includes the se tting of the inte rrupt level needed to exit a low-power mode. note the setting of the low-power mode se lect (lpmd) field in the power management module?s low-power cont rol register (l pcr) determines which low-power mode the device enters when a stop instruction is issued. if this field is set to enter stop mode, then the enbstop bit in the lpicr must also be set. following is the sequence of operations needed to enable this functionality: 1. the lpicr is programmed, setting the enbstop bit (if stop mode is the desired low-power mode) and loading the appropria te interrupt priority level. 2. at the appropriate time, the processor exec utes the privileged stop instruction. once the processor has stopped execution, it asserts a specif ic processor status (p st) encoding. issuing the stop instruction when the lpicr[enbstop] bit is set causes the scm to enter stop mode. 3. the entry into a low-power mode is processe d by the low-power mode control logic, and the appropriate clocks (usually those related to the high-speed processo r core) are disabled. 4. after entering the low-power mode, the interrupt controller enables a combinational logic path which evaluates any unmasked interrupt requests. the device waits for an event to generate an interrupt request with a priority leve l greater than the value programmed in lpicr[xlpm_ipl[2:0]]. table 7-1. chip configuration module memory map ipsbar offset bits 31?24 bits 23?16 bits 15?8 bits 7?0 access 1 1 s = cpu supervisor mode access only. user mode accesses to su pervisor only addresses have no effect and result in a cycle termination transfer error. 0x0000_0010 core reset status register (crsr) 2 2 the crsr, cwcr, and cwsr are described in the system in tegration module. they are shown here only to warn against accidental writes to these registers when accessing the lpicr. core watchdog control register (cwcr) low-power interrupt control register (lpicr) core watchdog service register (cwsr) s 0x0011_0004 chip configuration register (ccr) 3 3 the ccr is described in the chip configuration module. it is shown here only to warn against accidental writes to this register when accessing the lpcr. reserved low-power control register (lpcr) s mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 power management freescale semiconductor 7-3 note only fixed (external) in terrupt can bring a device out of stop mode. to exit from other low-power m odes, such as doze or wait, either fixed or programmable interrupts may be used; however, the module generating the interrupt must be enabled in th at particular low-power mode. 5. once an appropriately-high interrupt request leve l arrives, the interrupt controller signals its presence, and the sim responds by assertin g the request to exit low-power mode. 6. the low-power mode control lo gic senses the request signal a nd re-enables the appropriate clocks. 7. with the processor clocks enabled, the co re processes the pending interrupt request. 76 43 0 field enbstop xlpm_ipl ? reset 1/0 0 1/0 0 undefined r/w r/w address ipsbar + 0x012 figure 7-1. low-power interrupt control register (lpicr) table 7-2. lpicr field descriptions bits name description 7 enbstop enable low-power stop mode. 0 low-power stop mode disabled 1 low-power stop mode enabled. once the co re is stopped and the signal to enter stop mode is asserted, processor clocks can be disabled. 6?4 xlpm_ipl exit low-power mode interrupt priority leve l. this field defines the interrupt priority level needed to exit the low-power mode.refer to ta b l e 7 - 3 . 3?0 ? reserved, should be cleared. table 7-3. xlpm_ipl settings xlpm_ipl[2:0] interrupts level n eeded to exit low-power mode 000 any interrupt request exits low-power mode 001 interrupt request levels [2-7] exit low-power mode 010 interrupt request levels [3-7] exit low-power mode 011 interrupt request levels [4-7] exit low-power mode 100 interrupt request levels [5-7] exit low-power mode 101 interrupt request levels [6-7] exit low-power mode 11x interrupt request level [7] exits low-power mode mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 power management 7-4 freescale semiconductor 7.2.3.2 low-power control register (lpcr) the lpcr controls chip operation and module operation during low-power modes. 7 6543210 field lpmd ? stpmd ? lvdse ? reset 0000_0010 r/w r/w address ipsbar + 0x0011_0007 figure 7-2. low-power control register (lpcr) table 7-4. lpcr field descriptions bits name description 7?6 lpmd low-power mode select. used to select the low-power mode the chip enters once the coldfire cpu executes the stop instruction. these bits must be written prior to instruction ex ecution for them to take effect. the lpmd[1:0] bits are readable and writable in all modes. ta b l e 7 - 5 illustrates the four different power modes that can be configured with the lpmd bit field. 5 ? reserved, should be cleared. 4?3 stpmd pll/clkout stop mode. controls pll and clkout operation in stop mode as shown in ta b l e 7 - 6 2 ? reserved, should be cleared. 1 lvdse ldv standby enable. controls w hether the pmm enters vreg standby mode (lvd disabled) or vreg pseudo-standby (lvd enabled) mode when the pmm receives a power down request. this bit has no effect if the rcr[lvde] bit is a logic 0. 1 vreg pseudo-standby mode (lvd enabled on power down request). 0 vreg standby mode (lvd disabled on power down request). 0 ? reserved, should be cleared. table 7-5. low-power modes lpmd[1:0] mode 11 stop 10 wait 01 doze 00 run mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 power management freescale semiconductor 7-5 note if lpcr[lpmd] is cleared, then the device stops executing code upon issue of a stop instruction. howeve r, no clocks are disabled. 7.3 functional description the functions and characteristics of the low-power m odes, and how each module is affected by, or affects, these modes are discussed in this section. 7.3.1 low-power modes the system enters a low-power m ode by executing a stop instructi on. which mode the device actually enters (either stop, wait, or doze) depends on what is program med in lpcr[lpmd]. entry into any of these modes idles the cpu with no cycles active, pow ers down the system and st ops all internal clocks appropriately. during stop mode, the system clock is stopped low. for entry into stop mode, the lpicr[enbstop] bit must be set before a stop instruction is issued. a wakeup event is required to exit a low-power mode and return to run mode. wakeup events consist of any of these conditions: ? any type of reset ? any valid, enabled interrupt request the latter method of exiting from low-power mode , by a valid and enabled interrupt request, requires several things: ? an interrupt request whose priori ty is higher than the value programmed in the xlpm_ipl field of the lpicr ? an interrupt request whose priori ty higher than the value programmed in the interrupt priority mask (i) field of the core?s status register ? an interrupt request from a source which is not masked in the inte rrupt controller?s interrupt mask register ? an interrupt request which has been enable d at the module of the interrupt?s origin 7.3.1.1 run mode run mode is the normal system oper ating mode. current consumption in this mode is related directly to the system clock frequency. table 7-6. pll/clkout stop mode operation stpmd[1:0] operation during stop mode system clocks clkout pll osc pmm 00 disabled enabled enabled enabled enabled 01 disabled disabled enabled enabled enabled 10 disabled disabled disabled enabled enabled 11 disabled disabled disabled disabled low-power option mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 power management 7-6 freescale semiconductor 7.3.1.2 wait mode wait mode is intended to be used to stop only the cpu and memory clocks until a wakeup event is detected. in this mode, peripherals may be programmed to continue ope rating and can gene rate interrupts, which cause the cpu to exit from wait mode. 7.3.1.3 doze mode doze mode affects the cpu in the same manner as wait mode, except that each peripheral defines individual operational characteristic s in doze mode. peripherals which continue to run and have the capability of producing interrupts may cause the cpu to exit the do ze mode and return to run mode. peripherals which are stopped will restart operation on exit fr om doze mode as define d for each peripheral. 7.3.1.4 stop mode stop mode affects the cpu in the same manner as the wa it and doze modes, except that all clocks to the system are stopped and the peripherals cease operation. stop mode must be entered in a controlled manner to ensure that any curr ent operation is properly terminated. when exiting stop mode, most peripherals retain their pre-stop st atus and resume operation. the following subsections specify the operation of each module while in and when exiting low-power modes. note entering stop mode will disable the sdramc including th e refresh counter. if sdram is used, then code is require d to insure proper entry and exit from stop mode. see section 7.3.2.5, ?sdram controller (sdramc) ? for more information. 7.3.1.5 peripheral shut down most peripherals may be disabled by software in order to cease internal clock generation and remain in a static state. each peripheral has it s own specific disabling sequence (ref er to each peripheral description for further details). a peripheral may be disabled at any time and will re main disabled during any low-power mode of operation. 7.3.2 peripheral behavior in low-power modes 7.3.2.1 coldfire core the coldfire core is disabled during any low-power m ode. no recovery time is required when exiting any low-power mode. 7.3.2.2 static random-access memory (sram) sram is disabled during an y low-power mode. no rec overy time is required when exiting any low-power mode. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 power management freescale semiconductor 7-7 7.3.2.3 flash the flash module is in a low-power state if not being accessed. no rec overy time is required after exit from any low-power mode. the mcf5280 does not have a flash module. 7.3.2.4 system control module (scm) the scm?s core watchdog timer can br ing the device out of all low- power modes except stop mode. in stop mode, all clocks stop, and th e core watchdog does not operate. when enabled, the core watchdog can bring the device out of low-power mode in one of two ways. if the core watchdog reset/interrupt select (csri) bit is set, then a co re watchdog timeout will cause a reset of the device. if the csri bit is cleared, then a co re watchdog interrupt may be enabled and upon watchdog timeout, can bring the device out of low-power mode. this system setup must meet the conditions specified in section 7.3.1, ?low-power modes ? for the core watchdog interr upt to bring the part out of low-power mode. 7.3.2.5 sdram controller (sdramc) sdramc operation is unaffected by e ither the wait or doze modes; however, the sdramc is disabled by stop mode. since all clocks to the sdramc are disabled by stop m ode, the sdramc wi ll not generate refresh cycles. to prevent loss of data the sdram should be placed in self-refresh mode by setting dcr[is] before entering stop mode. the sdram self-r efresh mode allows the sdram to enter a low-power state where internal refresh operations are used to maintain the integrity of the data stored in the sdram. when stop mode is exited clearing the dcr[is] bit wi ll cause the sdram to exit the self-refresh mode and allow bus cycles to the sdram to resume. note the sdram is inaccessible while in th e self-refresh mode. therefore, if stop mode is used the vector table and any interrupt handlers that could wake the processor should not be stored in or attempt to access sdram. 7.3.2.6 chip select module in wait and doze modes, the chip select module c ontinues operation but does not generate interrupts; therefore it cannot bring a device out of a low- power mode. this module is stopped in stop mode. 7.3.2.7 dma controller (dmac0?dma3) in wait and doze modes, the dma co ntroller is capable of bringing the device out of a low-power mode by generating an interrupt either upon completion of a transfer or upon an error condition. the completion of transfer interrupt is generate d when dma interrupts are enabled by the setting of the dcr[int] bit, and an interrupt is generated when the dsr[done] bit is set. the interrupt upon error condition is generated when the dcr[int] bit is set, and an interrupt is generate d when either the ce, bes or bed bit in the dsr becomes set. the dma controller is stopped in st op mode and thus cannot cause an exit from this low-power mode. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 power management 7-8 freescale semiconductor 7.3.2.8 uart modules (uart0, uart1, and uart2) in wait and doze modes, the uart may generate an interrupt to exit the low-power modes. ? clearing the transmit enable bit (te) or the r eceiver enable bit (re) disables uart functions. ? the uarts are unaffected by wa it mode and may generate an interrupt to exit this mode. in stop mode, the uarts stop immedi ately and freeze their operation, regi ster values, state machines, and external pins. during this mode, the uart clocks are shut down. co ming out of stop mode returns the uarts to operation from the state pr ior to the low-power mode entry. 7.3.2.9 i 2 c module when the i 2 c module is enabled by the setting of the i2cr [ien] bit and when the device is not in stop mode, the i 2 c module is operable and may generate an interrupt to bring th e device out of a low-power mode. for an interrupt to occur, the i2cr[iie] bit must be set to enable interrupt s, and the setting of the i2sr[iif] generates the interrupt signal to the cpu and interrupt controller. the setting of i2sr[iif] signifies either the completion of one byte transfer or the reception of a calli ng address matching its own specified address when in slave receive mode. in stop mode, the i 2 c module stops immediat ely and freezes operation, register values, and external pins. upon exiting stop mode, the i 2 c resumes operation unless stop mode was exited by reset. 7.3.2.10 queued serial peripheral interface (qspi) in wait and doze modes, the queued se rial peripheral interface (qspi) may generate an interrupt to exit the low-power modes. ? clearing the qspi enable bit ( spe) disables the qspi function. ? the qspi is unaffected by wait mode and ma y generate an interrupt to exit this mode. in stop mode, the qspi stops immediately and free zes operation, register valu es, state machines, and external pins. during this mode, the qspi clocks ar e shut down. coming out of st op mode returns the qspi to operation from the state prio r to the low-power mode entry. 7.3.2.11 dma timers (dmat0?dmat3) in wait and doze modes, the dma timers may generate an interrupt to exit a low-power mode. this interrupt can be generated when th e dma timer is in either input cap ture mode or reference compare mode. in input capture mode, wher e the capture enable (ce) field of the timer mode register (dtmr) has a non-zero value and the dma enable (dmaen) bit of the dma timer ex tended mode register (dtxmr) is cleared, an interrupt is issued upon a capture d input. in reference comp are mode, where the output reference request interrupt enable (orri) bit of dtmr is set and the dtxmr[dmaen] bit is cleared, an interrupt is issued when the time r counter reaches the reference value. dma timer operation is disabled in stop mode, but the dma timer is unaff ected by either th e wait or doze modes and may generate an interrupt to exit these modes. upon exi ting stop mode, the timer will resume operation unless stop mode was exited by reset. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 power management freescale semiconductor 7-9 7.3.2.12 interrupt controllers (intc0, intc1) the interrupt controller is not affe cted by any of the low-power modes. all logic between the input sources and generating the interrupt to the processor will be co mbinational to allow the ab ility to wake up the cpu processor during low-power stop mode when all system clocks are stopped. an interrupt request will ca use the cpu to exit a low-power mode onl y if that interrupt?s priority level is at or above the level programmed in the interrupt priori ty mask field of the cpu?s status register (sr). the interrupt must also be enabled in th e interrupt controller?s interrupt mask register as well as at the module from which the interrupt request would originate. 7.3.2.13 fast ethernet controller (fec) in wait and doze modes, the fec may generate an interrupt to exit the low-power modes. ? clearing the ecntrl[ether_en] bit disables the fec function. ? the fec is unaffected by wait mode and may generate an interrupt to exit this mode. in stop mode, the fec stops immediately and freeze s operation, register values, state machines, and external pins. during this mode, the fec clocks are shut down. coming out of stop mode returns the fec to operation from the state prio r to the low-power mode entry. the mcf5214 and mcf5216 do not contain an fec. 7.3.2.14 i/o ports the i/o ports are unaffected by entr y into a low-power mode. these pi ns may impact low-power current draw if they are configured as out puts and are sourcing current to an external load. if low-power mode is exited by a reset, the state of th e i/o pins will revert to th eir default direction settings. 7.3.2.15 reset controller a power-on reset (por) will alwa ys cause a chip reset and ex it from any low-power mode. in wait and doze modes, as serting the external rsti pin for at least four clocks will cause an external reset that will reset the chip a nd exit any low-power modes. in stop mode, the rsti pin synchronization is disabled and asserting the external rsti pin will asynchronously generate an internal reset and exit any low-power modes. registers will lose current values and must be reconfigured from reset state if needed. if the phase lock loop (pll) in th e clock module is active and if th e appropriate (lo cre, lolre) bits in the synthesizer control re gister are set, then any lo ss-of-clock or loss-of-lock will reset the chip and exit any low-power modes. if the watchdog timer is st ill enabled during wait or doze modes, then a wa tchdog timer timeout may generate a reset to exit these low-power modes. when the cpu is inactive, a software reset ca nnot be generated to exit any low-power mode. 7.3.2.16 chip configuration module the chip configuration module is unaffected by entr y into a low-power mode . if low-power mode is exited by a reset, chip conf iguration may be executed if configured to do so. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 power management 7-10 freescale semiconductor 7.3.2.17 clock module in wait and doze modes, the clocks to the cpu, flash, and sram will be stopped and the system clocks to the peripherals are enabled. each module may disa ble the module cloc ks locally at the module level. in stop mode, all clocks to th e system will be stopped. during stop mode, there are several options for enabling/disabling th e pll and/or crysta l oscillator (osc); each of these options requires a compromise betw een wakeup recovery time and stop mode power. the pll may be disabled during stop mode. a wakeup time of up to 200 s is required for th e pll to re-lock. the osc may also be disabled during stop mode. the time required for the osc to restart is dependent upon the startup time of the crystal used. power consum ption can be reduced in stop mode by disabling either or both of these functi ons via the syncr[stmpd] bits. the external clkout signal may be enabled during low-power stop (if the p ll is still enabled) to support systems using this si gnal as the clock source. the system clocks may be enable d during wakeup from stop mode with out waiting for the pll to lock. this eliminates the wakeup recovery time, but at the risk of sending a potentially unstable clock to the system. it is recommended, if this option is used, that the pll frequency divider is set so that the targeted system frequency is no more than half the maximu m allowed. this will allo w for any frequency overshoot of the pll while still keeping the system cloc k within specification. in external clock mode, there are no wait times for the osc startup or pll lock. during wakeup from stop mode, the flash clock will alwa ys clock through 16 cycl es before the system clocks are enabled. this allows the flash module time to recover from th e low-power mode. thus, software may immediately continue to fetch instructions from the flash memory. the external clkout output pin ma y be disabled in the low state to lower power consumption via the disclk bit in the syncr. the ex ternal clkout pin function is en abled by default at reset. 7.3.2.18 edge port in wait and doze modes, th e edge port continues to operate normall y and may be configured to generate interrupts (either an edge transition or low level on an external pin) to exit the low-power modes. in stop mode, there is no system cl ock available to perform the edge detect function. thus, only the level detect logic is active (if configur ed) to allow any low level on the exte rnal interrupt pin to generate an interrupt (if enabled) to exit the stop mode. 7.3.2.19 watchdog timer in stop mode (or in wait/doze mode , if so programmed), the watchdog ce ases operation and freezes at the current value. when exiting these modes, the watchdog resumes ope ration from the stopped value. it is the responsibility of software to avoid erroneous operation. when not stopped, the watchdog may generate a reset to exit the low-power modes. 7.3.2.20 programmable interrupt time rs (pit0, pit1, pit2 and pit3) in stop mode (or in doze mode, if so programmed), the programma ble interrupt timer (pit) ceases operation, and freezes at the current value. when ex iting these modes, the pit resumes operation from the stopped value. it is the responsibility of software to avoid erroneous operation. when not stopped, the pit may generate an interrupt to exit the low-power modes. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 power management freescale semiconductor 7-11 7.3.2.21 queued analog-to-digital converter (qadc) setting the queued analog-to-digital converter (qadc) stop bit (qstop) will disable the qadc. the qadc is unaffected by either wa it or doze mode and may generate an interrupt to exit these modes. low-power stop mode (or setting the qstop bit), immediately freezes operation, register values, state machines, and external pins. this stops the clock signals to the digi tal electronics of the module and eliminates the quiescent current draw of the analog electronics. any conversion sequences in progress are stopped. exit from lo w-power stop mode (or clearing the qstop bit), returns the q adc to operation from the state prior to stop mode entry, but any convers ions in progress are undefi ned and the qadc requires recovery time to stabilize th e analog circuits before new conversions can be performed. 7.3.2.22 general purpose timers (gpta and gptb) when not stopped, the general purpose timers may gene rate an interrupt to ex it the low-power modes. clearing the timer enable bit (te) in the gpt system control register 1 (gptscr1) or the pulse accumulator enable bit (pae) in the gpt pulse accumulator control register (g ptpactl) disables timer functions. timer and pulse accumula tor registers are still accessibl e by the cpu and bdm interface, but the remaining functions of the timer are disabled. the timer is unaffected by either the wait or doze mode s and may generate an interrupt to exit these modes. in stop mode, the general purpose ti mers stop immediately a nd freeze their operation, register values, state machines, and external pins. upon exiting st op mode, the timer will re sume operation unless stop mode was exited by reset. 7.3.2.23 flexcan when enabled, the flexcan module is capable of generating interrupts and bringing the device out of a low-power mode. the module has 35 interrupt sources (32 sources due to message buffers and 3 sources due to bus-off, error and wake-up). when in stop mode, a recessive to dominant transi tion on the can bus causes the wake-int bit in the error & status register to be set. this event can cause a cpu interr upt if the wake-mask bit in module configuration register (mcr) is set. when setting stop mode in the flexcan (by setting the mcr[stop] bit), the flexcan checks for the can bus to be either idle or waits for the third bit of inte rmission and checks to see if it is recessive. when this condition exists, the flexcan waits for all inte rnal activity other than in the can bus interface to complete and then the following occurs: ? the flexcan shuts down its clocks, stopping most of the internal circui ts, to achieve maximum possible power saving. ? the internal bus interface logic continues ope ration, enabling cpu to ac cess the mcr register. ? the flexcan ignores its rx input pin, and drives its tx pins as recessive. ? flexcan loses synchronization with the can bus, and stop_ack and not_rdy bits in mcr register are set. exiting stop mode is done in one of the following ways: ? reset the flexcan (either by hard reset or by asserting the soft_rst bit in mcr). ? clearing the stop bit in the mcr. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 power management 7-12 freescale semiconductor ? self-wake mechanism. if the self-wake bit in the mcr is set at the time the flexcan enters stop mode, then upon detection of recessive to dominant transi tion on the can bus, the flexcan resets the stop bit in the mcr and resume s its clocks. recommendations for, and features of, fl excan?s stop mode opera tion are as follows: ? upon stop/self-wake mode entry, the flexcan tries to receive the frame that caused it to wake; that is, it assumes that the dominant bit detected is a start-of-frame bit. it does not arbitrate for the can bus then. ? before asserting stop mode, the cp u should disable all interrupts in the flexcan, otherwise it may be interrupted while in stop mode upon a non-wake-up condition. if desired, the wake-mask bit should be set to enable the wake-int. ? if stop mode is asserted while the flexcan is busoff (see error and status register), then the flexcan enters stop mode and stops counting th e synchronization sequence; it continues this count once stop mode is exited. ? the correct flow to ente r stop mode with self-wake: ? assert self-wake at the same time as stop. ? wait for stop_ack bit to be set. ? the correct flow to negate stop with self-wake: ? negate self-wake at the same time as stop. ? wait for stop_ack negation. ? self-wake should be set only when the mcr[stop ] bit is negated and th e flexcan is ready; that is, the not_rdy bit in the mcr is negated. ? if stop and self_wake are set and if a recessive to dominant edge immediately follows on the can bus, the stop_ack bit in the mcr may never be set, and the stop bit in the mcr is reset. ? if the user does not want to have old frames sent when the flexcan is awakened (stop with self-wake), the user should disable all tx sour ces, including remote-response, before stop mode entry. ? if halt mode is active at the time the stop bit is set, then the flexcan assumes that halt mode should be exited; hence it tries to synchronize to the can bus (11 consecut ive recessive bits), and only then does it search for the correct conditions to stop. ? trying to stop the flexcan immediately after rese t is allowed only after basic initialization has been performed. if stop with self-wake is activated, and the flexc an operates with single syst em clock per time-quanta, then there are extreme cases in which flexcan's wake-up upon re cessive to dominant edge may not conform to the standard can protoc ol, in the sense that the flexcan synchronization is shifted one time quanta from the required timing. this shift lasts until the next re cessive to dominant edge, which re-synchronizes the flexcan back to conform to the protocol. the same holds for auto-power save mode upon wake-up by recessive to dominant edge. the auto-power save mode in the flexcan is in tended to enable normal operation with optimized power saving. upon se tting the auto power save bi t in the mcr register, the flexcan looks for a set of conditions in which there is no need for clocks to run. if all these cond itions are met, then the flexcan stops its cloc ks, thus saving power. while its clocks are stopped, if any of the conditions below is not met, the flexcan resumes it s clocks. it then continues to m onitor the conditions and stops/resumes its clocks appropriately. the following are conditions for the automatic shut-off of flexcan clocks: ? no rx/tx frame in progress. ? no moving of rx/tx frames betw een smb and mb and no tx fram e is pending for transmission in any mb. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 power management freescale semiconductor 7-13 ? no host access to the flexcan module. ? the flexcan is neither in halt mode (mcr bi t 8), in stop mode (mct bit 15), nor in busoff. 7.3.2.24 coldfire flash module the coldfire flash control module is capable of generating interrupt s by the setting of the cbeif or ccif bits in the cfmustat. these in terrupt sources, however, should not occur when the device is in a low-power mode as long as no flash operation was in progress when the low-power mode was entered. when performing a program or erase operation on the fl ash, if a command is activ e (ccif = 0) when the mcu enters a low-power mode, the command sequence monitor will perform the following: 1. the command in progress will be aborted. 2. the flash high voltage circuitry will be switched off and any pe nding command (cbe if = 0) will not be executed when the mcu exits low-power mode. 3. the ccif and accerr flags will be set if a command is active when the mcu enters low-power mode. note the state of any longword(s) being programmed, or any erase pages/physical blocks being erased, is not guaranteed if the mcu enters stop mode with a command in progress. active co mmands are immediately aborted when the mcu enters st op mode. do not execute the stop instruction during program and erase operations. 7.3.2.25 bdm entering halt mode via the bdm port (by assert ing the external bkpt pin) will cause th e cpu to exit any low-power mode. 7.3.2.26 jtag the jtag (joint test action group) controller logic is clocked using the tclk input and is not affected by the system clock. the jtag cannot generate an event to cause the cpu to exit any low-power mode. toggling tclk during any low-pow er mode will increase the system current consumption. 7.3.3 summary of peripheral state during low-power modes the functionality of each of the peripherals and cpu during the various low-power modes is summarized in table 7-7 . the status of each periphera l during a given mode refers to the condition the peripheral automatically assumes when the stop instruction is executed and the lpcr[lpmd ] field is set for the particular low-power mode. individua l peripherals may be disabled by programming its de dicated control bits. the wakeup capability field refers to the ability of an interrupt or reset by that periphe ral to force the cpu into run mode. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 power management 7-14 freescale semiconductor table 7-7. cpu and peripherals in low-power modes module peripheral status 1 / wakeup capability 1 ?program? indicates that the peripheral function during th e low-power mode is dependent on programmable bits in the peripheral register map. wait mode doze mode stop mode cpu stopped no stopped no stopped no sram stopped no stopped no stopped no flash stopped no stopped no stopped no flash control module enabled yes 2 enabled yes 2 stopped no system integration module enabled yes 3 enabled yes 3 stopped no sdram controller enabled no enabled no stopped no chip select module enabled no enabled no stopped no dma controller enabled yes enabled yes stopped no uart0, uart1 and uart2 enabled yes 2 enabled yes 2 stopped no i 2 c module enabled yes 2 enabled yes 2 stopped no qspi enabled yes 2 enabled yes 2 stopped no dma timers enabled yes 2 enabled yes 2 stopped no interrupt controller enabled yes 2 2 these modules can generate a interrupt which will exit a lo w-power mode. the cpu will begin to service the interrupt exception after wakeup. enabled yes 2 enabled yes 2 fast ethernet controller enabled yes 2 enabled yes 2 stopped no i/o ports enabled no enabled no enabled no reset controller enabled yes 3 3 these modules can generate a reset which will exit any low-power mode. enabled yes 3 enabled yes 3 chip configuration module enabled no enabled no stopped no power management enabled no enabled no stopped no clock module enabled yes 2 enabled yes 2 program yes 2 edge port enabled yes 2 enabled yes 2 stopped yes 2 watchdog timer program yes 3 program yes 3 stopped no programmable interrupt timers enabled yes 2 program yes 2 stopped no qadc enabled yes 2 program yes 2 stopped no general purpose timers enabled yes 2 enabled yes 2 stopped no flexcan enabled yes 2 enabled yes 2 stopped no bdm enabled yes 4 enabled yes 4 enabled yes 4 jtag enabled no enabled no enabled no mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 power management freescale semiconductor 7-15 4 the bdm logic is clocked by a separate tclk clock. enteri ng halt mode via the bdm port exits any low-power mode. upon exit from halt mode, the previous low-power mode will be re-entered and changes made in halt mode will remain in effect. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 power management 7-16 freescale semiconductor mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor 8-1 chapter 8 system control module (scm) this section details the functi onality of the system control module (scm) which provides the programming model for the system access control unit (sacu), the system bus arbiter, a 32-bit core watchdog timer (cwt), and the system control regist ers and logic. specifical ly, the system control includes the internal peri pheral system (ips) base address register (ipsbar), the processor?s dual-port ram base address register (rambar) , and system control re gisters that include the core watchdog timer control. 8.1 overview the scm provides the control and status for a variet y of functions including base addressing and address space masking for both the i ps peripherals and resources (ipsbar) and the coldfire core memory spaces (rambar). the cpu core supports two memory banks, one for the internal sram and the other for the internal flash. the sacu provides the mechanism needed to implemen t secure bus transactions to the system address space. the programming model for the syst em bus arbitration resides in the scm. the scm sources the necessary control signals to the ar biter for bus mast er management. the cwt provides a means of preventing system loc kup due to uncontrolled softwa re loops via a special software service sequence. if periodic software serv icing action does not occur, the cwt times out with a programmed response (interrupt) to allow recovery or co rrective action to be taken. 8.2 features the scm includes these distinctive features: ? ips base address register (ipsbar) ? base address location for 1-gbyte peripheral space ? user control bits ? processor-local memory base address register (rambar) ? system control registers ? core reset status register (crsr) indicates type of last reset ? core watchdog control register (c wcr) for watchdog timer control ? core watchdog service register (c wsr) to service watchdog timer ? system bus master arbitrat ion programming model (mpark) ? system access control unit (sacu) programming model ? master privilege register (mpr) ? peripheral access control registers (pacrs) ? grouped peripheral access contro l registers (gpacr0, gpacr1) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 system control module (scm) 8-2 freescale semiconductor 8.3 memory map and register definition the memory map for the sc m registers is shown in table 8-1 . all the registers in the scm are memory-mapped as offsets within the 1 gbyte ips address space and accesses are cont rolled to these registers by the control definitions programmed into the sacu. 8.4 register descriptions 8.4.1 internal peripheral system base address register (ipsbar) the ipsbar specifies the base a ddress for the 1 gbyte memory space associat ed with the on-chip peripherals. at reset, the base address is load ed with a default location of 0x4000_0000 and marked as valid (ipsbar[v]=1). if desired, the address space asso ciated with the internal modules can be moved by loading a different value into the ipsbar at a later time. note accessing reserved ipsbar memory sp ace could result in an unterminated bus cycle that causes the core to hang. only a hard reset will allow the core to recover from this state. therefor e, all bus accesses to ipsbar space should fall within a module?s memory map space. if an address ?hits? in overlapping memory regions, the following priority is used to determine what memory is accessed: 1. ipsbar 2. rambar 3. cache 4. sdram table 8-1. scm register map ipsbar offset [31:24] [23:16] [15:8] [7:0] 0x00_0000 ipsbar 0x00_0004 ? 0x00_0008 rambar 0x00_000c ? 0x00_0010 crsr cwcr lpicr 1 1 the lpicr is described in chapter 7, ?power management ." cwsr 0x00_0018 ? 0x00_001c mpark 0x00_0020 mpr ? 0x00_0024 pacr0 pacr1 pacr2 pacr3 0x00_0028 pacr4 ? pacr5 pacr6 0x00_002c pacr7 ? pacr8 ? 0x00_0030 gpacr0 gpacr1 ? ? 0x00_0034 ? ? ? ? 0x00_0038 ? ? ? ? 0x00_003c ? ? ? ? mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 system control module (scm) freescale semiconductor 8-3 5. chip selects note this is the list of memory access priori ties when viewed from the processor core. see figure 8-1 and table 8-2 for descriptions of the bits in ipsbar. 8.4.2 memory base address register (rambar) the processor supports dual -ported local sram memory. this pro cessor-local memory can be accessed directly by the core and/or other system bus masters. since this me mory provides singl e-cycle accesses at processor speed, it is ideal for applications where double-buffer schemes can be used to maximize system-level performance. for example, a dma channel in a t ypical double-buffer (also known as a ping-pong scheme) application may lo ad data into one portion of the dual-ported sram while the processor is manipulating data in another portion of the sram. once the processor completes the data calculations, it begins pr ocessing the just-loaded buffer while th e dma moves out the just-calculated data from the other buffer, and reloads the next data block into the just -freed memory region. the process repeats with the processor and th e dma ?ping-ponging? between alternate regions of the dual-ported sram. the processor design implements the dual-ported sram in the me mory space defi ned by the rambar register. there are two physical copies of the rambar register: one located in the processor core and accessible only via the privileged movec instruction at cpu space address 0xc 05, and another located in the scm at ipsbar + 0x008. coldfire core a ccesses to this memory are controlled by the processor-local copy of the rambar, while m odule accesses are enabled by the scm's rambar. 31 30 29 16 field ba31 ba30 ? reset 0 1 ? r/w r/w 15 10 field ? v reset ? 1 r/w r/w address ipsbar + 0x000 figure 8-1. ips base address register (ipsbar) table 8-2. ipsbar field description bits name description 31?30 ba base address. defines the base address of the 1-gbyte internal peripheral space. this is the starting address for the ips registers when the valid bit is set. 29?1 ? reserved, should be cleared. 0 v valid. enables/disables the ips base address region. v is set at reset. 0 ips base address is not valid. 1 ips base address is valid. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 system control module (scm) 8-4 freescale semiconductor the physical base address programmed in both copi es of the rambar is t ypically the same value; however, they can be programmed to different valu es. by definition, the ba se address must be a 0-modulo-size value. the sram modules are configured through the rambar shown in figure 8-2 . ? rambar specifies the base address of the sram. ? all undefined bits are reserve d. these bits are ignored during wr ites to the rambar and return zeros when read. ? the back door enable bit, rambar [bde], is cleared at reset, di sabling the module access to the sram. note the rambar default value of 0x0000_0000 is invalid. the rambar located in the processor?s cpu space mu st be initialized with the valid bit set before the cpu (or modules) can access the on-chip sram (see chapter 5, ?static ram (sram) ? for more information. for details on the processor's view of the local sram memories, see section 5.3.1, ?sram base address register (rambar) .? 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 field ba31 ba30 ba29 ba28 ba27 ba26 ba25 ba2 4 ba23 ba22 ba21 ba20 ba19 ba18 ba17 ba16 reset 0000_0000_0000_0000 r/w r/w 15 10 9 8 0 field ? bde ? reset 0000_0000_0000_0000 r/w r/w address ipsbar + 0x008 figure 8-2. memory base address register (rambar) table 8-3. rambar field description bits name description 31?16 ba base address. defines the memory module's base address on a 64-kbyte boundary corresponding to the physical array location within the 4 gbyte address space supported by coldfire. 15?10 ? reserved, should be cleared. 9 bde back door enable. qualifies the module accesses to the memory. 0 disables module acce sses to the memory. 1 enables module accesses to the memory. note: the spv bit in the cpu?s rambar must also be set to allow dual port access to the sram. for more information, see section 5.3.1, ?sram base address register (rambar) .? 8?0 ? reserved, should be cleared. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 system control module (scm) freescale semiconductor 8-5 8.4.3 core reset stat us register (crsr) the crsr contains a bit for two of the reset sources to the cpu. a bit set to 1 indicate s the last type of reset that occurred. the crsr is upda ted by the control logic when the reset is complete. only one bit is set at any one time in the crsr. the register reflects the cause of the most recent reset. to clear a bit, a logic 1 must be written to the bit location; writing a zero has no effect. note the reset status register (rsr) in the reset controller module (see chapter 29, ?reset controller module ?) provides indication of all reset sources except the co re watchdog timer. 8.4.4 core watchdog control register (cwcr) the core watchdog timer prevents system lockup if the software becomes trapped in a loop with no controlled exit. the core watchdog timer can be enabled or disabled through cwcr [cwe]. by default it is disabled. if enabled, the watchdog timer requires the periodic execution of a core watchdog servicing sequence. if this periodic servicing action does not occu r, the timer times out, resulting in a watchdog timer interrupt. if the timer ti mes out and the core watchdog transfer acknowledge enable bit (cwcr[cwta]) is set, a watchdog timer interrupt is asserted. if a core watchdog timer interrupt acknowledge cycle has not occurred after another time out, cwt ta is asserted in an attempt to allow the interrupt acknowledge cycle to proceed by terminating the bus cycle. the sett ing of cwcr[cwtaval] indicates that the watchdog timer ta was asserted. note the core watchdog timer is available to provide compatibility with the watchdog timer implemented on previous coldfire devices. however, there is a second watchdog timer availabl e that has new features. see chapter 18, ?watchdog timer module ? for more information. 7654 0 field ext ? reset see note r/w r/w address ipsbar + 0x010 note: the reset value of ext and cwdr depend on the last reset source. all other bits are initialized to zero. figure 8-3. core reset status register (crsr) table 8-4. crsr field descriptions bits name description 7 ext external reset. 1 an external device driving rsti caused the last reset. assertion of reset by an external device causes the processor core to init iate reset exception processing. all registers are forced to their initial state. 6-0 ? reserved. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 system control module (scm) 8-6 freescale semiconductor when the core watchdog timer tim es out and cwcr[cwri] is programmed for a software reset, an internal reset is asserted and cr sr[cwdr] is set. to prevent the core watchdog timer from interrupting or resetting, the cwsr must be serviced by performing the following sequence: 1. write 0x55 to cwsr. 2. write 0xaa to the cwsr. both writes must occur in order before the time- out, but any number of instructions can be executed between the two writes. this order allows interrupts and exceptions to occur, if necessary, between the two writes. caution should be exercised when changing cwcr values after the so ftware watchdog timer has been enabled with the setting of cw cr[cwe], because it is difficult to determine the state of the core watchdog timer while it is running. the countdown value is constantly co mpared with the time-out period specified by cwcr[cwt]. the following steps must be taken to change cwt: 1. disable the core watchdog timer by clearing cwcr[cwe]. 2. reset the counter by writing 0x55 and then 0xaa to cwsr. 3. update cwcr[cwt]. 4. re-enable the core watchdog timer by setting cw cr[cwe]. this step can be performed in step 3. the cwcr controls the software wa tchdog timer, time-out periods, and software watchdog timer transfer acknowledge. the register can be read at any time, but can be wr itten only if the cwt is not pending. at system reset, the software watchdog timer is disabled. 765 32 1 0 field cwe cwri cwt[2:0] cwta cwtaval cwtic reset 0000_0000 r/w r/w address ipsbar + 0x011 figure 8-4. core watchdog control register (cwcr) table 8-5. cwcr field description bits name description 7 cwe core watchdog enable. 0 swt disabled. 1 swt enabled. 6 cwri core watchdog reset/interrupt select. 0 if a time-out occurs, the cwt generates an interrupt to the processor core. the interrupt level for the cwt is programmed in the interrupt control register 8 (icr8) of intc0. 1 reserved; do not use. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 system control module (scm) freescale semiconductor 8-7 8.4.5 core watchdog service register (cwsr) the software watchdog service sequence must be performed using the cwsr as a data register to prevent a cwt time-out. the service sequen ce requires two writes to this da ta register: firs t a write of 0x55 followed by a write of 0xaa. both wr ites must be performed in this order prior to the cwt time-out, but any number of instructions or acces ses to the cwsr can be executed between the two writes. if the cwt has already timed out, writing to this register has no effect in negating the cwt interrupt. figure 8-5 illustrates the cwsr. at system reset, the contents of cwsr are uninitialized. 8.5 internal bus arbitration the internal bus arbitration is perf ormed by the on-chip bus arbiter, wh ich containing the arbitration logic that controls which of up to four mbus masters (m0?m3 in figure 8-6 ) has access to the external buses. the function of the arbitration logi c is described in this section. 5?3 cwt[2:0] core watchdog timing delay. these bits select the timeout period for the cwt. at system reset, the cwt field is cleared signaling the minimum time-out period but the watchdog is disabled (cwcr[cwe] = 0). 2 cwta core watchdog transfer acknowledge enable. 0 cwta transfer acknowledge disabled. 1 cwta transfer acknowledge enabled. after one cwt time-out period of the unacknowledged assertion of the cwt interrupt, the transfer acknowledge asserts, which allows cwt to terminate a bus cycle and allow the interrupt acknowledge to occur. 1 cwtaval core watchdog transfer acknowledge valid. 0 cwta transfer acknowledge has not occurred. 1 cwta transfer acknowledge has occurred. write a 1 to clear this flag bit. 0 cwtif core watchdog timer interrupt flag. 0 cwt interrupt has not occurred 1 cwt interrupt has occurred. write a 1 to clear the interrupt request. 7 0 field cwsr[7:0] reset uninitialized r/w r/w address ipsbar + 0x013 figure 8-5. core watchdog service register (cwsr) table 8-5. cwcr field description (continued) cwt cwt time-out period cwt cwt time-out period 000 2 9 bus clock frequency 100 2 19 bus clock frequency 001 2 11 bus clock frequency 101 2 23 bus clock frequency 010 2 13 bus clock frequency 110 2 27 bus clock frequency 011 2 15 bus clock frequency 111 2 31 bus clock frequency mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 system control module (scm) 8-8 freescale semiconductor figure 8-6. arbiter module functions 8.5.1 overview the basic functionality is that of a 4-port, pipelined internal bus ar bitration module with the following attributes: ? the master pointed to by the current arbitration poi nter may get on the bus with zero latency if the address phase is available. all other requesters f ace at least a one cycle ar bitration pipeline delay in order to meet bus timing constraints on address phase hold. ? if a requester will get an immediat e address phase (that is, it is pointed to by the current arbitration pointer and the bus address phase is available), it will be the current bus master and is ignored by arbitration. all remaining requesting ports are eval uated by the arbitration algorithm to determine the next-state arbitration pointer. ? there are two arbitration algorithms, fixed and round-robin. fixed arbitrati on sets the next-state arbitration pointer to the highest priority requester. round-robin ar bitration sets the next-state arbitration pointer to the highest priority requester (calculated by a dding a requester's fixed priority to the current bus master?s fixed priority and then taking this sum modulo the number of possible bus masters). ? the default priority is fec (m 3) > dma (m2) > internal master (m1) > cpu (m0) , where m3 is the highest and m0 the lowest priority. m3 is not used for the mcf5216 and mcf5214. ? there are two actions for an idle arbitration cycle, either leave the current arbi tration pointer as is or set it to the lowest priority requester. ? the anti-lock-out logic for the fixed priority scheme forces the arbitrat ion algorithm to round-robin if any requester has been held for longer than a specified cycle count. sram1 mpark rambar cpu m0 dma m2 internal m1 bus master fec m3 eim internal marb modules sdramc ?back door? to sram and flash *not used on mcf5214/16 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 system control module (scm) freescale semiconductor 8-9 8.5.2 arbitration algorithms there are two modes of arbitration: fixed and round-robin. this section discusses the differences between them. 8.5.2.1 round-robin mode round-robin arbitration is the default mode after reset. this scheme cycles th rough the sequence of masters as specified by mpark[m n _prty] bits. upon completion of a transfer, the master is given the lowest priority and the priority for all other masters is increased by one. m3 = 11 m2 =01 m1 = 10 m0 = 00 next +1 m3 = 00 m2 =10 m1 = 11 m0 = 01 next +2 m3 = 01 m2 =11 m1 = 00 m0 = 10 next +3 m3 = 10 m2 =00 m1 = 01 m0 = 11 if no masters are requesting, the arbitr ation unit must ?park?, pointing at one of the masters. there are two possibilities, park the arbitration unit on the last active master, or pa rk pointing to the highest priority master. setting mpark[prk_last] ca uses the arbitration pointer to be parked on the highest priority master. in round-robin mode, progr amming the timeout enable and lo ckout bits mpark[13,11:8] will have no effect on the arbitration. 8.5.2.2 fixed mode in fixed arbitration the mast er with highest priority (as specified by the mpark[m n _prty] bits) will win the bus. that master will relinquish the bus when all transfers to that master are complete. if mpark[timeout] is set, a counter will increment for each master for every cy cle it is denied access. when a counter reaches the limi t set by mpark[lckout_time], the arbitration algorithm will be changed to round-robin arbitrat ion mode until all locks ar e cleared. the arbitration will then return to fixed mode and the highest priority ma ster will be granted the bus. as in round-robin mode, if no masters are requestin g, the arbitration pointer will park on the highest priority master if mpark[prk_last ] is set, or will park on the mast er which last requested the bus if cleared. 8.5.3 bus master park register (mpark) the mpark controls the operation of the system bus arbitration module. the platform bus master connections are defined as: ? master 3 (m3): fast ethernet controller (not used for the mcf5216 and mcf5214) ? master 2 (m2): 4-channel dma ? master 1 (m1): internal bus master (not used in normal user operation) ? master 0 (m0): v2 coldfire core mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 system control module (scm) 8-10 freescale semiconductor 31 26 25 24 23 22 21 20 19 18 17 16 field ? m2_p_en bcr24bit m3_prty m2_prty m0_prty m1_prty reset 0011_0000_1110_0001 r/w r/w 15 14 13 12 11 8 7 0 field ? fixed timeout prklast lckout_time ? reset 0000_0000_0000_0000 r/w r/w address ipsbar + 0x01c figure 8-7. default bus mast er park register (mpark) table 8-6. mpark field description bits name description 31?26 ? reserved, should be cleared. 25 m2_p_en dma bandwith control enable 0 disable the use of the dma's b andwidth control to elevate the priority of its bus requests. 1 enable the use of the dma's bandwidth control to elevate the priority of its bus requests. 24 bcr24bit enables the use of 24 bit by te count registers in the dma module 0 dma bcrs function as 16 bit counters. 1 dma bcrs function as 24 bit counters. 23?22 m3_prty master priority level for master 3 (fast ethernet controller) 00 fourth (lowest) priority 01 third priority 10 second priority 11 first (highest) priority note: reserved on the mcf5214 and mcf5216 21?20 m2_prty master priority level for master 2 (dma controller) 00 fourth (lowest) priority 01 third priority 10 second priority 11 first (highest) priority 19?18 m0_prty master priority level for master 0 (coldfire core) 00 fourth (lowest) priority 01 third priority 10 second priority 11 first (highest) priority 17?16 m1_prty master priority level for master 1 (not used in user mode) 00 fourth (lowest) priority 01 third priority 10 second priority 11 first (highest) priority 15 ? reserved, should be cleared. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 system control module (scm) freescale semiconductor 8-11 the initial state of the master pr iorities is m3 > m2 > m1 > m0. system soft ware should guarantee that the programmed m n _prty fields are unique, otherw ise the hardware defaults to the initial-state priorities. note the m1_prty field should not be se t for a priority higher than third (default). 8.6 system access control unit (sacu) this section details the functionality of the sy stem access control unit (s acu) which provides the mechanism needed to implement secure bus transact ions to the address space mapped to the internal modules. 8.6.1 overview the sacu supports the traditional m odel of two privilege levels: superv isor and user. typically, memory references with the supervisor attri bute have total accessibility to all th e resources in the system, while user mode references cannot access system control and conf iguration registers. in many systems, the operating system executes in supervisor mode, while application software executes in user mode. the sacu further partitions the acce ss control functions into two parts: one control register defines the privilege level associated with each bus master, and another se t of control registers define the access levels associated with the periphera l modules and the memory space. the sacu?s programming model is phys ically implemented as part of the system control module (scm) with the actual access control logic included as part of the arbitration controll er. each bus transaction targeted for the ips space is first checked to see if its privilege rights allow access to the given memory space. if the privilege rights are correct, the access proceeds on th e bus. if the privilege rights are insufficient for the targeted memory space, the tran sfer is immediately aborte d and terminated with an exception, and the targeted module not accessed. 14 fixed fixed or round robin arbitration 0 round robin arbitration 1 fixed arbitration 13 timeout timeout enable 0 disable count for when a master is locked out by other masters. 1 enable count for when a master is locked out by other masters and allow access when lckout_time is reached. 12 prklast park on the last active master or hi ghest priority master if no masters are active 0 park on last active master 1 park on highest priority master 11?8 lckout_time lock-out time. lock-out time for a master being denied the bus. the lock out time is defi ned as 2^ lckout_time[3:0]. 7?0 ? reserved, should be cleared. table 8-6. mpark field description (continued) bits name description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 system control module (scm) 8-12 freescale semiconductor 8.6.2 features each bus transfer can be classified by its privilege le vel and the reference type. the complete set of access types includes: ? supervisor instruction fetch ? supervisor operand read ? supervisor operand write ? user instruction fetch ? user operand read ? user operand write instruction fetch accesses are associ ated with the execute attribute. it should be noted that wh ile the bus does not implement the concep t of reference type (code versus data) and only supports the user/supervisor privilege level, the reference type attribute is supported by the system bus. accordingly, the access checking associated with both priv ilege level and reference type is performed in the ips controller usi ng the attributes associated with the reference from the system bus. the sacu partitions the access control m echanisms into three distinct functions: ? master privilege register (mpr) ? allows each bus master to be assigned a privilege level: ? disable the master?s user/supervisor a ttribute and force to user mode access ? enable the master?s user/supervisor attribute ? the reset state provides supervisor privileg e to the processor core (bus master 0). ? input signals allow the non-core bus masters to have their user/s upervisor attribute enabled at reset. this is intended to support the concept of a trusted bus master, and also controls the ability of a bus master to modify the register state of any of the sacu control registers; that is, only trusted masters can modi fy the control registers. ? peripheral access control registers (pacrs) ? nine 8-bit registers cont rol access to 17 of the on- chip peripheral modules. ? provides read/write access rights, supervisor/user privilege levels ? reset state provides supervisor-only read/write access to these modules ? grouped peripheral access contro l registers (gpacr0, gpacr1) ? one single register (gpacr0) controls access to 14 of the on-chip peripheral modules ? one register (gpacr1) controls access for ips reads and writes to the flash module ? provide read/write/execute access ri ghts, supervisor/user privilege levels ? reset state provides supervisor-only read/wri te access to each of these peripheral spaces 8.6.3 memory map/register definition the memory map for the sacu progr am-visible registers within th e system control module (scm) is shown in figure 8-7 . the mpr, pacr, and gpacrs are 8 bits in width. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 system control module (scm) freescale semiconductor 8-13 8.6.3.1 master privilege register (mpr) the mpr specifies the access privilege level associated with each bus ma ster in the platform. the register provides one bit per bus mast er, where bit 3 corresponds to master 3 (fast ethernet controller, not used on mcf5216 and mcf5214), bit 2 to master 2 (dma controller), bit 1 to mast er 1 (internal bu s master), and bit 0 to master 0 (coldfire core). only trusted bus masters can modify the access control registers. if a non-trusted bus master attempts to write any of the sacu control regist ers, the access is aborted with an error termination and the registers remain unaffected. the processor core is connect ed to bus master 0 and is always trea ted as a trusted bus master. accordingly, mpr[0] is forced to 1 at reset. 8.6.3.2 peripheral access control registers (pacr0?pacr8) access to several on-chip pe ripherals is controlled by shared peri pheral access control registers. a single pacr defines the access level for each of the two modules. th ese modules only support operand reads table 8-7. sacu register memory map ipsba r offset [31:28] [27:24] [23:20] [19:16] [15:12] [11:8] [7:4] [3:0] 0x020 mpr ?????? 0x024 pacr0 pacr1 pacr2 pacr3 0 x 0 2 8 pac r 4 ? pac r 5 pac r 6 0x02c pacr7 ? pacr8 ? 0x030 gpacr0 gpacr1 ? ? 0x034 ? ? ? ? 0x038 ? ? ? ? 0x03c ? ? ? ? 7 0 field ? mpr[3:0] reset 0000_0011 r/w r/w address ipsbar + 0x020 figure 8-8. master privilege register (mpr) table 8-8. mpr[n] field descriptions bits name description 7?4 ? reserved. should be cleared. 3?0 mpr each 1-bit field defines the access privilege level of the given bus master n . 0 all bus master accesses are in user mode. 1 all bus master accesses use the sourced user/supervisor attribute. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 system control module (scm) 8-14 freescale semiconductor and writes. each pacr follow s the format illustrated in figure 8-9 . for a list of pacrs and the modules that they control, refer to table 8-11 . 76 432 0 field lock1 access_ctrl1 lock0 access_ctrl0 reset 0000_0000 r/w r/w address ipsbar + 0x24 + offset figure 8-9. peripheral access control register (pacr n ) table 8-9. pacr field descriptions bits name description 7 lock1 this bit, when set, prevents subs equent writes to accessctrl1. any attempted write to the pacr generates an error termin ation and the contents of the register are not affected. only a system reset clears this flag. 6?4 access_ctrl1 this 3-bit field defines the acce ss control for the given platform peripheral. the encodings for this field are shown in ta b l e 8 - 1 0 . 3 lock0 this bit, when set, prevents subs equent writes to accessctrl0. any attempted write to the pacr generates an error termin ation and the contents of the register are not affected. only a system reset clears this flag. 2?0 access_ctrl0 this 3-bit field defines the acce ss control for the given platform peripheral. the encodings for this field are shown in ta b l e 8 - 1 0 . table 8-10. pacr accessctrl bit encodings bits supervisor mode user mode 000 read/write no access 001 read no access 010 read read 011 read no access 100 read/write read/write 101 read/write read 110 read/write read/write 111 no access no access table 8-11. peripheral access control registers (pacrs) ipsbar offset name modules controlled access_ctrl1 access_ctrl0 0x024 pacr0 scm sdramc 0x025 pacr1 eim dma 0x026 pacr2 uart0 uart1 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 system control module (scm) freescale semiconductor 8-15 at reset, these on-chip modules are configured to have only supervisor read/write access cap abilities. if an instruction fetch access to any of these peripheral modul es is attempted, the ips bus cycle is immediately terminated with an error. 8.6.3.3 grouped peripheral access control registers (gpacr0 & gpacr1) the on-chip peripheral space starting at ipsbar is subdivided into sixteen 64-mbyte regions. each of the first two regions has a unique access co ntrol register associated with it. the other fourteen regions are in reserved space; the access control registers for these regions are not implemente d. bits [29:26] of the address select the specific gpacrn to be used for a given reference within the ips address space. these access control registers are 8 bits in width so that read, write, and execute attributes ma y be assigned to the given ips region. note the access control for modules wi th memory space protected by pacr0?pacr8 are determined by th e pacr0?pacr8 settings. the access control is not affected by gpacr0, even though the modu les are mapped in its 64-mbyte address space. 0x027 pacr3 uart2 ? 0x028 pacr4 i 2 c qspi 0x029 ? ? ? 0x02a pacr5 dtim0 dtim1 0x02b pacr6 dtim2 dtim3 0x02c pacr7 intc0 intc1 0x02d ? ? ? 0x02e pacr8 fec0 ? 76 ? 43 0 field lock ? access_ctrl reset 0000_0000 read/write r/w r r/w address ipsbar + 0x030, ipsbar + 0x31 figure 8-10. grouped peripheral access control register (gpacr) table 8-11. peripheral access control registers (pacrs) (continued) ipsbar offset name modules controlled access_ctrl1 access_ctrl0 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 system control module (scm) 8-16 freescale semiconductor at reset, these on-chip modules are configured to have only supervisor read/write access capabilities. bit encodings for the access_ctrl fi eld in the gpac r are shown in table 8-13 . table 8-14 shows the memory space protected by the gpacrs a nd the modules mapped to these spaces. table 8-12. gpacr field descriptions bits name description 7 lock this bit, once set, prevents subsequent writ es to the gpacr. any attempted write to the gpacr generates an error termination and the contents of the regist er are not affected. only a system reset clears this flag. 6?4 ? reserved, should be cleared. 3?0 access_ctrl this 4-bit field defines the ac cess control for the given memory region. the encodings for this field are shown in ta b l e 8 - 1 3 . table 8-13. gpacr access_ctrl bit encodings bits supervisor mode user mode 0000 read / write no access 0001 read no access 0010 read read 0011 read no access 0100 read / write read / write 0101 read / write read 0110 read / write read / write 0111 no access no access 1000 read / write / execute no access 1001 read / execute no access 1010 read / execute read / execute 1011 execute no access 1100 read / write / execute read / write / execute 1101 read / write / execute read / execute 1110 read / write read 1111 read / write / execute execute mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 system control module (scm) freescale semiconductor 8-17 table 8-14. gpacr address space register space protected (ipsbar offset) modules protected gpacr0 0x0000_0000? 0x03ff_ffff ports, ccm, pmm, reset controller, clock, eport, wdog, pit0?pit3, qadc, gpta, gptb, flexcan, cfm (control) gpacr1 0x0400_0000? 0x07ff_ffff cfm (flash module?s backdoor access for programming or access by a bus master other than the core) note: reserved for the mcf5280 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 system control module (scm) 8-18 freescale semiconductor mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor 9-1 chapter 9 clock module the clock module configures the device for one of several cloc king methods. cloc king modes include internal phase-locked loop (pll) clocki ng with either an external clock reference or an external crystal reference supported by an internal crystal amplifier. the pll can also be disabled and an external oscillator can be used to clock the de vice directly. the clock module contains: ? crystal amplifier and oscillator (osc) ? phase-locked loop (pll) ? reduced frequency divider (rfd) ? status and control registers ? control logic 9.1 features features of the clock module include: ? 2- to 10-mhz reference crystal oscillator ? support for low-power modes ? separate clock out signal 9.2 modes of operation the clock module can be operated in normal pll mode (default), 1:1 p ll mode, or external clock mode. 9.2.1 normal pll mode in normal pll mode, the pll is fully programmable. it can synthesize frequencies ranging from 2x to 9x the reference frequency and has a post divider capable of reducing this synthesized frequency without disturbing the pll. the pll reference can be either a crystal oscillator or an external clock. 9.2.2 1:1 pll mode in 1:1 pll mode, the pll synthesize s a frequency equal to the external clock input reference frequency. the post divider is not active. 9.2.3 external clock mode in external clock mode, the pll is bypassed, and the external clock is applied to extal. the resulting operating frequency is equal to the external clock frequency. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 clock module 9-2 freescale semiconductor 9.3 low-power mode operation this subsection describes the operation of the clock module in low-power and halted modes of operation. low-power modes are described in chapter 7, ?power management .? table 9-1 shows the clock module operation in low-power modes. table 9-1. clock module operation in low-power modes during wakeup from a low-power mode, the flash clock always clocks through at least 16 cycles before the cpu clocks are enabled. this allows the flash module time to recover from the low-power mode, and software can immediately resume fe tching instructions from memory. in wait and doze modes, the system clocks to the peripherals are enable d, and the clocks to the cpu, flash, and sram are stopped. each m odule can disable its clock lo cally at the module level. in stop mode, all system clocks are disabled. there are several options for enabling or disabling the pll or crystal oscillator in stop mode, compromising between stop mode current and wakeup recovery time. the pll can be disabled in stop mo de, but requires a wakeup period before it can relock. the oscillator can also be disabled during stop mode, but requires a wakeup period to restart. when the pll is enabled in stop mode (stpmd[1:0]), the external clkout signal can support systems using clkout as the clock source. there is also a fast wakeup opt ion for quickly enabling the system clocks during stop recovery. this eliminates the wakeup recovery time but at the risk of se nding a potentially unstabl e clock to the system. to prevent a non-locked pll freque ncy overshoot when using the fast wakeup option, change the rfd divisor to the current rfd value pl us one before entering stop mode. in external clock mode, there are no wakeup periods for oscillator startup or pll lock. 9.4 block diagram figure shows a block diagram of the en tire clock module. the pll block in this diagram is expanded in detail in figure 9-2 . low-power mode clock operation mode exit wait clocks sent to peripheral modules only exit not caused by clock module, but normal clocking resumes upon mode exit doze clocks sent to peripheral modules only exit not caused by clock module, but normal clocking resumes upon mode exit stop all system clocks disabled exit not caused by clock module, but clock sources are re-enabled and normal clocking resumes upon mode exit halted normal exit not caused by clock module mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 clock module freescale semiconductor 9-3 . figure 9-1. clock module block diagram clkout xtal external clock osc pllref reference clock pll mfd pllmode locen clkmod[1:0] rstout clkout locks lock locs rfd[2:0] to reset module lolre locre stpmd[1:0] stop mode pllsel disclk pll clock out scaled pll clock out internal clock pllmode clkgen stop mode internal clocks lock fwkup extal mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 clock module 9-4 freescale semiconductor figure 9-2. pll block diagram 9.5 signal descriptions the clock module signals are summarized in table 9-2 and a brief description fo llows. for more detailed information, refer to chapter 14, ?signal descriptions .? 9.5.1 extal this input is driven by an external clock except when used as a connection to the external crystal when using the internal oscillator. table 9-2. signal properties name function extal oscillator or clock input xtal oscillator output clkout system clock output clkmod[1:0] clock mode select inputs rstout reset signal from reset controller stpmd clkmod[1:0] rstout mfd (4?18) locks lock locs to reset module clkout pllsel disclk mdf[2:0] phase and frequency detect loss of clock detect lock detect charge pump filter vco rfd[2:0] scaled pll clock out pll clock out reference clock locen lolre pllmode locre mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 clock module freescale semiconductor 9-5 9.5.2 xtal this output is an internal oscillator connection to the external crystal. 9.5.3 clkout this output reflects the internal system clock. 9.5.4 clkmod[1:0] these inputs are used to select the clock mode during chip configuration. 9.5.5 rstout the rstout pin is asserted by one of the following: ? internal system reset signal ? frcrstout bit in the reset cont rol status register (rcr); see section 29.4.1, ?reset control register (rcr) .? 9.6 memory map and registers the clock module programming model consists of these registers: ? synthesizer control register (syn cr), which defines clock operation ? synthesizer status register (syn sr), which reflects clock status 9.6.1 module memory map table 9-3. clock module memory map ipsbar offset register name access 1 1 s = cpu supervisor mode access only. 0x0012_0000 synthesizer control register (syncr) s 0x0012_0002 synthesizer status register (synsr) s mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 clock module 9-6 freescale semiconductor 9.6.2 register descriptions this subsection provides a description of the clock module registers. 9.6.2.1 synthesizer control register (syncr) 15 14 13 12 11 10 9 8 field lolre mfd2 mfd1 mf d0 locre rfd2 rfd1 rfd0 reset 0010_0001 r/w r/w 76 5 4 32 10 field locen disclk fwkup ? stpmd1 stpmd0 ? ? reset 0000_0000 r/w r/w r r/w r address ipsbar + 0x0012_0000 figure 9-3. synthesizer c ontrol register (syncr) table 9-4. syncr field descriptions bit(s) name description 15 lolre loss of lock reset enable. determines how the system handles a loss of lock indication. when operating in normal mode or 1:1 pll mode, the pll must be locked before setting the lolre bit. otherwise reset is immediately asserted. to prevent an immediate reset, the lolre bit must be clear ed before writing the mfd[2:0] bits or entering stop mode with the pll disabled. 1 reset on loss of lock 0 no reset on loss of lock note: in external clock mode, the lolre bit has no effect. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 clock module freescale semiconductor 9-7 14?12 mfd multiplication factor divider. contain the binary value of the divider in the pll feedback loop. the mfd[2: 0] value is the multiplication fa ctor applied to the reference frequency. when mfd[2:0] are changed or the pll is disabled in stop mode, the pll loses lock. in 1:1 pll mode, mfd[2:0] are i gnored, and the multiplication factor is one. note: in external clock mode, th e mfd[2:0] bits have no effect. 11 locre loss-of-clock reset enable. determines how the system handles a loss-of-clock condition. when the locen bit is clear, locre has no effect. if the locs flag in synsr indicates a loss-of-clock condition, setting the locre bit causes an immediate reset. to prevent an immediate reset, the locre bit must be cleared before entering stop mode with the pll disabled. 1 reset on loss-of-clock 0 no reset on loss-of-clock note: in external clock mode, the locre bit has no effect. 10?8 rfd reduced frequency divider field. the binary value written to rfd[2:0] is the pll frequency divisor. see table in mfd bit description. changing rfd[2:0] does not affect the pll or cause a relock delay. changes in clock frequency are synchronized to the next falling edge of the current system clock. to avoid surpassing the allowable system operating frequency, write to rfd[2:0] only when the lock bit is set. table 9-4. syncr field descriptions (continued) bit(s) name description (( the following table illustrate s the system frequency mult iplier of the reference frequency 1 in normal pll mode. 1 , where f sys(max) is the maximum system frequency for the particular mcf5282 device (66 mhz or 80 mhz). mfd[2:0] 000 2 (4x) 2 mfd = 000 not valid for f ref < 3 mhz 001 (6x) 010 (8x) (3) 011 (10x) 100 (12x) 101 (14x) 110 (16x) 111 (18x) rfd[2:0] 000 ( 1) 4 6 8 1012141618 001 ( 2) 3 3 default value out of reset 23 4 56789 010 ( 4) 1 3/2 2 5/2 3 7/2 4 9/2 011 ( 8) 1/2 3/4 1 5/4 3/2 7/4 2 9/4 100 ( 16) 1/4 3/8 1/2 5/8 3/4 7/8 1 9/8 101 ( 32) 1/8 3/16 1/4 5/16 3/8 7/16 1/2 9/16 110 ( 64) 1/16 3/32 1/8 5/32 3/16 7/32 1/4 9/32 111 ( 128) 1/32 3/64 1/16 5/64 3/32 7/64 1/8 9/64 f sys f ref 2mfd 2 + () 2 rfd --------------------------------------------- - f ref 2mfd 2 + () f sys max () f sys f sys max () ; ; = mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 clock module 9-8 freescale semiconductor 9.6.2.2 synthesizer status register (synsr) the synsr is a read-only register th at can be read at a ny time. writing to the synsr has no effect and terminates the cycle normally. 7 locen enables the loss-of-clock function. locen does not affect the loss of lock function. 1 loss-of-clock function enabled 0 loss-of-clock function disabled note: in external clock mode, the locen bit has no effect . 6 disclk disable clkout determines whether clkout is driven. setting the disclk bit holds clkout low. 1 clkout disabled 0 clkout enabled 5 fwkup fast wakeup determines when the system clocks are enabled during wakeup from stop mode. 1 system clocks enabled on wakeup regardless of pll lock status 0 system clocks enabled only when pll is locked or operating normally note: when fwkup = 0, if the pll or oscillator is enabled and unintentionally lost in stop mode, the pll wakes up in self-clocked mode or reference clock mode depending on the clock that was lost. in external clock mode, the fwkup bit has no effect on the wakeup sequence. 4 ? reserved, should be cleared. 3?2 stpmd control pll and clkout operation in stop mode. the following table illustrates stpmd operation in stop mode. 1?0 ? reserved, should be cleared. 76 5 4 32 10 field pllmode pllsel pllref locks lock locs ? reset see note 1 see note 2 000 r/w r address ipsbar + 0x0012_0002 note: 1. reset state determined during reset configuration. 2. see the locks and lock bit descriptions. figure 9-4. synthesizer status register (synsr) table 9-4. syncr field descriptions (continued) bit(s) name description stpmd[1:0] operation during stop mode system clocks pll osc clkout 00 disabled enabled enabled enabled 01 disabled enabled enabled disabled 10 disabled disabled enabled disabled 11 disabled disabled disabled disabled mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 clock module freescale semiconductor 9-9 table 9-5. synsr field descriptions bit(s) name description 7 pllmode clock mode bit. the pllmode bit is configured at reset and reflects the clock mode as shown in ta b l e 9 - 6 . 1 pll clock mode 0 external clock mode 6 pllsel pll select. configured at reset and reflects the pll mode as shown in ta b l e 9 - 6 . 1 normal pll mode 0 1:1 pll mode 5 pllref pll reference. configured at reset and reflects the pll reference source in normal pll mode as shown in ta b l e 9 - 6 . 1 crystal clock reference 0 external clock reference 4 locks sticky indication of pll lock status. 1 no unintentional pll loss of lock since last system reset or mfd change 0 pll loss of lock since last system rese t or mfd change or currently not locked due to exit from stop with fwkup set the lock detect function sets the locks bit when the pll achieves lock after: ? a system reset ? a write to syncr that changes the mf d[2:0] bits when the pll loses lock, locks is cleared. when the pll relocks, locks remains cleared until one of the two listed events occurs. in stop mode, if the pll is intentionally di sabled, then the locks bit reflects the value prior to entering stop mode. however, if fwkup is set, then locks is cleared until the pll regains lock. once lock is regained, the locks bit reflects the value prior to entering stop mode. furthermore, reading the locks bit at the same time that the pll loses lock does not return the current loss of lock condition. in external clock mode, locks remains cleared after reset. in normal pll mode and 1:1 pll mode, locks is set after reset. 3 lock set when the pll is locked. pll lock occurs when the synthesized frequency is within approximately 0.75 percent of the programm ed frequency. the pll loses lock when a frequency deviation of greater than approx imately 1.5 percent occurs. reading the lock flag at the same time that the pll loses lock or acquires lock does not return the current condition of the pll. the power-on reset circuit uses the lock bit as a condition for releasing reset. if operating in external clock mode, lock remains cleared after reset. 1 pll locked 0 pll not locked mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 clock module 9-10 freescale semiconductor 9.7 functional description this subsection provides a functiona l description of the clock module. 9.7.1 system clock modes the system clock source is determined during reset (see table 27-8 ). the values of clkmod[1:0] are latched during reset and are of no importance after reset is negated. if clkmod 1 or clkmod0 is changed during a reset other than powe r-on reset, the internal clocks may glitch as the system clock source is changed between external cl ock mode and pll cloc k mode. whenever clkmod1 or clkmod0 is changed in reset, an immediat e loss-of-lock condition occurs. table 9-7 shows the clockout frequency to clockin frequency relationships for the possible system clock modes. 2 locs sticky indication of whether a loss-of-clock condition has occurred at any time since exiting reset in normal pll and 1:1 pll modes. locs = 0 when the system clocks are operating normally. locs = 1 when system clocks have failed due to a reference failure or pll failure. after entering stop mode with fwkup set and the pll and oscillator intentionally disabled (stpmd[1:0] = 11), the pll exits stop mode in the scm while the oscillator starts up. during this time, locs is temporar ily set regardless of locen. it is cleared once the oscillator comes up and the pll is attempting to lock. if a read of the locs flag and a loss-of-clock condition occur simultaneously, the flag does not reflect the current loss-of-clock condition. a loss-of-clock condition can be detected only if locen = 1 or the oscillator has not yet returned from exit from stop mode with fwkup = 1. 1 loss-of-clock detected since exiting reset or oscillator not yet recovered from exit from stop mode with fwkup = 1 0 loss-of-clock not detected since exiting reset note: the locs flag is always 0 in external clock mode. 1?0 ? reserved, should be cleared. table 9-6. system clock modes pllmode:pllsel:pllref clock mode 000 external clock mode 100 1:1 pll mode 110 normal pll mode with external clock reference 111 normal pll mode with crystal reference table 9-7. clock out and clock in relationships system clock mode pll options 1 normal pll clock mode f sys = f ref 2(mfd + 2)/2 rfd 1:1 pll clock mode f sys = f ref external clock mode f sys = f ref table 9-5. synsr field de scriptions (continued) bit(s) name description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 clock module freescale semiconductor 9-11 caution xtal must be tied low in external cl ock mode when rese t is asserted. if it is not, clocks could be suspended indefinitely. the external clock is divided by two in ternally to produce the system clocks. 9.7.2 clock operation during reset in external clock mode, the system is static and does not re cognize reset until a cloc k is applied to extal. in pll mode, the pll operates in se lf-clocked mode (scm) during rese t until the input reference clock to the pll begins operating within the limits given in the electrical specifications. if a pll failure causes a reset, the system enters reset using the reference clock. then the system clock source changes to the pll operating in scm. if scm is not functiona l, the system becomes static. alternately, if the locen bit in syncr is cleared when the pll fails, the system becomes static. if external reset is asserted, the sy stem cannot enter reset unless the pll is capable of operating in scm. 9.7.3 system clock generation in normal pll clock mode, the defau lt system frequency is two times th e reference freque ncy after reset. the rfd[2:0] and mfd[2:0] bits in the syncr select the frequency multiplier. when programming the pll, do not ex ceed the maximum system clock fr equency listed in the electrical specifications. use this procedure to accommodate the frequency overshoot that occurs when the mfd bits are changed: 1. determine the appropriate value for the mfd and rfd fields in the syncr. the amount of jitter in the system clocks can be minimized by select ing the maximum mfd factor that can be paired with an rfd factor to provide the required frequency. 2. write a value of rfd (from step 1) + 1 to the rfd field of the syncr. 3. write the mfd value from step 1 to the syncr. 4. monitor the lock flag in synsr. when the pl l achieves lock, write the rfd value from step 1 to the rfd field of the syncr. this changes the system clocks frequency to the required frequency. note keep the maximum system clock fre quency below the limit given in the electrical characteristics. 9.7.4 pll operation in pll mode, the pll synthesizes th e system clocks. the pll can multip ly the reference clock frequency by 2x to 9x, provided that the syst em clock frequency remains within the range listed in electrical specifications. for example, if the reference frequenc y is 2 mhz, the pll can synt hesize frequencies of 4 mhz to 18 mhz. in additi on, the rfd can reduce the system frequency by dividing the output of the pll. 1 f ref = input reference frequency f sys = clkout frequency mfd ranges from 0 to 7. rfd ranges from 0 to 7. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 clock module 9-12 freescale semiconductor the rfd is not in the feedback loop of the pll, so changing the rfd divisor does not affect pll operation. figure 9-5 shows the external support circuitry for the crys tal oscillator with example component values. actual component values de pend on crystal specifications. the following subsections describe each major block of the pll. refer to figure to see how these functional sub-blocks interact. figure 9-5. crystal oscillator example 9.7.4.1 phase and fre quency detector (pfd) the pfd is a dual-latch phase-freque ncy detector. it compares both the phase and frequency of the reference and feedback clocks. the reference clock come s from either the crystal oscillator or an external clock source. v ss v sssyn extal xtal rs rf c1 c2 on-chip 8-mhz crystal configuratio c1 = c2 = 16 pf rf = 1 m rs = 470 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 clock module freescale semiconductor 9-13 the feedback clock comes fr om one of the following: ? clkout in 1:1 pll mode ? vco output divided by two if clkou t is disabled in 1:1 pll mode ? vco output divided by the mfd in normal pll mode when the frequency of the feedback clock equals the frequency of the reference clock, the pll is frequency-locked. if the falling edge of the feedback clock lags the fa lling edge of the reference clock, the pfd pulses the up signal. if the falling edge of the f eedback clock leads the fall ing edge of the reference clock, the pfd pulses the down signal . the width of these pulses relati ve to the reference clock depends on how much the two clocks lead or lag each other. once phase lock is achieved, the pfd continues to pulse the up and down signals for very short duratio ns during each reference clock cycle. these short pulses continually update the pll and prevent the frequency drift phenomenon known as dead-banding. 9.7.4.2 charge pump/loop filter in 1:1 pll mode, the charge pump us es a fixed current. in normal mo de the current magnitude of the charge pump varies with the mfd as shown in table 9-8 . the up and down signals from th e pfd control whether the charge pump applies or removes charge, respectively, from the l oop filter. the filter is integrated on the chip. 9.7.4.3 voltage control output (vco) the voltage across the loop filter controls the frequency of the vc o output. the frequency-to-voltage relationship (vco gain) is positive, and the output frequency is four times the target system frequency. 9.7.4.4 multiplication factor divider (mfd) when the pll is not in 1:1 pll mode, the mfd divides the output of the vco and feeds it back to the pfd. the pfd controls the vco freque ncy via the charge pump and loop filter such that the reference and feedback clocks have the same fr equency and phase. thus, the frequenc y of the input to the mfd, which is also the output of the vco, is the reference frequency multiplied by the same amount that the mfd divides by. for example, if the mfd divides the vc o frequency by six, the pll is frequency locked when the vco frequency is six times the reference frequency. the presence of the mfd in the loop allows the pll to perform frequency mu ltiplication, or synthesis. in 1:1 pll mode, the mfd is bypassed, and th e effective multiplicat ion factor is one. 9.7.4.5 pll lock detection the lock detect logic monitors th e reference frequency a nd the pll feedback frequency to determine when frequency lock is achieved. phase lock is inferred by the frequency re lationship, but is not guaranteed. the lock flag in the synsr reflects the pll lock stat us. a sticky lock flag, lo cks, is also provided. table 9-8. charge pump current a nd mfd in normal mode operation charge pump current mfd 1x 0 mfd < 2 2x 2 mfd < 6 4x 6 mfd mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 clock module 9-14 freescale semiconductor the lock detect function uses two c ounters. one is clocked by the refere nce and the other is clocked by the pll feedback. when the reference c ounter has counted n cycles, its count is compared to that of the feedback counter. if the feedback counter has also counted n cycles, the process is repeated for n + k counts. then, if the tw o counters still match, the lock criteria is relaxed by 1/2 and the system is notified that the pll has achieved frequency lock. after lock is detected, the lock circuit continues to monitor the reference and feedback frequencies using the alternate count and compare pro cess. if the counters do not match at any comparison time, then the lock flag is cleared to indi cate that the pll has lost lock. at this point, the lock criteria is tightened and the lock detect process is repeated. the alternate count sequences preven t false lock detects due to freque ncy aliasing while the pll tries to lock. alternating between tight and relaxed lock criteria pr events the lock dete ct function from randomly toggling between locked and non-locked status due to phase sensitivities. figure 9-6 shows the sequence for detecting locked and non-locked conditions. in external clock mode, the pll is disabled and cannot lock. figure 9-6. lock detect sequence 9.7.4.6 pll loss of lock conditions once the pll acquires lock after reset, the lock and locks flags are set. if the mfd is changed, or if an unexpected loss of lock condition occu rs, the lock and lock s flags are negated. while the pll is in the non-locked condition, the system clocks continue to be sourced from th e pll as the pll attempts to relock. consequently, during the relocking process, the system clocks fre quency is not well defined and may exceed the maximum system frequency, vi olating the system cloc k timing specifications. however, once the pll has relocked, the lock flag is set. the locks flag remain s cleared if the loss of lock is unexpected. the locks flag is set when the loss of lock is caused by changing mfd. if the pll is intentionally disabled duri ng stop mode, then after exit from stop mode, the locks flag reflects the value prior to entering stop mode once lock is regained. count n reference cycles and compare number of feedback cycles elapsed start with tight lock criteria reference count feedback count loss of lock detected set tight lock criteria and notify system of loss of lock condition count n + k reference cycles and compare number of feedback cycles elapsed lock detected. set relaxed lock condition and notify system of lock condition reference count feedback count reference count = feedback count = n in same count/compare sequence reference count = feedback count = n + k in same count/compare sequence mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 clock module freescale semiconductor 9-15 9.7.4.7 pll loss of lock reset if the lolre bit in the sy ncr is set, a loss of lock condition asserts reset. re set reinitializes the lock and locks flags. therefore, softwa re must read the lol bit in th e reset status register (rsr) to determine if a loss of lock caused the reset. see section 29.4.2, ?reset stat us register (rsr) .? to exit reset in pll mode, the reference must be present, and the pll must achieve lock. in external clock mode, the pll ca nnot lock. therefore, a loss of lo ck condition cannot occur, and the lolre bit has no effect. 9.7.4.8 loss of clock detection the locen bit in the syncr enables the loss of clock detection circui t to monitor the input clocks to the phase and frequency detector ( pfd). when either the reference or feedback clock frequency falls below the minimum frequency, the loss of clock ci rcuit sets the sticky locs flag in the synsr. note in external clock mode, the loss of clock circuit is disabled. 9.7.4.9 loss of clock reset the clock module can assert a reset when a loss of cl ock or loss of lock occurs. when a loss-of-clock condition is recognized, reset is asse rted if the locre bit in syncr is set. the locs bit in synsr is cleared after reset. therefore, the loc bit must be read in rsr to de termine that a loss of clock condition occurred. locre has no effect in external clock mode. to exit reset in pll mode, the reference must be present, and the pll must acquire lock. reset initializes the clock m odule registers to a known star tup state as described in section 9.6, ?memory map and registers .? 9.7.4.10 alternate clock selection depending on which clock source fails, the loss-of-clock circuit switches the system clocks source to the remaining operational clock. the alternat e clock source generates the system clocks until reset is asserted. as table 9-9 shows, if the reference fails, the pll goes out of lock and into self-clocked mode (scm). the pll remains in scm until the ne xt reset. when the pll is operating in scm, the system frequency depends on the value in the rfd fi eld. the scm system frequency stat ed in electrical specifications assumes that the rf d has been programme d to binary 000. if the loss-of-clock c ondition is due to pll failure, the pll reference becomes th e system clocks source until the next reset, even if the pll regains and relocks. table 9-9. loss of clock summary clock mode system clock source before failure reference failure alternate clock selected by loc circuit 1 until reset 1 the loc circuit monitors the reference and feedback inputs to the pfd. see figure 9-5 . pll failure alternate clock selected by loc circuit until reset pll pll pll self-clocked mode pll reference external external clock none na mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 clock module 9-16 freescale semiconductor a special loss-of-clock condition occurs when both the reference and the pll fa il. the failures may be simultaneous, or the pll may fail first. in either case, the refere nce clock failure take s priority and the pll attempts to operate in scm. if successful, the pll remains in scm until the next reset. if the pll cannot operate in scm, the system re mains static until the next reset. both the reference and the pll must be functioning properly to exit reset. 9.7.4.11 loss of clock in stop mode table 9-10 shows the resulting actions for a loss of clock in stop mode when the device is being clocked by the various clocking methods. table 9-10. stop mode operation (sheet 1 of 5) mode in locen locre lolre pll osc fwkup expected pll action at stop pll action during stop mode out lockss lock locs comments ext x x x x x x ? ? ext 0 0 0 lose reference clock stuck ??? nrm 0 0 0 off off 0 lose lock, f.b. clock, reference clock regain nrm ?lk 1 ?lc no regain stuck ? ? ? nrm x 0 0 off off 1 lose lock, f.b. clock, reference clock regain clocks, but don?t regain lock scm?> unstable nrm 0?>?l k 0?> 1 1?>?l c block locs and locks until clock and lock respectively regain; enter scm regardless of locen bit until reference regained no reference clock regain scm?> 0?> 0?> 1?> block locs and locks until clock and lock respectively regain; enter scm regardless of locen bit no f.b. clock regain stuck ??? mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 clock module freescale semiconductor 9-17 nrm 0 0 0 off on 0 lose lock regain nrm ?lk 1 ?lc block locks from being cleared lose reference clock or no lock regain stuck ??? lose reference clock, regain nrm ?lk 1 ?lc block locks from being cleared nrm 0 0 0 off on 1 lose lock no lock regain unstable nrm 0?>?l k 0?> 1 ?lc block locks until lock regained lose reference clock or no f.b. clock regain stuck ??? lose reference clock, regain unstable nrm 0?>?l k 0?> 1 ?lc locs not set because locen = 0 nrm 000onon0 ? ? nrm ?lk 1 ?lc lose lock or clock stuck ? ? ? lose lock, regain nrm 0 1 ?lc lose clock and lock, regain nrm 0 1 ?lc locs not set because locen = 0 nrm 000onon1 ? ? nrm ?lk 1 ?lc lose lock unstable nrm 0 0?> 1 ?lc lose lock, regain nrm 0 1 ?lc lose clock stuck ? ? ? lose clock, regain without lock unstable nrm 0 0?> 1 ?lc lose clock, regain with lock nrm 0 1 ?lc nrm x x 1 off x x lose lock, f.b. clock, reference clock reset reset ? ? ? reset immediately table 9-10. stop mode operation (sheet 2 of 5) mode in locen locre lolre pll osc fwkup expected pll action at stop pll action during stop mode out lockss lock locs comments mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 clock module 9-18 freescale semiconductor nrm 001ononx ? ? nrm ?lk 1 ?lc lose lock or clock reset ? ? ? reset immediately nrm 1 0 0 off off 0 lose lock, f.b. clock, reference clock regain nrm ?lk 1 ?lc ref not entered during stop; scm entered during stop only during oscillator startup no regain stuck ? ? ? nrm 1 0 0 off on 0 lose lock, f.b. clock regain nrm ?lk 1 ?lc ref mode not entered during stop no f.b. clock or lock regain stuck ??? lose reference clock scm 0 0 1 wakeup without lock nrm 1 0 0 off on 1 lose lock, f.b. clock regain f.b. clock unstable nrm 0?>?l k 0?> 1 ?lc ref mode not entered during stop no f.b. clock regain stuck ??? lose reference clock scm 0 0 1 wakeup without lock nrm 100onon0 ? ? nrm ?lk 1 ?lc lose reference clock scm 0 0 1 wakeup without lock lose f.b. clock ref 0 x 1 wakeup without lock lose lock stuck ? ? ? lose lock, regain nrm 0 1 ?lc nrm 100onon1 ? ? nrm ?lk 1 ?lc lose reference clock scm 0 0 1 wakeup without lock lose f.b. clock ref 0 x 1 wakeup without lock lose lock unstable nrm 0 0?> 1 ?lc table 9-10. stop mode operation (sheet 3 of 5) mode in locen locre lolre pll osc fwkup expected pll action at stop pll action during stop mode out lockss lock locs comments mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 clock module freescale semiconductor 9-19 nrm 101ononx ? ? nrm ?lk 1 ?lc lose lock or clock reset ? ? ? reset immediately nrm 1 1 x off x x lose lock, f.b. clock, reference clock reset reset ? ? ? reset immediately nrm 110onon0 ? ? nrm ?lk 1 ?lc lose clock reset ? ? ? reset immediately lose lock stuck ? ? ? lose lock, regain nrm 0 1 ?lc nrm 110onon1 ? ? nrm ?lk 1 ?lc lose clock reset ? ? ? reset immediately lose lock unstable nrm 0 0?> 1 ?lc lose lock, regain nrm 0 1 ?lc nrm 111ononx ? ? nrm ?lk 1 ?lc lose clock or lock reset ? ? ? reset immediately ref 100xxx ? ? ref 0 x 1 lose reference clock stuck ??? scm 100offx 0pll disabled regain scm scm 0 0 1 wakeup without lock scm 100offx 1pll disabled regain scm scm 0 0 1 scm 1 0 0 on on 0 ? ? scm 0 0 1 wakeup without lock lose reference clock scm table 9-10. stop mode operation (sheet 4 of 5) mode in locen locre lolre pll osc fwkup expected pll action at stop pll action during stop mode out lockss lock locs comments mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 clock module 9-20 freescale semiconductor scm 1 0 0 on on 1 ? ? scm 0 0 1 lose reference clock scm note: pll = pll enabled during stop mode. pll = on when stpmd[1:0] = 00 or 01 osc = oscillator enabled during stop mode. osci llator is on when stpmd[1:0] = 00, 01, or 10 modes nrm = normal pll crystal clock reference or normal pll external reference or pll 1:1 mode. during pll 1:1 or normal external reference mode, the oscillator is never enab led. therefore, during these modes, refer to the osc = on case regardless of stpmd values. ext=external clock mode ref=pll reference mode due to losing pll clock or lock from nrm mode scm=pll self-clocked mode due to losing reference clock from nrm mode reset= immediate reset locks ?lk= expecting previous value of locks before entering stop 0?>?lk= current value is 0 until lock is regained wh ich then will be the previous value before entering stop 0?> = current value is 0 until lock is regained but lock is never expected to regain locs ?lc=expecting previous value of locs before entering stop 1?>?lc= current value is 1 until clock is regained whic h then will be the previous value before entering stop 1?> =current value is 1 until clock is regained but clk is never expected to regain table 9-10. stop mode operation (sheet 5 of 5) mode in locen locre lolre pll osc fwkup expected pll action at stop pll action during stop mode out lockss lock locs comments mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor 10-1 chapter 10 interrupt controller modules this section details the functionality for the interrupt controllers (intc0, intc1) . the general features of each interrupt controller include: ? 63 interrupt sources, organized as: ? 56 fully-programmabl e interrupt sources ? 7 fixed-level interrupt sources ? each of the 63 sources has a unique interrupt control register (icr nx ) to define the software-assigned levels and priorities within the level ? unique vector number for each interrupt source ? ability to mask any individual interrupt source, plus globa l mask-all capability ? supports both hardware and software interrupt acknowledge cycles ? ?wake-up? signal from low-power stop modes the 56 fully-programmable and seven fixed-level interrupt sources for each of the two interrupt controllers handle the complete set of interrupt sources from all of the modules on the device. this section describes how the interrupt sources are mapped to the interrupt controller logic and how interrupts are serviced. 10.1 68k/coldfire interrupt architecture overview before continuing with the specifics of the interrupt c ontrollers, a brief review of the interrupt architecture of the 68k/coldfire family is appropriate. the interrupt architecture of coldfire is exactly th e same as the m68000 family , where there is a 3-bit encoded interrupt priority level sent from the interrupt contro ller to the core, providi ng 7 levels of interrupt requests. level 7 represents the highe st priority interrupt level, while level 1 is the lowest priority. the processor samples for active interr upt requests once per instruction by comparing the encoded priority level against a 3-bit interrupt mask va lue (i) contained in bits 10:8 of the machine?s st atus register (sr). if the priority level is grea ter than the sr[i] field at the sample point, the processor suspends normal instruction execution and initiates interrupt exce ption processing. level 7 interrupts are treated as non-maskable and edge-sensitive within the processor, while levels 1-6 are treated as level-sensitive and may be masked depending on the value of the sr[i] field. for correct ope ration, the coldfire requires that, once asserted, the interrupt source rema in asserted until explic itly disabled by the in terrupt service routine. during the interrupt exception processing, the cpu ente rs supervisor mode, disables trace mode and then fetches an 8-bit vector from the in terrupt controller. this byte-sized operand fetch is known as the interrupt acknowledge (iack) cycl e with the coldfire implementation using a special encoding of the transfer type and transfer modifier attri butes to distinguish this da ta fetch from a ?normal? memory access. the fetched data provides an index into the ex ception vector table which contains 256 addresses, each pointing to the beginning of a specific exception se rvice routine. in particular, ve ctors 64 - 255 of the exception vector table are reserved for user interr upt service routines. the first 64 exception vectors are reserved for the processor to handle reset, error conditions (access, addr ess), arithmetic faults, syst em calls, etc. once the interrupt vector number has been re trieved, the processor continues by creating a stack frame in memory. for coldfire, all exception stack frame s are 2 longwords in length, and c ontain 32 bits of vector and status register data, along with th e 32-bit program counter value of the instruction that was interrupted (see mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 interrupt controller modules 10-2 freescale semiconductor section 2.3.3.1, ?exception stack frame definition ? for more information on the stack frame format). after the exception stack frame is stored in memory, the processor accesses the 32-bit pointer from the exception vector table using the vector number as the offset, and then jumps to that address to begin execution of the service routin e. after the status register is stored in the exception stack frame, the sr[i] mask field is set to the level of the interrupt being acknowledged, eff ectively masking that level and all lower values while in the service routine. for many peripheral devices, the proces sing of the iack cycle directly negates the interr upt request, while other devi ces require that request to be explicitly negated during the processing of the service routine. for this device, the processing of the interrupt acknow ledge cycle is fundamentally different than previous 68k/coldfire cores. in the new approach, all iack cycles are direct ly handled by the interrupt controller, so the requesting peripheral device is not accessed during the iack. as a result, the interrupt request must be explicitly cleared in the peri pheral during the interrupt service r outine. for more information, see section 10.1.1.3, ?interrupt vector determination .? unlike the m68000 family, all coldfire processors guarantee that the first instruction of the service routine is executed before sampling for interrupts is resumed. by making this initial instru ction a load of the sr, interrupts can be safely disabled, if required. during the execution of the service ro utine, the appropriate actions mu st be performed on the peripheral to negate the interrupt request. for more information on exception proces sing, see the coldfire programmer?s reference manual at http://www.freescale.com/coldfire . 10.1.1 interrupt controlle r theory of operation to support the interrupt architecture of the 68k/c oldfire programming model, the combined 63 interrupt sources are organized as 7 levels, with each level supporting up to 9 prioritize d requests. consider the interrupt priority structure shown in table 10-1 , which orders the interrupt levels/priorities from highest to lowest. table 10-1. interrupt priority scheme interrupt level icr[il] priority icr[ip] supported interrupt sources 7 7 #8?63 6 5 4 ? (mid-point) #7 (irq7) 3 #8?63 2 1 0 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 interrupt controller modules freescale semiconductor 10-3 the level and priority is fully pr ogrammable for all sources except in terrupt sources 1?7. interrupt source 1?7 (from the edgeport module) are fixed at the corr esponding level?s midpoint priority. thus, a maximum of 8 fully-programmable interrupt sources are mapped into a single interrupt level. the ?fixed? interrupt source is hardwired to the given level, and represents the mid-point of the priority within the level. for the fully-programmable interrupt sources, the 3-bit level and the 3-bit priori ty within the level are defined in the 8-bit interrupt control register (icrnx ). the operation of the interrupt controller can be br oadly partitioned into three activities: ? recognition ? prioritization ? vector determination during iack 10.1.1.1 interrupt recognition the interrupt controller continuously examines the request sources and the in terrupt mask register to determine if there are active requests. this is the recognition phase. 6 7?4 #8?63 ? (mid-point) #6 (irq6) 3?0 #8?63 5 7?4 #8?63 ? (mid-point) #5 (irq5) 3?0 #8?63 4 7?4 #8?63 ? (mid-point) #4 (irq4) 3?0 #8?63 3 7?4 #8?63 ? (mid-point) #3 (irq3) 3?0 #8?63 2 7?4 #8?63 ? (mid-point) #2 (irq2) 3?0 #8?63 1 7?4 #8?63 ? (mid-point) #1 (irq1) 3?0 #8?63 table 10-1. interrupt priority scheme (continued) interrupt level icr[il] priority icr[ip] supported interrupt sources mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 interrupt controller modules 10-4 freescale semiconductor 10.1.1.2 interrupt prioritization as an active request is detected, it is translated into the programmed interrupt level, and the resulting 7-bit decoded priority level (irq[7:1]) is driven out of the interru pt controller. the decode d priority levels from all the interrupt controllers are logically summed toge ther and the highest enabled interrupt request is then encoded into a 3-bit priority level that is sent to the processor core during this prioritization phase. 10.1.1.3 interrupt vector determination once the core has sampled for pending interrupts a nd begun interrupt exception processing, it generates an interrupt acknowledge cycle (iack). the iack transfer is treated as a memory-mapped byte read by the processor, and routed to the appr opriate interrupt controller. next, th e interrupt controller extracts the level being acknowledged from address bits[4:2], and then determines the highest pr iority interrupt request active for that level, and returns th e 8-bit interrupt vector for that reque st to complete the cycle. the 8-bit interrupt vector is formed using the following algorithm: for intc0, vector_number = 64 + interrupt source number for intc1, vector_number = 128 + interrupt source number recall vector_numbers 0 - 63 are reserved for the coldfi re processor and its intern al exceptions. thus, the following mapping of bit positions to vector numbers applies for the intc0: if interrupt source 1 is active and acknowledged, then vector_number = 65 if interrupt source 2 is active and acknowledged, then vector_number = 66 ... if interrupt source 8 is active and acknowledged, then vector_number = 72 if interrupt source 9 is active and acknowledged, then vector_number = 73 ... if interrupt source 62 is active and acknowledged, then vector_number = 126 the net effect is a fixed mapping be tween the bit position within the s ource to the actual interrupt vector number. if there is no active interrupt source for the given level, a special ?spurious interrupt? vector (vector_number = 24) is return ed and it is the responsibility of th e service routine to handle this error situation. note this protocol implies the interrupting peripheral is not accesse d during the acknowledge cycle since the interrupt controller completely services the ac knowledge. this means the in terrupt source must be explicitly disabled in the interrupt service routine. this design provide s unique vector capability for all interrupt requests, regardless of the ?complexity? of the peripheral device. vector numbers 64-71, and 91-255 are unused. 10.2 memory map the register programming model for the interrupt controllers is memo ry-mapped to a 256-byte space. in the following discussion, ther e are a number of program- visible registers greater th an 32 bits in size. for these control fields, the physical regi ster is partitioned into two 32-bit values: a regi ster ?high? (the upper longword) and a regi ster ?low? (the lower longword). the nomenclature interrupt controller modules freescale semiconductor 10-5 the registers and their lo cations are defined in table 10-3 . the offsets listed star t from the base address for each interrupt controller. the base addresse s for the interrupt controllers are listed below: table 10-2. interrupt controller base addresses interrupt controller number base address intc0 ipsbar + 0xc00 intc1 ipsbar + 0xd00 global iack registers space 1 1 this address space only contains the l1ack-l7iack registers. see section 10.3.7, ?software and level n iack registers (swiackr, l1iack?l7iack) " for more information ipsbar + 0xf00 table 10-3. interrupt controller memory map module offset bits[31:24] bit s[23:16] bits[15:8] bits[7:0] 0x00 interrupt pending register high (iprh), [63:32] 0x04 interrupt pending register low (iprl), [31:1] 0x08 interrupt mask register high (imrh), [63:32] 0x0c interrupt mask register low (imrl), [31:0] 0x10 interrupt force register high (intfrch), [63:32] 0x14 interrupt force register low (intfrcl), [31:1] 0x18 irlr[7:1] iacklpr[7:0] reserved 0x1c?0x3c reserved 0x40 reserved icr01 icr02 icr03 0x44 icr04 icr05 icr06 icr07 0x48 icr08 icr09 icr10 icr11 0x4c icr12 icr13 icr14 icr15 0x50 icr16 icr17 icr18 icr19 0x54 icr20 icr21 icr22 icr23 0x58 icr24 icr25 icr26 icr27 0x5c icr28 icr29 icr30 icr31 0x60 icr32 icr33 icr34 icr35 0x64 icr36 icr37 icr38 icr39 0x68 icr40 icr41 icr42 icr43 0x6c icr44 icr45 icr46 icr47 0x70 icr48 icr49 icr50 icr51 0x74 icr52 icr53 icr54 icr55 0x78 icr56 icr57 icr58 icr59 0x7c icr60 icr61 icr62 icr63 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 interrupt controller modules 10-6 freescale semiconductor 10.3 register descriptions 10.3.1 interrupt pending registers (iprh n , iprl n ) the iprh n and iprl n registers, figure 10-1 and figure 10-2, are each 32 bits in si ze, and provide a bit map for each interrupt request to indicate if there is an active request (1 = active request, 0 = no request) for the given source. the state of the interr upt mask register doe s not affect the ipr n. the ipr n is cleared by reset. the ipr n is a read-only register, so any attempted write to this register is ignored. bit 0 is not implemented and reads as a zero. 0x80?0xdc reserved 0xe0 swiack reserved 0xe4 l1iack reserved 0xe8 l2iack reserved 0xec l3iack reserved 0xf0 l4iack reserved 0xf4 l5iack reserved 0xf8 l6iack reserved 0xfc l7iack reserved 31 16 field int[63:48] reset 0000_0000_0000_0000 r/w r 15 0 field int[47:32] reset 0000_0000_0000_0000 r/w r ipsbar + 0xc00, 0xd00 figure 10-1. interrupt pending register high (iprh n ) table 10-3. interrupt controller memory map (continued) module offset bits[31:24] bit s[23:16] bits[15:8] bits[7:0] mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 interrupt controller modules freescale semiconductor 10-7 . 10.3.2 interrupt mask register (imrh n , imrl n ) the imrh n and imrl n registers are each 32 bits in size and provide a bit map for each interrupt to allow the request to be disabled (1 = disable the request, 0 = enable the request). the imr n is set to all ones by reset, disabling all inte rrupt requests. the imr n can be read and written. a writ e that sets bit 0 of the imr forces the other 63 bits to be set, disabling all inte rrupt sources, and providing a global mask-all capability. table 10-4. iprh n field descriptions bits name description 31?0 int interrupt pending. each bit corresponds to an interrupt source. the corresponding imrh n bit determines whether an interrupt condition can gener ate an interrupt. at every system clock, the iprhn samples the signal generated by the interrupting source. the corresponding iprh n bit reflects the state of the interrupt signal even if the corresponding imrh n bit is set. 0 the corresponding interrupt source does not have an interrupt pending 1 the corresponding interrupt source has an interrupt pending 31 16 field int[31:16] reset 0000_0000_0000_0000 r/w r 15 10 field int[16:1] ? reset 0000_0000_0000_0000 r/w r ipsbar + 0xc04, 0xd04 figure 10-2. interrupt pending register low (iprl n ) table 10-5. iprl n field descriptions bits name description 31?1 int interrupt pending. each bit corresponds to an interrupt source. the corresponding imrl n bit determines whether an interrupt condition can gener ate an interrupt. at every system clock, the iprl n samples the signal generated by the interrupting source. the corresponding iprl n bit reflects the state of the interrupt signal even if the corresponding imrl n bit is set. 0 the corresponding interrupt source does not have an interrupt pending 1 the corresponding interrupt source has an interrupt pending 0 ? reserved, should be cleared. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 interrupt controller modules 10-8 freescale semiconductor . . 31 16 field int_mask[63:48] reset 1111_1111_1111_1111 r/w r/w 15 0 field int_mask[47:32] reset 1111_1111_1111_1111 r/w r/w ipsbar + 0xc08, 0xd08 figure 10-3. interrupt mask register high (imrh n ) table 10-6. imrh n field descriptions bits name description 31?0 int_mask interrupt mask. each bit corresponds to an interrupt source. the corresponding imrh n bit determines whether an interrupt condition can generate an interrupt. the corresponding iprhn bit reflects the state of the interrupt signal even if the corresponding imrh n bit is set. 0 the corresponding interrupt source is not masked 1 the corresponding interrupt source is masked 31 16 field int_mask[31:16] reset 1111_1111_1111_1111 r/w r/w 15 10 field int_mask[16:1] maskall reset 1111_1111_1111_1111 r/w r/w ipsbar + 0xc0c, 0xd0c figure 10-4. interrupt mask register low (imrl n ) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 interrupt controller modules freescale semiconductor 10-9 note if an interrupt source is being mask ed in the interrupt controller mask register (imr) or a modul e?s interrupt mask regi ster while the interrupt mask in the status register (sr[i]) is set to a value lower than the interrupt?s level, a spurious interrupt may occur. this is because by the time the status register acknowledges this interrupt, the interrupt has been masked. a spurious interrupt is generated because the cpu cannot determine the interrupt source. to avoid this situat ion for interrupts sources with levels 1-6, first write a higher level interrupt mask to the status register, before setting the mask in the imr or the module?s interrupt mask register. after the mask is set, return the interrupt mask in the status regi ster to its previous value. since level seven in terrupts cannot be disabled in the status register prior to masking, use of the imr or module interrupt mask registers to disable level seven interrupts is not recommended. 10.3.3 interrupt force registers (intfrch n , intfrcl n ) the intfrch n and intfrcl n registers are each 32 bi ts in size and provide a mechanism to allow software generation of interrupt s for each possible source for func tional or debug purposes. the system design may reserve one or more sources to allow so ftware to self-schedule interrupts by forcing one or more of these bits (1 = force request, 0 = negate request) in the appropriate intfrc n register. the assertion of an interrupt request via the intfrc n register is not affected by the interrupt mask register. the intfrc n register is cleared by reset. table 10-7. imrl n field descriptions bits name description 31?1 int_mask interrupt mask. each bit corresponds to an interrupt source. the corresponding imrl n bit determines whether an interrupt condition can generate an interrupt. the corresponding iprl n bit reflects the state of the interrupt signal even if the corresponding imrl n bit is set. 0 the corresponding interrupt source is not masked 1 the corresponding interrupt source is masked 0 maskall mask all interrupts. setting this bit will force the other 63 bits of the imrh n and imrl n to ones, disabling all interrupt sources, and providing a global mask-all capability. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 interrupt controller modules 10-10 freescale semiconductor . 31 16 field intfrch[63:48] reset 0000_0000_0000_0000 r/w r/w 15 0 field intfrch[47:32] reset 0000_0000_0000_0000 r/w r/w ipsbar + 0xc10, 0xd10 figure 10-5. interrupt force register high (intfrch n ) table 10-8. intfrch n field descriptions bits name description 31?0 intfrc interrupt force. allows software generation of interrupts for each possible source for functional or debug purposes. 0 no interrupt forced on corresponding interrupt source 1 force an interrupt on the corresponding source 31 16 field intfrcl[31:16] reset 0000_0000_0000_0000 r/w r/w 15 10 field intfrcl[16:1] ? reset 0000_0000_0000_0000 r/w r/w ipsbar + 0xc14, 0xd14 figure 10-6. interrupt force register low (intfrcl n ) table 10-9. intfrcl n field descriptions bits name description 31?1 intfrc interrupt force. allows software generation of interrupts for each possible source for functional or debug purposes. 0 no interrupt forced on corresponding interrupt source 1 force an interrupt on the corresponding source 0 ? reserved, should be cleared. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 interrupt controller modules freescale semiconductor 10-11 10.3.4 interrupt request level register (irlr n ) this 7-bit register is upda ted each machine cycle a nd represents the current interrupt requests for each interrupt level, where bit 7 corresponds to level 7, bit 6 to level 6, etc. this register output is combined with similar outputs from intc1 and eventually encoded into the 3-bit priority interrupt level driven to the processor core. 10.3.5 interrupt acknowledge level and priority register (iacklpr n ) each time an iack is performed, the interrupt contro ller responds with the v ector number of the highest priority source within th e level being acknowledged. in addition to providing th e vector number directly for the byte-sized iack read, this 8-bit register is al so loaded with information about the interrupt level and priority being acknowledged. this register provides the asso ciation between the acknowledged ?physical? interrupt request number and the program med interrupt level/priority. the contents of this read-only register are described in figure 10-8 and table 10-11 . 7 210 field irq[7:1] ? reset 0000_0000 r/w r address ipsbar + 0xc18, 0xd18 figure 10-7. interrupt request level register (irlr n ) table 10-10. irq n field descriptions bits name description 7?1 irq interrupt requests. represents the prioritized active interrupts for each level. 0 there are no active interrupts at this level 1 there is an active interrupt at this level 0?reserved 76 43 0 field ? level pri reset 0000_0000 r/w r address ipsbar + 0xc19, 0xd19 figure 10-8. iack level and priority register (iacklpr n ) table 10-11. iacklpr n field descriptions bits name description 7?reserved mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 interrupt controller modules 10-12 freescale semiconductor 10.3.6 interrupt control register (icr nx , ( x = 1, 2,..., 63)) each icr nx specifies the interrupt level (1-7) and the priority within the level (0-7). all icr nx registers can be read, but only icr n 8 to icr n63 can be written. it is the respons ibility of the software to program the icr nx registers with unique and non-overlapping level and priority defi nitions. failure to program the icr nx registers in this manner can result in undefined behavior. if a specif ic interrupt request is completely unused, the icr nx value can remain in its reset (and disabled) state. 6?4 level interrupt level. represents the interrupt level currently being acknowledged. 3?0 pri interrupt priority. represents the priority within the interrupt level of the interrupt currently being acknowledged. 0 priority 0 1 priority 1 2 priority 2 3 priority 3 4 priority 4 5 priority 5 6 priority 6 7 priority 7 8 mid-point priority associated with the fixed level interrupts only 7 6 53 20 field ? il ip reset 0000_0000 r/w r/w (read only for icr n 1-icr n 7) address see table 10-2 and ta b l e 1 0 - 3 for register offsets note: it is the responsibility of th e software to program the icr n x registers with unique and non-overlapping level and priority definitions. failure to program the icr n x registers in this manner can result in undefined behavior. if a specific interrupt request is completely unused, the icr n x value can remain in its reset (and disabled) state. figure 10-9. interrupt control register (icr nx ) table 10-12. icr nx field descriptions bits name description 7?6 ? reserved, should be cleared. 5?3 il interrupt level. indicates the interrupt level assigned to each interrupt input. 2?0 ip interrupt priority. indicates the interrupt priority for internal modules within the interrupt-level assignment. 000b represents the lowest priority and 111b represents the highest. for the fixed level interrupt sources, the priority is fixed at the midpoi nt for the level, and the ip field will always read as 000b. table 10-11. iacklpr n field descriptions (continued) bits name description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 interrupt controller modules freescale semiconductor 10-13 10.3.6.1 interrupt sources table 10-13 and table 10-14 list the interrupt sources for each interrupt request line for intc0 and intc1. table 10-13. interrupt source assignment for intc0 source module flag source description flag clearing mechanism 1 eport epf1 edge port flag 1 write epf1 = 1 2 epf2 edge port flag 2 write epf2 = 1 3 epf3 edge port flag 3 write epf3 = 1 4 epf4 edge port flag 4 write epf4 = 1 5 epf5 edge port flag 5 write epf5 = 1 6 epf6 edge port flag 6 write epf6 = 1 7 epf7 edge port flag 7 write epf7 = 1 8 scm swt1 software watchdog timeout cleared when service complete 9 dma done dma channel 0 transfer complete write done = 1 10 done dma channel 1 transfer complete write done = 1 11 done dma channel 2 transfer complete write done = 1 12 done dma channel 3 transfer complete write done = 1 13 uart0 multiple uart0 interrupt cleared when service complete 14 uart1 multiple uart1 interrupt cleared when service complete 15 uart2 multiple uart2 interrupt cleared when service complete 16 not used 17 i 2 ciifi 2 c interrupt write iif = 0 18 qspi multiple qspi interrupt see qir description 19 dtim0 cap/ref dtim0 capture/reference event write cap = 1 or ref = 1 20 dtim1 cap/ref dtim1 capture/reference event write cap = 1 or ref = 1 21 dtim2 cap/ref dtim2 capture/reference event write cap = 1 or ref = 1 22 dtim3 cap/ref dtim3 capture/reference event write cap = 1 or ref = 1 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 interrupt controller modules 10-14 freescale semiconductor 23 fec note: not used on mcf5214 & mcf5216 x_intf transmit frame interrupt write x_intf = 1 24 x_intb transmit buffer interrupt write x_intb = 1 25 un transmit fifo underrun write un = 1 26 rl collision retry limit write rl = 1 27 r_intf receive frame interrupt write r_intf = 1 28 r_intb receive buffer interrupt write r_intb = 1 29 mii mii interrupt write mii = 1 30 lc late collision write lc = 1 31 hberr heartbeat error write hberr = 1 32 gra graceful stop complete write gra = 1 33 eberr ethernet bus error write eberr = 1 34 babt babbling transmit error write babt = 1 35 babr babbling receive error write babr = 1 36 pmm lvdf lvd write lvdf = 1 37 qadc cf1 queue 1 conversion complete write cf1 = 0 after reading cf1 = 1 38 cf2 queue 2 conversion complete write cf2 = 0 after reading cf2 = 1 39 pf1 queue 1 conversion pause write pf1 = 0 after reading pf1 = 1 40 pf2 queue 2 conversion pause write pf2 = 0 after reading pf2 = 1 41 gpta tof timer overflow write tof = 1 or access timcnth/l if tffca = 1 42 paif pulse accumulator input write paif = 1 or access pac if tffca = 1 43 paovf pulse accumulator overflow write paovf = 1 or access pac if tffca = 1 44 c0f timer channel 0 write c0f = 1 or access ic/oc if tffca = 1 45 c1f timer channel 1 write c1f = 1 or access ic/oc if tffca = 1 46 c2f timer channel 2 write c2f = 1 or access ic/oc if tffca = 1 47 c3f timer channel 3 write c3f = 1 or access ic/oc if tffca = 1 48 gptb tof timer overflow write tof = 1 or access timcnth/l if tffca = 1 49 paif pulse accumulator input write paif = 1 or access pac if tffca = 1 50 paovf pulse accumulator overflow write paovf = 1 or access pac if tffca = 1 51 c0f timer channel 0 write c0f = 1 or access ic/oc if tffca = 1 52 c1f timer channel 1 write c1f = 1 or access ic/oc if tffca = 1 53 c2f timer channel 2 write c2f = 1 or access ic/oc if tffca = 1 54 c3f timer channel 3 write c3f = 1 or access ic/oc if tffca = 1 55 pit0 pif pit interrupt flag write pif = 1 of write pmr table 10-13. interrupt source assignment for intc0 (continued) source module flag source description flag clearing mechanism mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 interrupt controller modules freescale semiconductor 10-15 56 pit1 pif pit interrupt flag write pif = 1 of write pmr 57 pit2 pif pit interrupt flag write pif = 1 of write pmr 58 pit3 pif pit interrupt flag write pif = 1 of write pmr 59 cfm cbeif sgfm buffer empty write cbeif = 1 60 cfm ccif sgfm command complete cleared automatically 61 cfm pvif protection violation cleared automatically 62 cfm aeif access error cleared automatically 63 not used table 10-13. interrupt source assignment for intc0 (continued) source module flag source description flag clearing mechanism mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 interrupt controller modules 10-16 freescale semiconductor 10.3.7 software and level n iack registers (swiackr, l1iack?l7iack) the eight iack registers can be explicitly addressed via the cpu, or implicitly addressed via a processor-generated interrupt acknowledge cycle during exception processing. in ei ther case, the interrupt controller?s actions are very similar. first, consider an iack cycle to a specific level: that is, a level-n iack . when this type of iack arrives in the interrupt controller, the c ontroller examines all the currentl y-active level n interrupt requests, determines the highest pr iority within the level, and then re sponds with the unique vector number corresponding to that specific interrupt source. the vector number is suppl ied as the data for the byte-sized iack read cycle. in addition to pr oviding the vector number, the interrupt controller also loads the level and priority number for the level into the iack lpr register, where it may be retrieved later. this interrupt controller design al so supports the concept of a software iack. a software iack is a useful concept that allows an interrupt service routine to determine if there are other pending interrupts so that the overhead associated with interrupt excepti on processing (including m achine state save/restore functions) can be minimized. in general, the software iack is pe rformed near the end of an interrupt table 10-14. interrupt source assignment for intc1 source module flag source descri ption flag clearing mechanism 1-7 not used 8flex can buf0i message buffer 0 interrupt wri te buf0i = 1 after reading buf0i = 1 9 buf1i message buffer 1 interrupt wri te buf1i = 1 after reading buf1i = 1 10 buf2i message buffer 2 interrupt write buf2i = 1 after reading buf2i = 1 11 buf3i message buffer 3 interrupt write buf3i = 1 after reading buf3i = 1 12 buf4i message buffer 4 interrupt write buf4i = 1 after reading buf4i = 1 13 buf5i message buffer 5 interrupt write buf5i = 1 after reading buf5i = 1 14 buf6i message buffer 6 interrupt write buf6i = 1 after reading buf6i = 1 15 buf7i message buffer 7 interrupt write buf7i = 1 after reading buf7i = 1 16 buf8i message buffer 8 interrupt write buf8i = 1 after reading buf8i = 1 17 buf9i message buffer 9 interrupt write buf9i = 1 after reading buf9i = 1 18 buf10i message buffer 10 interrupt write buf10i = 1 after reading buf10i = 1 19 buf11i message buffer 11 interrupt write buf11i = 1 after reading buf11i = 1 20 buf12i message buffer 12 interrupt write buf12i = 1 after reading buf12i = 1 21 buf13i message buffer 13 interrupt write buf13i = 1 after reading buf13i = 1 22 buf14i message buffer 14 interrupt write buf14i = 1 after reading buf14i = 1 23 buf15i message buffer 15 interrupt write buf15i = 1 after reading buf15i = 1 24 err_int error interrupt write err_ int = 1 after reading err_int = 1 25 boff_int bus-off interrupt write boff _int = 1 after reading boff_int = 1 26 wake_int wake-up interrupt write wake_ int = 1 after reading wake_int = 1 27-63 not used mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 interrupt controller modules freescale semiconductor 10-17 service routine, and if there are additional active interrupt sources, th e current interrupt service routine (isr) passes control to the appropriate service routine, but without taking another interrupt exception. when the interrupt controller receives a software iack read, it returns the vect or number associated with the highest level, highest priority unmasked interrupt source for that interrupt controller. the iacklpr register is also loaded as the software iack is performed. if there are no active sources, the interrupt controller returns an al l-zero vector as the operand. for this si tuation, the iacklpr register is also cleared. in addition to the iack registers within each interrupt controll er, there are global l niack registers. a read from one of the global l n iack registers returns the vector for the highest priority unmasked interrupt within a level for all interrupt c ontrollers. there is no global swiack register . however, reading the swiack register from each inte rrupt controller returns the vect or number of the highest priority unmasked request within that controller. 10.4 prioritization between interrupt controllers the interrupt controllers have a fi xed priority, where intc 0 has the highest priority, and intc1 has the lowest priority. if both inte rrupt controllers have active interrupts at the same level and priority, then the intc0 interrupt will be serviced fi rst. if intc1 has an active interrupt that has a higher level or priority than the highest intc0 interrupt, then th e intc1 interrupt will be serviced first. 10.5 low-power wakeup operation the system control module (scm) c ontains an 8-bit low-power interr upt control register (lpicr) used explicitly for controlling the low- power stop mode. this re gister must explicit ly be programmed by software to enter low-power mode. each interrupt controller provides a special combinatorial logic path to provide a special wake-up signal to exit from the low-power stop mode. this special mode of opera tion works as follows: ? first, lpicr[6:4] is loaded with the mask level that will be specified while the core is in stop mode. lpicr[7] must be set to enable this mode of operation. 76 43 0 field vector reset 0000_0000 r/w r address see table 10-2 and ta b l e 1 0 - 3 for register offsets figure 10-10. software and level n iack registers (swiackr, l1iack?l7iack) table 10-15. swiack and l1iack-l7iack field descriptions bits name description 7?0 vector vector number. a read from the swiack regist er returns the vector nu mber associated with the highest level, highest priority unmasked in terrupt source. a read from one of the l n ack registers returns the highest priority unmasked interrupt source within the level. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 interrupt controller modules 10-18 freescale semiconductor note the wakeup mask level taken from lpi cr[6:4] is adjusted by hardware to allow a level 7 irq to generate a wa keup. that is, the wakeup mask value used by the interrupt controller must be in the range of 0?6. ? second, the processor executes a stop instructi on which places it in stop mode. once the processor is stopped, each interrupt controller en ables a special logic path which evaluates the incoming interrupt sources in a purely combinator ial path; that is, there are no clocked storage elements. if an active interrupt reque st is asserted and the resulting interrupt level is greater than the mask value contained in lpi cr[6:4], then each interrupt contro ller asserts the wake-up output signal, which is routed to the scm where it is combined with the wakeup signals from the other interrupt controller and then to the pll module to re-enable the device?s clock trees and resume processing. ? mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor 11-1 chapter 11 edge port module (eport) 11.1 introduction the edge port module (eport) has se ven external inte rrupt pins, irq7 ?irq1 . each pin can be configured individually as a level-sensitive inte rrupt pin, an edge-detecting interrupt pin (rising edge, falling edge, or both), or a general-purpose input/output (i/o) pin. see figure 11-1 . figure 11-1. eport block diagram 11.2 low-power mode operation this section describes the operation of the eport m odule in low-power modes. for more information on low-power modes, see chapter 7, ?power management .? table 11-1 shows eport module operation in low-power modes, and desc ribes how this module may exit from each mode. note the low-power interrupt c ontrol register (lpicr) in the system control module specifies the interrupt level at or above which is needed to bring the device out of a low-power mode. ipbus synchronizer epdr[n] epfr[n] eppar[2n, 2n + 1] epier[n] edge detect d0 stop logic eppdr[n] d1 q d0 d1 q mode epddr[n] to interrupt controller irqx pin rising edge of system clock mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 edge port module (eport) 11-2 freescale semiconductor table 11-1. edge port module operation in low-power modes in wait and doze modes, the eport module continue s to operate as it does in run mode. it may be configured to exit the low-power m odes by generating an interrupt reques t on either a sele cted edge or a low level on an external pin. in stop mode, there are no clocks avai lable to perform the edge-detect function. only the level-detect logic is active (if configured) to allow any low level on the external interrupt pin to generate an interrupt (if enabled) to exit stop mode. note the input pin synchronizer is bypassed for the level-detect logic since no clocks are available. 11.3 interrupt/general-pur pose i/o pin descriptions all pins default to general-purpose i nput pins at reset. the pin value is synchronized to the rising edge of clkout when read from the eport pin data register (eppdr). the valu es used in the edge/level detect logic are also synchronized to the rising edge of clkout. these pi ns use schmitt trig gered input buffers which have built in hysteresis de signed to decrease the probability of generating false edge-triggered interrupts for slow rising and falling input signals. when a pin is configured as an output, it is driven to a state whose level is de termined by the corresponding bit in the eport data register (epdr). all bits in the epdr are high at reset. low-power mode eport operation mode exit wait normal any irqx interrupt at or above level in lpicr doze normal any irqx interrupt at or above level in lpicr stop level-sensing only any irqx interrupt set for level-sensing at or above level in lpicr mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 edge port module (eport) freescale semiconductor 11-3 11.4 memory map and registers this subsection describes the memory map and register structure. 11.4.1 memory map refer to table 11-2 for a description of the eport memory map. the eport has an ipsbar offset for base address of 0x0013_0000. 11.4.2 registers the eport programming model cons ists of these registers: ? the eport pin assignment register (eppar) controls the function of each pin individually. ? the eport data direction register (epddr) controls the direct ion of each one of the pins individually. ? the eport interrupt enable regi ster (epier) enables interrupt re quests for each pin individually. ? the eport data register (epdr) holds the data to be driven to the pins. ? the eport pin data register (eppdr) reflects the current state of the pins. ? the eport flag register (epfr) indi vidually latches eport edge events. 11.4.2.1 eport pin assignm ent register (eppar) table 11-2. edge port module memory map ipsbar offset bits 15?8 bits 7?0 access 1 1 s = cpu supervisor mode access only. s/u = cpu supervisor or user mode access. user mode accesses to supervisor only addresses have no effect and result in a cycl e termination transfer error. 0x0013_0000 eport pin assignment register (eppar) s 0x0013_0002 eport data direction register (epd dr) eport interrupt enable register (epier) s 0x0013_0004 eport data register (epdr) eport pin data register (eppdr) s/u 0x0013_0006 eport flag register (epfr) reserved 2 2 writing to reserved address locations has no effect, and reading returns 0s. s/u 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 field eppa7 eppa6 eppa5 eppa4 eppa3 eppa2 eppa1 ? reset 0000_0000_0000_0000 r/w r/w r address ipsbar + 0x0013_0000, 0x0013_0001 figure 11-2. eport pin assignment register (eppar) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 edge port module (eport) 11-4 freescale semiconductor 11.4.2.2 eport data dir ection register (epddr) table 11-3. eppar field descriptions bit(s) name description 15?2 eppax eport pin assignment select fields. the read/write eppax fields configure eport pins for level detection and rising and/or falling edge detection. pins configured as level-sensitive are inve rted so that a logic 0 on the external pin represents a valid interrupt request. level-sensit ive interrupt inputs are not latched. to guarantee that a level-sensitive interrup t request is acknowledged, the interrupt source must keep the signal asserted until acknowledged by software. level sensitivity must be selected to bring the device out of stop mode with an irqx interrupt. pins configured as edge-triggered are latched and need not remain asserted for interrupt generation. a pin configured fo r edge detection can trigger an interrupt regardless of its configuration as input or output. interrupt requests generated in the eport module can be masked by the interrupt controller module. eppar functionality is independent of the selected pin direction. reset clears the eppax fields. 00 pin irqx level-sensitive 01 pin irqx rising edge triggered 10 pin irqx falling edge triggered 11 pin irqx both falling edge and rising edge triggered 1?0 ? reserved, should be cleared. 765 43210 field epdd7 epdd6 epdd5 epdd4 epdd3 epdd2 epdd1 ? reset 0000_0000 r/w r/w r address ipsbar + 0x0013_0002 figure 11-3. eport data di rection register (epddr) table 11-4. epdd field descriptions bit(s) name description 7?1 epddx setting any bit in the epddr configures the corresponding pin as an output. clearing any bit in epddr configures the corresponding pin as an input. pin direction is independent of the level/edge detection c onfiguration. reset clears epdd7-epdd1. to use an eport pin as an external interrupt request source, its corresponding bit in epddr must be clear. software can generate interrupt requests by programming the eport data register when the epddr selects output. 1 corresponding eport pin configured as output 0 corresponding eport pin configured as input 0 ? reserved, should be cleared. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 edge port module (eport) freescale semiconductor 11-5 11.4.2.3 edge port interrupt enable register (epier) 11.4.2.4 edge port data register (epdr) 765 43210 field epie7 epie6 epie5 epie4 epie3 epie2 epie1 ? reset 0000_0000 r/w r/w r address ipsbar + 0x0013_0003 figure 11-4. eport port interrupt enable register (epier) table 11-5. epier field descriptions bit(s) name description 7?1 epiex edge port interrupt enable bits enable eport interrupt requests. if a bit in epier is set, eport generates an interrupt request when: ? the corresponding bit in the eport flag register (epfr) is set or later becomes set. ? the corresponding pin level is low and the pin is configured for level-sensitive operation. clearing a bit in epier negates any interrupt request from the corresponding eport pin. reset clears epie7-epie1. 1 interrupt requests from corresponding eport pin enabled 0 interrupt requests from corresponding eport pin disabled 0 ? reserved, should be cleared. 765 43210 field epd7 epd6 epd5 epd4 epd3 epd2 epd1 ? reset 1111_1111 r/w r/w r address ipsbar + 0x0013_0004 figure 11-5. eport port data register (epdr) table 11-6. epdr field descriptions bit(s) name description 7?1 epdx edge port data bits. data written to epdr is stored in an internal register; if any pin of the port is configured as an output, the bi t stored for that pin is driven onto the pin. reading edpr returns the data stored in the register. reset sets epd7-epd1. 0 ? reserved, should be cleared. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 edge port module (eport) 11-6 freescale semiconductor 11.4.2.5 edge port pin data register (eppdr) 11.4.2.6 edge port flag register (epfr) 765 43210 field eppd7 eppd6 eppd5 eppd4 eppd3 eppd2 eppd1 ? reset current pin state 0 r/w r address ipsbar + 0x0013_0005 figure 11-6. eport port pin data register (eppdr) table 11-7. eppdr field descriptions bit(s) name description 7?1 eppdx edge port pin data bits . the read-only eppdr reflects th e current state of the eport pins irq7 ?irq1 . writing to eppdr has no effect, and the write cycle terminates normally. reset does not affect eppdr. 0 ? reserved, should be cleared. 765 43210 field epf7 epf6 epf5 epf4 epf3 epf2 epf1 ? reset 0000_0000 r/w r/w r address ipsbar + 0x0013_0006 figure 11-7. eport port flag register (epfr) table 11-8. epfr field descriptions bit(s) name description 7?1 epfx edge port flag bits. when an eport pin is configured for edge triggering, its corresponding read/write bit in epfr indicates that the selected edge has been detected. reset cl ears epf7-epf1. bits in this register are set when the sele cted edge is detected on the corresponding pin. a bit remains set until cleared by writi ng a 1 to it. writing 0 has no effect. if a pin is configured as level-sensitive (epparx = 00 ), pin transitions do not affect this register. 1 selected edge for irqx pin has been detected. 0 selected edge for irqx pin has not been detected. 0 ? reserved, should be cleared. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor 12-1 chapter 12 chip select module this chapter describes the chip select module, in cluding the operation and pr ogramming model of the chip select registers, which include the chip se lect address, mask, and control registers. note unless otherwise noted, in this chapter, ?clock? refers to the clkout used for the bus. 12.1 overview the following list summarizes the key chip select features: ? up to seven independent, user-progr ammable chip select signals (cs [6:0]) that can interface with external sram, prom, eprom, eeprom, flash, and peripherals ? address masking for 64-kbyte to 4-gbyte memory block sizes 12.2 chip select module signals table 12-1 lists signals used by the chip select module. table 12-2 shows the interaction of the byte-enable /byte-write enables with related signals. table 12-1. chip select module signals signal description chip selects (cs [6:0]) each cs n can be independently programmed for an address location as well as for masking, port size, read/write burst capability, wait-state genera tion, and internal/external termination. only cs 0 is initialized at reset and may act as an external boot chip select to allow boot rom to be at an external address space. port size for cs 0 is configured by the logic levels of d[19:18] when rsto negates and rcon is asserted. output enable (oe ) interfaces to memory or to peripheral devices and enables a read transfer. it is asserted and negated on the falling edge of the clock. oe is asserted only when one of the chip selects matches for the current address decode. byte strobes bs [3:0] these signals are individually programmed through the byte-enable mode bit, cscr n [bem], described in section 12.4.1.3, ?chip select control registers (cscr0?cscr6) ?. these generated signals provide byte data select si gnals, which are decoded from the transfer size, a1, and a0 signals in addition to the programmed port size and burstability of the memory accessed, as table 12-2 shows. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 chip select module 12-2 freescale semiconductor table 12-2. byte enables/byte write enable signal settings transfer size port size a1 a0 bs 3 bs2 bs1 bs0 d[31:24] d[23:16] d[15:8] d[7:0] b y t e8 - b i t000111 010111 100111 110111 1 6 - b i t000111 011011 100111 111011 3 2 - b i t000111 011011 101101 111110 w o r d8 - b i t000111 010111 100111 110111 1 6 - b i t000011 100011 3 2 - b i t000011 101100 l o n g w o r d8 - b i t000111 010111 100111 110111 1 6 - b i t000011 100011 3 2 - b i t000000 l i n e8 - b i t000111 010111 100111 110111 1 6 - b i t000011 100011 3 2 - b i t000000 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 chip select module freescale semiconductor 12-3 12.3 chip select operation each chip select has a dedicated set of registers for configuration and control. ? chip select address registers (csar n) control the base address of the chip select. see section 12.4.1.1, ?chip select addr ess registers (csar0?csar6) ?. ? chip select mask registers (csmr n) provide 16-bit addr ess masking and acc ess control. see section 12.4.1.2, ?chip select mask registers (csmr0?csmr6) ?. ? chip select control registers (cscr n ) provide port size and burst capability indication, wait-state generation, and automatic acknowle dge generation features. see section 12.4.1.3, ?chip select control registers (cscr0?cscr6) ?. cs0 is a global chip select after reset a nd provides relocatable boot rom capability. 12.3.1 general chip select operation when a bus cycle is initiated, th e device first compares its address with the base address and mask configurations programmed for ch ip selects 0?6 (configured in cscr 0?cscr6) and dram blocks 0 and 1 (configured in dacr0 and dacr1). if the driven address matches a programmed chip select or dram block, the appropriate chip select is asserted or the dram block is selected using the specifications programmed in the respective c onfiguration register. otherwise, the following occurs: ? if the address and attributes do not match in csar or dacr, the device runs an external burst-inhibited bus cycle with a default of external termination on a 32-bit port. ? should an address and attribute match in multiple cscrs, the matching chip select signals are driven; however, the chip select si gnals are driven during an extern al burst-inhibited bus cycle with external termination on a 32-bit port. ? if the address and attribute match both dacrs or a dacr and a csar, the operation is undefined. table 12-3 shows the type of access as a func tion of match in the csars and dacrs. 12.3.1.1 8-, 16-, and 32-bit port sizing static bus sizing is progr ammable through the port size bits, cscr[ps]. see section 12.4.1.3, ?chip select control registers (cscr0?cscr6) ? for more information. figure 12-1 shows the correspondence table 12-3. accesses by matches in csars and dacrs number of cscr matches number of dacr matches type of access 00e x t e r n a l 1 0 defined by csar multiple 0 external, burst-inhibited, 32-bit 0 1 defined by dacrs 1 1 undefined multiple 1 undefined 0 multiple undefined 1 multiple undefined multiple multiple undefined mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 chip select module 12-4 freescale semiconductor between the data bus and the extern al byte strobe control lines (bs [3:0]). note that all byte lanes are driven, although the state of unus ed byte lanes is undefined. figure 12-1. connections for external memory port sizes 12.3.1.2 external boot chip select operation cs0 , the external boot chip select, al lows address decoding fo r boot rom before syst em initialization. its operation differs from other external chip select outputs after system reset. after system reset, cs0 is asserted for every external access. no other chip select can be used until the valid bit, csmr0[v], is set, at which point cs0 functions as configured and cs [6:1] can be used. at reset, the port size function of the external boot chip select is determined by the logic levels of the inputs on d[19:18]. table 12-4 and table 12-4 list the various reset encodi ngs for the configuration signals multiplexed with d[19:18]. provided the required address range is in the chip select address re gister (csar0), cs0 can be programmed to continue decoding for a range of addr esses after the csmr0[v] is set, after which the external boot chip select can be restored only by a system reset. 12.4 chip select registers table 12-5 shows the chip select register memory ma p. reading reserved locations returns zeros. table 12-4. d[19:18] external boot chip select configuration d[19:18] boot device/data port size 00 internal (32-bit) 01 external (16-bit) 10 external (8-bit) 11 external (32-bit) byte 0 8-bit port 16-bit port 32-bit port byte 1 byte 2 byte 3 byte 0 byte 1 byte 2 byte 3 byte 0 byte 1 byte 2 byte 3 d[31:24] d[23:16] d[15:8] d[7:0] external memory memory memory data bus bs3 bs2 bs1 bs0 driven, undefined driven, undefined mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 chip select module freescale semiconductor 12-5 table 12-5. chip select registers ipsbar offset [31:24] [23:16] [15:8] [7:0] 0x00_0080 chip select address register?bank 0 (csar0) [p. 12-6] reserved 1 1 addresses not assigned to a register and undefined register bits are reserved for expansion. write accesses to these reserved address spaces and reserved register bits have no effect. 0x00_0084 chip select mask register?bank 0 (csmr0) [p. 12-6] 0x00_0088 reserved 1 chip select contro l register?bank 0 (cscr0) [p. 12-7] 0x00_008c chip select address register?bank 1 (csar1) [p. 12-6] reserved 1 0x00_0090 chip select mask register?bank 1 (csmr1) [p. 12-6] 0x00_0094 reserved 1 chip select contro l register?bank 1 (cscr1) [p. 12-7] 0x00_0098 chip select address register?bank 2 (csar2) [p. 12-6] reserved 1 0x00_009c chip select mask register?bank 2 (csmr2) [p. 12-6] 0x00_00a0 reserved 1 chip select contro l register?bank 2 (cscr2) [p. 12-7] 0x00_00a4 chip select address register?bank 3 (csar3) [p. 12-6] reserved 1 0x00_00a8 chip select mask register?bank 3 (csmr3) [p. 12-6] 0x00_00ac reserved 1 chip select contro l register?bank 3 (cscr3) [p. 12-7] 0x00_00b0 chip select address register?bank 4 (csar4) [p. 12-6] reserved 1 0x00_00b4 chip select mask register?bank 4 (csmr4) [p. 12-6] 0x00_00b8 reserved 1 chip select contro l register?bank 4 (cscr4) [p. 12-7] 0x00_00bc chip select address register?bank 5 (csar5) [p. 12-6] reserved 1 0x00_00c0 chip select mask register?bank 5 (csmr5) [p. 12-6] 0x00_00c4 reserved 1 chip select contro l register?bank 5 (cscr5) [p. 12-7] 0x00_00c8 chip select address register?bank 6 (csar6) [p. 12-6] reserved 1 0x00_00cc chip select mask register?bank 6 (csmr6) [p. 12-6] 0x00_00d0 reserved 1 chip select contro l register?bank 6 (cscr6) [p. 12-7] mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 chip select module 12-6 freescale semiconductor 12.4.1 chip select module registers the chip select module is program med through the chip select addre ss registers (csar0?csar6), chip select mask registers (csmr0?csmr6), and the chip select control registers (cscr0?cscr6). 12.4.1.1 chip select addres s registers (csar0?csar6) the csars, figure 12-2 , specify the chip select base addresses. table 12-6 describes csar[ba]. 12.4.1.2 chip select mask registers (csmr0?csmr6) the csmrs, figure 12-3 , are used to specify the address mask and allowable access types for the respective chip selects. . table 12-7 describes csmr fields. 15 0 field ba reset uninitialized r/w r/w address 0x080 (csar0); 0x08c (csar1); 0x098 (csar2); 0x0a4 (csar3); 0x0b0 (csar4); 0x0bc (csar5); 0x0c8 (csar6) figure 12-2. chip select address registers (csar n ) table 12-6. csar n field description bits name description 15?0 ba base address. defines the base address for memory dedicated to chip select cs [6:0]. ba is compared to bits 31?16 on the internal address bus to determine if chip select memory is being accessed. 31 1615 9876543210 field bam ? wp ? am c/i sc sd uc ud v reset unitialized 0 r/w r/w addr 0x084 (csmr0); 0x090 (csmr1); 0x09c (csmr2); 0x0a8 (csmr3); 0x0b4 (csmr4); 0x0c0 (csmr5); 0x0cc (csmr6) figure 12-3. chip select mask registers (csmr n ) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 chip select module freescale semiconductor 12-7 12.4.1.3 chip select control registers (cscr0?cscr6) each cscr, shown in figure 12-4 , controls the auto-acknowledge, port size, burst capability, and activation of each chip select. note that to support th e external boot chip select, cs0 , the cscr0 reset values differ from the other cscrs. cs0 allows address decoding for boot rom before system initialization. table 12-7. csmr n field descriptions bits name description 31?16 bam base address mask. defines the chip select bl ock by masking address bits. setting a bam bit causes the corresponding csar bit to be ignored in the decode. 0 corresponding address bit is used in chip select decode. 1 corresponding address bit is a don?t care in chip select decode. the block size for cs [6:0] is 2 n where n = (number of bits set in respective csmr[bam]) + 16. so, if csar0 = 0x0000 and cs mr0[bam] = 0x0001, cs0 addresses a 128-kbyte (2 17 byte) range from 0x0000?0x1_ffff. likewise, for cs0 to access 32 mbytes (2 25 bytes) of address space starting at location 0x0000, and for cs1 to access 16 mbytes (2 24 bytes) of address space starting after the cs0 space, then csar0 = 0x0000, csmr0[bam] = 0x01ff, csar1 = 0x0200, and csmr1[bam] = 0x00ff. 8 wp write protect. controls write accesses to the addr ess range in the corresponding csar. attempting to write to the range of addresses for which csar n [wp] = 1 results in the appropriate chip select not being selected. no exception occurs. 0 both read and write accesses are allowed. 1 only read accesses are allowed. 7 ? reserved, should be cleared. 6 am alternate master. when am = 0 during a dma access, sc, sd, uc, and ud are don?t cares in the chip select decode. 5?1 c/i, sc, sd, uc, ud address space mask bits. these bits determine whethe r the specified accesses can occur to the address space defined by the bam for this chip select. c/i cpu space and interrupt acknowledge cycle mask sc supervisor code address space mask sd supervisor data address space mask uc user code address space mask ud user data address space mask 0 the address space assigned to this chip select is available to the specified access type. 1 the address space assigned to this chip select is not available (masked) to the specified access type. if this address space is accessed, chip select is not activated and a regular external bus cycle occurs. note that if am = 0, sc, sd, uc, and ud are ignored in the chip select decode on dma access. 0 v valid bit. indicates whether the corresponding csar, csmr, and cscr contents are valid. programmed chip selects do not assert un til v is set (except for cs0 , which acts as the global chip select). reset clears each csmr n [v]. 0 chip select invalid 1 chip select valid mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 chip select module 12-8 freescale semiconductor figure 12-4. chip select control registers (cscr n ) table 12-8 describes cscr n fields. 15 14 13 10 9 8 7 6 5 4 3 2 0 field ? ws ? aa ps1 ps0 bem bstr bstw ? reset: cscr0 ? 11_11 ? 1 d19 d18 ? ? reset: other cscr s uninitialized r/w r/w address 0x08a (cscr0); 0x096 (cscr1); 0x0a2 (cscr2); 0x0ae (cscr3); 0x0ba (cscr4); 0x0c6 (cscr5); 0x0d2 (cscr6) table 12-8. cscr n field descriptions bits name description 15?14 ? reserved, should be cleared. 13?10 ws wait states. the number of wait states inserted before an internal transfer acknowledge is generated (ws = 0 inserts zero wait states, ws = 0x f inserts 15 wait states). if aa = 0, ta must be asserted by the external system regardle ss of the number of wait states ge nerated. in that case, the external transfer acknowledge ends the cycle. an external ta supercedes the generation of an internal ta . 9 ? reserved, should be cleared. 8 aa auto-acknowledge enable. determines the assertion of the internal transfer acknowledge for accesses specified by the chip select address. 0 no internal ta is asserted. cycle is terminated externally. 1 internal ta is asserted as specified by ws. note that if aa = 1 for a corresponding cs n and the external system asserts an external ta before the wait-state countdown asserts the internal ta , the cycle is terminated. burst cycles increment the address bus between each internal termination. 7?6 ps port size. specifies the width of the data associat ed with each chip select. it determines where data is driven during write cycles and where data is sampled during read cycles. see section 12.3.1.1, ?8-, 16-, and 32-bit port sizing ?. 00 32-bit port size. valid data sampled and driven on d[31:0] 01 8-bit port size. valid data sampled and driven on d[31:24] 1x 16-bit port size. valid data sampled and driven on d[31:16] 5 bem byte enable mode. specifies the byte enable opera tion. certain srams have byte enables that must be asserted during reads as well as writes. bem can be set in the relevant cscr to provide the appropriate mode of byte enable in support of these srams. 0bs is not asserted for read. bs is asserted for data write only. 1bs is asserted for read and write accesses. 4 bstr burst read enable. specifies whether burst reads are used for memory associated with each cs n . 0 data exceeding the specified port size is broken into individual, port-sized non-burst reads. for example, a longword read from an 8-bit port is broken into four 8-bit reads. 1 enables data burst reads larger than the specified port size, including longword reads from 8- and 16-bit ports, word reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 chip select module freescale semiconductor 12-9 3 bstw burst write enable. specifies whether burst writ es are used for memory associated with each cs n . 0 break data larger than the specified port size into individual port-sized, non-burst writes. for example, a longword write to an 8-bit port takes four byte writes. 1 enables burst write of data larger than the specif ied port size, including longword writes to 8 and 16-bit ports, word writes to 8-bit ports and line writes to 8-, 16-, and 32-bit ports. 2?0 ? reserved, should be cleared. table 12-8. cscr n field descriptions (continued) bits name description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 chip select module 12-10 freescale semiconductor mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor 13-1 chapter 13 external interface module (eim) this chapter describes data -transfer operations, error co nditions, and reset operations. chapter 15, ?synchronous dram controller module ,? describes dram cycles. note unless otherwise noted, in this chapter, ?clock? refers to the clkout used for the bus. 13.1 features the following list summari zes bus operation features: ? up to 24 bits of addr ess and 32 bits of data ? access 8-, 16-, and 32- bit data port sizes ? generates byte, word, longword, and line-size transfers ? burst and burst-inhibited transfer support ? optional internal terminat ion for external bus cycles 13.2 bus and control signals table 13-1 summarizes the bus signals described in chapter 14, ?signal descriptions ?. table 13-1. coldfire bus signal summary signal name description i/o clkout edge a[23:0] address bus o rising bs 1 1 these signals change after the falling edge. in the electrical specifications , these signals are specified off of the rising edge because clkin is squared up internally. byte selects o falling cs [6:0] 1 chip selects o falling d[31:0] data bus i/o rising oe 1 output enable o falling r/w read/write o rising siz[1:0] transfer size o rising ta transfer acknowledge i rising tip transfer in progress o rising ts transfer start o rising mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 external interface module (eim) 13-2 freescale semiconductor 13.3 bus characteristics the device uses its system clock to generate clkout. therefore, the external bus operates at the same speed as the bus clock rate , where all bus operations are synchronous to the ri sing edge of clkout, and some of the bus control signals (bs , oe , and cs n ,) are synchronous to th e falling edge, shown in figure 13-1 . bus characteristics may differ somewh at for interfacing with external dram. figure 13-1. signal relationship to clkout for non-dram access 13.4 data transfer operation data transfers between the processor and other devices involve the following signals: ? address bus (a[23:0]) ? data bus (d[31:0]) ? control signals (ts and ta ) ?cs n , oe , bs ? attribute signals (r/w , siz, and tip ) the address bus, write data, ts , and all attribute signals change on the rising edge of clkout. read data is latched into the processor on the rising edge of clkout. the bus supports byte, word, and longword operand transfers and allo ws accesses to 8- , 16-, and 32-bit data ports. aspects of the transfer, such as the port size, the number of wait states for the external slave being accessed, and whether in ternal transfer termination is enabled, can be programmed in the chip-select control registers (cscrs) and the dram control registers (dacrs). figure 13-2 shows the byte lanes that extern al memory should be connected to and the sequential transfers if a longword is transferred for three port sizes. fo r example, an 8-bit memory should be connected to d[31:24] (bs3 ). a longword transfer takes four transfer s on d[31:24], starting with the msb and going to the lsb. rising-edge signals falling-edge signals inputs t vo t ho t vo t ho t si t hi clkout t vo = propagation delay of signal relative to clkout edge t ho = output hold time relative to clkout edge t si = required input setup time relative to clkout edge t hi = required input hold time relative to clkout edge mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 external interface module (eim) freescale semiconductor 13-3 figure 13-2. connections for external memory port sizes the timing relationship of chip selects (cs [7:0]), byte selects (bs [3:0]), and output enable (oe ) with respect to clkout is similar in that all transitions occur during the low phase of clkout. however, due to differences in on-chip signal routing, signals may not assert simultaneously. figure 13-3. chip-select module output timing diagram 13.4.1 bus cycle execution when a bus cycle is initiated, the devi ce first compares the address of th at bus cycle with the base address and mask configurations programmed for chip se lects 0?7 (confi gured in cscr0?cscr7) and dram block 0 and 1 address and control registers (configured in dacr0 a nd dacr1). if the driven address compares with one of the programmed chip selects or dram blocks, the appropriat e chip select is asserted or the dram block is selected using the specifi cations programmed by the user in the respective configuration register. otherwise, the following occurs: ? if the address and attributes do not match in cs cr or dacr, the processor runs an external burst-inhibited bus cycle with a default of external termination on a 32-bit port. ? should an address and attribute match in multip le cscrs, the matching chip-select signals are driven; however, the processor runs an external bur st-inhibited bus cycle with external termination on a 32-bit port. ? should an address and attribute match both da crs or a dacr and a cscr, the operation is undefined. table 13-2 shows the type of access as a func tion of match in the cscrs and dacrs. processor data bus byte 0 8-bit port 16-bit port 32-bit port byte 1 byte 2 byte 3 byte 0 byte 1 byte 2 byte 3 byte 0 byte 1 byte 2 byte 3 d[31:24] d[23:16] d[15:8] d[7:0] external memory memory memory byte enable bs3 bs2 bs1 bs0 driven with indeterminate values driven with indeterminate values cs [7:0] clkout bs [3:0] oe mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 external interface module (eim) 13-4 freescale semiconductor basic operation of the bus is a three-clock bus cycle: 1. during the first clock, the address, attributes, and ts are driven. 2. data and ta are sampled during the second clock of a bus -read cycle. during a read, the external device provides data and is sampled at the rising edge at the end of the second bus clock. this data is concurrent with ta , which is also sampled at the rising edge of the clock. during a write, the coldfire device drives data from the rising clock edge at the end of the first clock to the rising clock edge at the end of the bus cycle. wait stat es can be added between the first and second clocks by dela ying the assertion of ta . ta can be configured to be generated internally through the cscrs. if ta is not generated internally, the sy stem must provide it externally. 3. the last clock of the bus cycle uses what would be an idle clock between cycles to provide hold time for address, attributes and write data. figure 13-6 and figure 13-8 show the basic read and write operations. 13.4.2 data transfer cycle states the data transfer operation is contro lled by an on-chip state machine. ea ch bus clock cycle is divided into two states. even states occur when clkout is high and odd states occur when clk out is low. the state transition diagram for basic and fast termin ation read and write cycles are shown in figure 13-4 . table 13-2. accesses by matches in cscrs and dacrs number of cscr matches number of dacr matches type of access 0 0 external 1 0 defined by cscr multiple 0 external, burst-inhibited, 32-bit 0 1 defined by dacrs 1 1 undefined multiple 1 undefined 0 multiple undefined 1 multiple undefined multiple multiple undefined mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 external interface module (eim) freescale semiconductor 13-5 figure 13-4. data transfer state transition diagram table 13-3 describes the states as they appear in subsequent timing diagrams. table 13-3. bus cycle states state cycle clkout description s0 all high the read or write cycle is initiated in s0. on the rising edge of clkout, the device places a valid address on the address bus and drives r/w high for a read and low for a write, if it is not already in the appropriate state. the processor asserts tip , siz[1:0], and ts on the rising edge of clkout. s1 all low the appropriate cs n , bs , and oe signals assert on the clkout falling edge. fast termination ta must be asserted during s1. data is made available by the external device and is sampled on the rising edge of clkout with ta asserted. s2 read/write (skipped fast termination) high ts is negated on the rising edge of clkout in s2. write the data bus is driven out of high im pedance as data is placed on the bus on the rising edge of clkout. s3 read/write (skipped for fast termination) low the processor waits for ta assertion. if ta is not sampled as asserted before the rising edge of clkout at the end of the first clock cycle, the processor inserts wait states (full clock cycles) until ta is sampled as asserted. read data is made available by the external device on the falling edge of clkout and is sampled on the rising edge of clkout with ta asserted. s4 all high the external device should negate ta . read (including fast-terminati on) the external device can stop driving data after the rising edge of clkout. however data could be driven through the end of s5. s0 s3 s5 s4 s1 s2 basic next cycle wait states read/write fast termination mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 external interface module (eim) 13-6 freescale semiconductor note an external device has at most two clkout cycles after the start of s4 to three-state the data bus. this applies to basic read cycles, fast termination cycles, and the last transfer of a burst. 13.4.3 read cycle during a read cycle, the device receives data from memory or from a peripheral device. figure 13-5 is a read cycle flowchart. figure 13-5. read cycle flowchart the read cycle timing diagram is shown in figure 13-6 . note in the following timing diagrams, ta waveforms apply for chip selects programmed to enable either inte rnal or external termination. ta assertion should look the same in either case. s5 s5 low cs , bs , and oe are negated on the clkout fal ling edge of s5. the processor stops driving address lines and r/w on the rising edge of clkout, terminating the read or write cycle. at the same time, the processor negates tip , and siz[1:0] on the rising edge of clkout. note that the rising edge of clkout may be the start of s0 for the next access cycle. read the external device stops driving data between s4 and s5. write the data bus returns to high impedance on the rising edge of clkout. the rising edge of clkout may be the start of s0 for the next access. table 13-3. bus cycle states (continued) state cycle clkout description external device 1. set r/w to read 2. place address on a[31:0] 3. assert tip , and siz[1:0] 4. assert ts 5. negate ts 1. decode address and select the appropriate slave device. 2. drive data on d[31:0] 3. assert ta 1. sample ta low and latch data 1. negate ta . 2. stop driving d[31:0] 1. start next cycle coldfire processor mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 external interface module (eim) freescale semiconductor 13-7 figure 13-6. basic read bus cycle note the following characteristics of a basic read: ? in s3, data is made available by the external device on the falling edge of clkout and is sampled on the rising edge of clkout with ta asserted. ? in s4, the external device can stop driving data after the rising edge of clkout. however data could be driven up to s5. ? for a read cycle, the external device stops driving data between s4 and s5. states are described in table 13-3 . 13.4.4 write cycle during a write cycle, the processor sends data to th e memory or to a periphera l device. the write cycle flowchart is shown in figure 13-7 . figure 13-7. write cycle flowchart r/w tip ts d[31:0] ta read s0 s1 s2 s3 s4 s5 clkout cs n , bs n , oe a[31:0], siz[1:0] external device 1. set r/w to write 2. place address on a[31:0] 3. assert tip and siz[1:0] 4. assert ts 5. place data on d[31:0] 6. negate ts 1. decode address 2. store data on d[31:0] 3. assert ta 1. sample ta low 2. stop driving data from d[31:0] 1. negate ta 1. start next cycle coldfire processor mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 external interface module (eim) 13-8 freescale semiconductor the write cycle timing diagram is shown in figure 13-8 . figure 13-8. basic write bus cycle table 13-3 describes the six states of a basic write cycle. 13.4.5 fast termination cycles two clock cycle transfers are supported on the external bus. in most cases, this is impracti cal to use in a system because the terminati on must take place in the sa me half-clock during which ts is asserted. as this is atypical, it is not referred to as the zero-wait-state case but is called the fast-termination case. fast termination cycles occur when the ex ternal device or memory asserts ta less than one clock after ts is asserted. this means that the processor samples ta on the rising edge of th e second cycle of the bus transfer. figure 13-9 shows a read cycle with fast termination. note that fast term ination cannot be used with internal termination. figure 13-9. read cycle with fast termination figure 13-10 shows a write cycle wi th fast termination. r/w tip ts d[31:0] ta s0 s1 s2 s3 s4 s5 write clkout cs n , bs n a[31:0], siz[1:0] r/w tip ts d[31:0] ta s0 s1 s4 s5 read clkout cs n , bs n , oe a[31:0], siz[1:0] mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 external interface module (eim) freescale semiconductor 13-9 figure 13-10. write cycle with fast termination 13.4.6 back-to-back bus cycles the processor runs back-to-back bus cycles whenever possible. for example, when a longword read is started on a word-size bus, the processor performs two back-to-back word r ead accesses. back-to-back accesses are distinguished by th e continuous assertion of tip throughout the cycle. figure 13-11 shows a read back-to-back with a write. figure 13-11. back-to-back bus cycles basic read and write cycles are used to show a back-to-back cycle, but there is no restri ction as to the type of operations to be placed back to back. the initiation of a back-to-b ack cycle is not user definable. r/w tip ts cs n , bs n d[31:0] ta s0 s1 s4 s5 write clkout a[31:0], siz[1:0] r/w tip ts cs n , bs n d[31:0] ta read s0 s1 s2 s3 s4 s5 s0 s1 s2 s3 s4 s5 write oe clkout a[31:0], siz[1:0] mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 external interface module (eim) 13-10 freescale semiconductor 13.4.7 burst cycles the processor can be programme d to initiate burst cycles if its transf er size exceeds the size of the port it is transferring to. for exam ple, a word transfer to an 8-bit port would take a 2-byte burst cycle. a line transfer to a 32-bit port would ta ke a 4-longword burst cycle. the external bus can support 2-1- 1-1 burst cycles to maximize cache performa nce and optimize dma transfers. a user can add wait stat es by delaying termination of the cycle. the initiation of a burst cycle is encoded on the size pins. for burst transfers to smaller port sizes, si z[1:0] indicates the size of the entire transfer. for example, if the proces sor writes a longword to an 8-bit por t, siz[1:0] = 00 for the first byte transfer and does not change. the cscrs can be used to enable bursting for reads, writes, or both. processor memory space can be declared burst-inhibited fo r reads and writes by clea ring the appropriate cscr n [bstr,bstw]. a line access to a burst-inhibited region first accesses the processor bus en coded as a line access. the siz[1:0] encoding does not exceed the programmed port size. the address changes if internal termination is used but does not change if external termination is used, as shown in figure 13-12 and figure 13-13 . 13.4.7.1 line transfers a line is a 16-byte-aligne d, 16-byte value. despite the alignment, a line access may not begin on the aligned address; therefore, the bus interface supports line transf ers on multiple address boundaries. table 13-4 shows allowable patterns for line accesses. 13.4.7.2 line read bus cycles figure 13-12 and figure 13-13 show a line access read with zero wait states. the access starts like a basic read bus cycle with the first data transfer sampled on the rising edge of s4, but the next pipelined burst data is sampled a cycle later on the rising edge of s6. each subsequent pipelined data burst is single cycle until the last one, which can be held for up to tw o clkout cycles after ta is asserted. note that cs n are asserted throughout the burst transfer. this exampl e shows the timing for exte rnal termination, which differs from the internal termination example in figure 13-13 only in that the addr ess lines change only at the beginning (assertion of ts and tip ) and end (negation of tip ) of the transfer. table 13-4. allowable line access patterns a[3:2] longword accesses 00 0?4?8?c 01 4?8?c?0 10 8?c?0?4 11 c?0?4?8 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 external interface module (eim) freescale semiconductor 13-11 figure 13-12. line read burst (2-1-1-1), external termination figure 13-13 shows timing when internal termination is used. figure 13-13. line read burst (2-1-1-1), internal termination figure 13-14 shows a line access re ad with one wait stat e programmed in cscr n to give the peripheral or memory more time to return read data. this figur e follows the same execution as a zero-wait state read burst with the exception of an added wait state. r/w tip ts cs n , bs n , oe d[31:0] ta read read s0 s1 s2 s3 s4 s5 s10 s9s8s7 s6 s11 s12 s13 read read clkout a[31:0], siz[1:0] r/w tip ts cs n , bs n , oe d[31:0] ta read read s0 s1 s2 s3 s4 s5 s10 s9s8s7 s6 s11 s12 s13 read read clkout a[31:0] a[31:0], siz[1:0] mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 external interface module (eim) 13-12 freescale semiconductor . figure 13-14. line read burst (3-2-2-2), external termination figure 13-15 shows a burst-inhibited line read access with fast termination. the external device executes a basic read cycle while de termining that a line is being transf erred. the external device uses fast termination for subs equent transfers. figure 13-15. line read burst-inhibited, fast termination, external termination 13.4.7.3 line write bus cycles figure 13-16 shows a line access write with zero wait states. it begins like a basic write bus cycle with data driven one clock after ts . the next pipelined burst da ta is driven a cycle after the write data is registered (on the rising edge of s6). each subsequent burst ta kes a single cycle. note that as with the line read example in figure 13-12 , cs n remain asserted throughout the burst transfer. this example shows the behavior of the address lines for both internal a nd external termination. note that when external termination is used, the addre ss lines change with siz[1:0]. r/w tip ts cs n , bs n , oe d[31:0] ta read s0 s1 s2 s3 s4 s5 s10 s9s8 s7 s6 s11 s12 s13 ws ws ws ws read read read clkout a[31:0], siz[1:0] a[31:0] r/w tip siz[1:0] ts d[31:0] ta line longword basic fast fast fast a[3:2] = 00 a[3:2] = 01 a[3:2] = 10 a[3:2] = 11 s0 s1 s2 s3 s4 s5 s0 s1 s4 s5 s0 s1 s4 s5 s0 s1 s4 s5 s7s6 read read read read clkout cs n , bs n , oe mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 external interface module (eim) freescale semiconductor 13-13 figure 13-16. line write burst (2-1-1-1), internal/external termination figure 13-17 shows a line burst write with one wait-state insertion. figure 13-17. line write burst (3-2-2-2) with one wait state figure 13-18 shows a burst-inhibited line write. the external device executes a basic write cycle while determining that a line is being transferred. the external device uses fast termination to end each subsequent transfer. a[31:0] siz[1:0] ts cs n , oe , bs n d[31:0] ta write write write write s0 s1 s2 s3 s4 s5 s10 s9s8s7s6 s11 clkout a[31:0] internal termination external termination r/w , tip a[31:0] r/w , tip ts cs n , oe , bs n d[31:0] ta write write write write s0 s1 s2 s3 s4 s5 s10 s9s8 s7s6 s11 ws ws ws ws clkout siz[1:0] mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 external interface module (eim) 13-14 freescale semiconductor figure 13-18. line write burst-inhibited 13.5 misaligned operands because operands can reside at a ny byte boundary, unlike opcodes, they are allowed to be misaligned. a byte operand is properly aligned at any address, a wo rd operand is misaligned at an odd address, and a longword is misaligned at an addre ss not a multiple of f our. although the processor enforces no alignment restrictions for data operands (inc luding program counter (pc) relati ve data addressi ng), additional bus cycles are required fo r misaligned operands. instruction words and extension words (opcodes) mu st reside on word boundaries . attempting to prefetch a misaligned instruction word causes an address error exception. the processor converts misaligned, cache-inhibite d operand accesses to mult iple aligned accesses. figure 13-19 shows the transfer of a l ongword operand from a byte addr ess to a 32-bit port. in this example, siz[1:0] specify a byte tr ansfer and a byte offset of 0x1. the slave device supplies the byte and acknowledges the data transfer. when the processor starts the second cycle, siz[1:0] specify a word transfer with a byte offset of 0x2. the next two bytes are transferred in this cycle. in the third cycle, byte 3 is transferred. the byte offset is now 0x0, the port s upplies the final byte, and the operation is complete. figure 13-19. example of a misaligned longword transfer (32-bit port) if an operand is cacheable and is misaligned across a cache- line boundary, both lines are loaded into the cache. the example in figure 13-20 differs from that in figure 13-19 in that the operand is word-sized and the transfer takes only two bus cycles. a[31:0] r/w , tip siz[1:0] ts d[31:0] ta line longword basic fast fast fast a[3:2] = 00 a[3:2] = 01 a[3:2] = 10 a[3:2] = 11 write write write write s0 s1 s2 s3 s4 s5 s0 s1 s4 s5 s0 s1 s4 s5 s0 s1 s4 s5 clkout cs n oe , bs n transfer 1 transfer 2 transfer 3 ? ? byte 3 byte 0 ? ? ? byte 1 ? ? byte 2 ? 31 24 23 16 15 8 7 0 001 010 100 a[2:0] mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 external interface module (eim) freescale semiconductor 13-15 figure 13-20. example of a misaligned word transfer (32-bit port) transfer 1 transfer 2 ? byte 1 ? ? ? ? byte 0 ? 31 24 23 16 15 8 7 0 001 100 a[2:0] mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 external interface module (eim) 13-16 freescale semiconductor mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor 14-1 chapter 14 signal descriptions this chapter describes the processor? s external signals. it includes an alphabetical listing of signals that characterizes each signal as an input or output, defines its state at reset, and id entifies whether a pull-up resistor should be used. chapter 13, ?external interface module (eim) ,? describes how these signals interact. note the terms ?assertion? and ?negation? are used to avoid confusion when dealing with a mixture of active-lo w and active-high signals. the term ?asserted? indicates that a signal is act ive, independent of the voltage level. the term ?negated? indicates that a signal is inactive. active-low signals, such as sras and ta , are indicated with an overbar. 14.1 overview figure 14-1 shows the block diagram with the signal interface. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 signal descriptions 14-2 freescale semiconductor figure 14-1. mcf5282 block diagram with signal interfaces tdo/dso tdi/dsi tms/ bkpt tclk interface chip uart1 serial i/o extal dtin[3:0] dtout[3:0] ta r/ w siz[1:0] d[31:0] a[23:0] jtag port selects external utxd0 urxd0 urts0 ucts0 utxd1 urxd1 urts1 ucts1 dramw 2 24 32 bs [3:0] cs [6:0] 7 4 2 tea trst /dsclk test 4 4 te s t controller oe sras scas scke ts 4 pst[3:0] 4 tip i 2 c module scl sda uart2 serial i/o dma timer modules dram controller ddata[3:0] clock module chip configuration reset controller power rcon clkmod0 clkmod1 rsti rsto (pll) edgeport interrupt controller 0 interrupt controller 1 irq [7:1] fec uart0 serial i/o dma controller watchdog timer general purpose timer a general purpose timer b qspi flexcan qadc pit timers (pit0? jtag_en clkout xtal etxclk etxen etxdo ecol erxclk erxdv erxd0 ecrs etxd[3:1] etxer erxd[3:1] erxer emdio emdc utxd2 urxd2 (dtim0? dtim3) vrefh vrefl an0/anw an1/anx an2/any an3/anz an52/ma0 an53/ma1 an55/trig1 an56/trig2 synca gpta[3:0] 4 gptb[3:0] 4 syncb qspi_din qspi_dout qspi_clk qspi_cs[3:0] cantx canrx management module ports module sdram_cs [1:0] pit3) internal bus arbiter system control module (scm) vddf vstby not present and mcf5216 on mcf5214 note: coldfire v2 core emac 2-kbyte d-cache/i-cache debug module div flash module 64k sram note: not present on mcf5280 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 signal descriptions freescale semiconductor 14-3 table 14-1 lists the external signals grouped by functionality. note the primary functionality of a pin is not necessarily its de fault functionality. pins that are muxed with gpio will default to their gpio functionality. table 14-1. mcf5282 signal description signal name abbreviation function i/o page external memory interface address a[23:0] define the address of external byte, word, longword, and 16-byte burst accesses. i/o 14-19 data d[31:0] data bus. provide the general purpose data path between the mcu and all other devices. i/o 14-19 byte strobes bs [3:0] define the byte lane of data on the data bus. i/o 14-19 output enable oe indicates when an external device can drive data on the bus. o 14-19 transfer acknowledge ta indicates that the external data transfer is complete and should be asserted for one clock. i 14-19 transfer error acknowledge tea indicates that an error condition exists for the bus transfer. i 14-20 read/write r/w indicates the direction of the data transfer on the bus. i/o 14-20 transfer size siz[1:0] specify the data access size of the current external bus reference. o 14-20 transfer start ts asserted during the first clkout cycle of a transfer when address and attributes are valid. o 14-20 transfer in progress tip asserted to indicate that a bus transfer is in progress. negated during idle bus cycles. o 14-21 chip selects cs [6:0] programmed for a base address location and for masking addresses, port size and burst capability indication, wait state generation, and internal/external termination. o 14-21 sdram controller signals sdram row address strobe sras sdram synchronous row address strobe. o 14-21 sdram column address strobe scas sdram synchronous column address strobe. o 14-21 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 signal descriptions 14-4 freescale semiconductor sdram write enable dramw asserted to signify that a dram write cycle is underway. negated to indicate a read cycle. o 14-21 sdram bank selects sdram_cs [1:0] interface to the chip-select lines of the sdrams within a memory block. o 14-21 sdram clock enable scke sdram clock enable. o 14-22 clock and reset signals reset in rsti asserted to enter reset exception processing. i 14-22 reset out rsto automatically asserted with rsti . negation indicates that the pll has regained its lock. o 14-22 extal extal driven by an external clock except when used as a connection to the external crystal. i 14-22 xtal xtal internal oscillator connection to the external crystal. o 14-22 clock output clkout reflects the system clock. o 14-22 chip configuration module clock mode clkmod[1:0] clock mode select i 14-22 reset configuration rcon reset configuration select i 14-22 external interrupt signals external interrupts irq [7:1] external interrupt sources. i 14-23 ethernet module signals (not available on mcf5214 and mcf5216) management data emdio transfers control information between the external phy and the media access controller. i/o 14-23 management data clock emdc provides a timing reference to the phy for data transfers on the emdio signal. o 14-23 transmit clock etxclk provides a timing reference for etxen, etxd[3:0], and etxer. i 14-23 transmit enable etxen indicates when valid nibbles are present on the mii. o 14-23 transmit data 0 etxd0 serial output ethernet data. o 14-23 collision ecol asserted to indicate a collision. i 14-24 receive clock erxclk provides a timing reference for erxdv, erxd[3:0], and erxer. i 14-24 table 14-1. mcf5282 signal description (continued) signal name abbreviation function i/o page mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 signal descriptions freescale semiconductor 14-5 receive data valid erxdv asserted to indicate that the phy has valid nibbles present on the mii. i 14-24 receive data 0 erxd0 ethernet input data transferred from the phy to the media access controller (when erxdv is asserted). i 14-24 carrier receive sense ecrs asserted to indicate that the transmit or receive medium is not idle. i 14-24 transmit data etxd[3:1] contain the serial output ethernet data. o 14-24 transmit error etxer asserted (for one or more e_txclks while etxen is also asserted) to cause the phy to send one or more illegal symbols. o 14-24 receive data erxd[3:1] contain the ethernet input data transferred from the phy to the media access controller (when erxdv is asserted in mii mode). i 14-24 receive error erxer indicates (when asserted with erxdv) that the phy has detected an error in the current frame. i 14-25 queued serial peripheral interface (qspi) signals qspi synchronous serial data output qspi_dout provides serial data from the qspi. o 14-25 qspi synchronous serial data input qspi_din provides serial data to the qspi. i 14-25 qspi serial clock qspi_clk provides the serial clock from the qspi. o 14-25 qspi chip selects qspi_cs[3:0] provide qspi peripheral chip selects. o 14-25 flexcan signals flexcan transmit cantx controller area network transmit data. o 14-25 flexcan transmit canrx controller area network transmit data. i 14-25 i 2 c signals serial clock scl clock signal for the i 2 c interface. i/o 14-26 serial data sda data input/output for the i 2 c interface. i/o 14-26 uart signals transmit serial data output utxd[2:0] transmitter serial data outputs. o 14-26 receive serial data input urxd[2:0] receiver serial data inputs. i 14-26 table 14-1. mcf5282 signal description (continued) signal name abbreviation function i/o page mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 signal descriptions 14-6 freescale semiconductor clear-to-send ucts [1:0] signals uart that it can begin data transmission. i 14-26 request to send urts [1:0] automatic uart request to send outputs. o 14-27 general purpose timer signals gpta gpta[3:0] provide the external interface to the timer a functions. i/o 14-27 gptb gptb[3:0] provide the external interface to the timer b functions. i/o 14-27 external clock input synca/syncb clear the timer?s clock, providing a means of synchronization to externally clocked or timed events. i 14-27 dma timer signals dma timer input dtin[3:0] clock t he event counter or provide a trigger to timer value capture logic. i/o 14-27 dma timer output dtout[3:0] pulse or toggle on timer events. i/o 14-27 analog-to-digital con verter (qadc) signals qadc analog input an[0:3]/an[ w:z] direct analog input an n , or multiplexed input an x. i 14-28 qadc analog input an[52:53]/ma[ 0:1] direct analog input an n , or multiplexed output ma n . ma n selects the output of the external multiplexer. i/o 14-29 qadc analog input an[55:56]/ trig[1:2] direct analog input an n , or input trig n . trig n causes one of the two queues to execute. i 14-29 debug support signals jtag_en jtag_en selects between multiplexed debug module and jtag signals at reset. i 14-29 development serial clock/test reset dsclk/trst development serial clock for the serial interface to debug module (dsclk). asynchronously resets the internal jtag controller to the test logic reset state (trst ). i 14-30 breakpoint/ test mode select bkpt /tms signals a hardware breakpoint in debug mode (bkpt ). provides information that determines jtag test operation mode (tms). i 14-30 table 14-1. mcf5282 signal description (continued) signal name abbreviation function i/o page mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 signal descriptions freescale semiconductor 14-7 table 14-2 lists signals in alphabetical order by abbreviated name. development serial input/test data dsi/tdi provides single-bit communication for debug module commands (dsi). provides serial data port for loading jtag boundary scan, bypass, and instruction registers (tdi). i 14-30 development serial output/test data dso/tdo provides single-bit communication for debug module responses (dso). provides serial data port for outputting jtag logic data (tdo). o 14-30 test clock tclk jtag test logic clock. i 14-30 debug data ddata[3:0] display captured processor addresses, data, and breakpoint status. o 14-31 processor status outputs pst[3:0] indicate core status. o 14-31 test signals test test reserved, should be connected to vss. i 14-31 power and reference signals qadc analog reference vrh, vrl high (vrh) and low (vrl) reference potentials for the analog converter. ground 14-32 qadc analog supply vdda, vssa isolate the qadc analog circuitry from digital power supply noise. i 14-32 pll analog supply vddpll, vsspll isolate the pll analog circuitry from digital power supply noise. i 14-32 qadc positive supply vddh supplies positive power to the esd structures in the qadc pads. i 14-32 flash erase/program power vpp used for flash stress testing. i 14-32 flash array power and ground vddf, vssf supply power and ground to flash array. i 14-32 standby power vstby provides standby voltage to ram array if vdd is lost. i 14-32 positive supply vdd supplies positive power to the core logic and i/o pads. i 14-32 ground vss negative supply. 14-32 table 14-1. mcf5282 signal description (continued) signal name abbreviation function i/o page mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 signal descriptions 14-8 freescale semiconductor table 14-2. mcf5282 alphabetical signal index abbreviation function i/o a[23:0] define the address of external byte, word, longword, and 16-byte burst accesses. i/o an[0:3]/an[w:z] direct analog input an n , or multiplexed input an x.i an[52:53]/ma[0:1] direct analog input an n , or multiplexed output ma n. ma n selects the output of the external multiplexer. i/o an[55:56]/ trig[1:2] direct analog input an n , or input trig n . trig n causes one of the two queues to execute. i breakpoint/ test mode select signals a hardware breakpoint in debug mode (bkpt ). provides information that determines jtag test operation mode (tms). i bs [3:0] define the byte lane of data on the data bus. i/o canrx controller area network transmit data. i cantx controller area network transmit data. o clkmod[1:0] clock mode select i clkout reflects the system clock. o cs [6:0] programmed for a base address location and for masking addresses, port size and burst capability indication, wait state generation, and internal/external termination. o d[31:0] data bus. provide the general purpose data path between the mcu and all other devices. i/o ddata[3:0] display captured processor addresses, data, and breakpoint status. o dso/tdo provides single-bit communication for debug module responses (dso). provides serial data port for outputting jtag logic data (tdo). o dsi/tdi development serial clock for the serial interface to debug module (dsclk). asynchronously resets the internal jtag controller to the test logic reset state (trst ). i dsclk/trst provides single-bit communication for debug module commands (dsi). provides serial data port for loading jtag boundary scan, bypass, and instruction registers (tdi). i dramw asserted to signify that a dram write cycle is underway. negated to indicate a read cycle. o dtin[3:0] clock the event counter or provide a trigger to timer value capture logic. i/o dtout[3:0] pulse or toggle on timer events. i/o ecol asserted to indicate a collision. note: not available on mcf5214 and mcf5216 i ecrs asserted to indicate that the transmit or receive medium is not idle. note: not available on mcf5214 and mcf5216 i mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 signal descriptions freescale semiconductor 14-9 emdc provides a timing reference to the phy for data transfers on the emdio signal. note: not available on mcf5214 and mcf5216 o emdio transfers control information between the external phy and the media access controller. note: not available on mcf5214 and mcf5216 i/o erxclk provides a timing refer ence for erxdv, erxd[3:0], and erxer. note: not available on mcf5214 and mcf5216 i erxd[3:1] contain the ethernet input data transferred from the phy to the media access controller (when erxdv is asserted in mii mode). note: not available on mcf5214 and mcf5216 i erxd0 ethernet input data transfe rred from the phy to the media access controller (when erxdv is asserted). note: not available on mcf5214 and mcf5216 i erxdv asserted to indicate that the phy has valid nibbles present on the mii. note: not available on mcf5214 and mcf5216 i erxer indicates (when asserted with erxdv) that the phy has detected an error in the current frame. note: not available on mcf5214 and mcf5216 i etxclk provides a timing referenc e for etxen, etxd [3:0], and etxer. note: not available on mcf5214 and mcf5216 i etxd[3:1] contain the serial output ethernet data. note: not available on mcf5214 and mcf5216 o etxd0 serial output ethernet data. note: not available on mcf5214 and mcf5216 o etxen indicates when valid nibbles are present on the mii. note: not available on mcf5214 and mcf5216 o etxer asserted (for one or more e_txclks while etxen is also asserted) to cause the phy to send one or more illegal symbols. note: not available on mcf5214 and mcf5216 o extal driven by an external clock except when used as a connection to the external crystal. i vddf, vssf supply power and ground to flash array. i vpp used for flash stress testing. i gpta[3:0] provide the external inte rface to the timer a functions. i/o gptb[3:0] provide the external inte rface to the timer b functions. i/o ground negative supply. irq [7:1] external interrupt sources. i table 14-2. mcf5282 alphabetical signal index (continued) abbreviation function i/o mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 signal descriptions 14-10 freescale semiconductor jtag_en selects between multiplexed debug module and jtag signals at reset. i oe indicates when an external device can drive data on the bus. o vddpll isolate the pll analog circuitry from digital power supply noise. i vdd supplies positive power to the core logic and i/o pads. i pst[3:0] indicate core status. o vrh, vrl high (vrh) and low (vrl) reference potentials for the analog converter. i vdda, vssa isolate the qadc analog circuitry from digital power supply noise. i qadc analog supply supplies positive power to the esd structures in the qadc pads. i qspi_clk provides the serial clock from the qspi. o qspi_cs[3:0] provide qspi pe ripheral chip selects. o qspi_din provides serial data to the qspi. i qspi_dout provides serial data from the qspi. o r/w indicates the direction of the data transfer on the bus. i/o rcon reset configuration select. i rsti asserted to enter reset exception processing. i rsto automatically asserted with rsti . negation indicates that the pll has regained its lock. o scas sdram synchronous column address strobe. o scke sdram clock enable. o scl clock signal for the i 2 c interface. i/o sda data input/output for the i 2 c interface. i/o sdram_cs [1:0] interface to the chip-selec t lines of the sdrams within a memory block. o siz[1:0] specify the data access size of the current external bus reference. o sras sdram synchronous row address strobe. o vstby provides standby voltage to ram array if vdd is lost. i synca/syncb clear the timer?s clock, providing a means of synchronization to externally clocked or timed events. i ta indicates that the external data transfer is complete and should be asserted for one clkout cycle. i tea indicates that an error conditi on exists for the bus transfer. i table 14-2. mcf5282 alphabetical signal index (continued) abbreviation function i/o mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 signal descriptions freescale semiconductor 14-11 test reserved, should be connected to vss. i tck jtag test logic clock. i tip asserted to indicate that a bus transfer is in progress. negated during idle bus cycles. o ts asserted during the first clkout cycle of a transfer when address and attributes are valid. o ucts [1:0] signals uart that it can begin data transmission. i urts [1:0] automatic uart request to send outputs. o urxd[2:0] receiver serial data inputs. i utxd[2:0] transmitter serial data outputs. o xtal internal oscillator connection to the external crystal. o table 14-3. mcf5282 signals and pin numbers sorted by function mapbga pin pin functions description primary i/o internal pull-up 1 primary 2 secondary tertiary reset r11 rsti ? ? reset in iyes p11 rsto ? ? reset out o ? clock t8 extal ? ? external clock/crystal in i ? r8 xtal ? ? crystal drive o ? n7 clkout ? ? clock out o ? chip configuration/mode selection r14 clkmod0 ? ? clock mode select iyes t14 clkmod1 ? ? clock mode select iyes t11 rcon ? ? reset configuration enable iyes h1 d26 pa 2 ? chip mode i/o ? k2 d17 pb1 ? chip mode i/o ? k3 d16 pb0 ? chip mode i/o ? j4 d19 pb3 ? boot device/data port size i/o ? k1 d18 pb2 ? boot device/data port size i/o ? j2 d21 pb5 ? output pad drive strength i/o ? table 14-2. mcf5282 alphabetical signal index (continued) abbreviation function i/o mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 signal descriptions 14-12 freescale semiconductor external memory interface and ports c6:b6:a5 a[23:21] pf[7:5] cs [6:4] address bus o yes c4:b4:a4:b3:a3 a[20:16] pf [4:0] ? address bus o yes a2:b1:b2:c1: c2:c3:d1:d2 a[15:8] pg[7:0] ? address bus o yes d3:d4:e1:e2: e3:e4:f1:f2 a[7:0] ph[7:0] ? address bus o yes f3:g1:g2:g3: g4:h1:h2:h3 d[31:24] pa [ 7 : 0 ] ? data bus i/o ? h4:j1:j2:j3: j4:k1:k2:k3 d[23:16] pb[7:0] ? data bus i/o ? l1:l2:l3:l4: m1:m2:m3:m4 d[15:8] pc[7:0] ? data bus i/o ? n1:n2:n3:p1: n5:t6:r6:p6 d[7:0] pd[7:0] ? data bus i/o ? p14:t15:r15:r16 bs [3:0] pj[7:4] ? byte strobe i/o yes n16 oe pe7 ? output enable i/o ? p16 ta pe6 ? transfer acknowledge i/o ye s p15 tea pe5 ? transfer error acknowledge i/o yes n15 r/w pe4 ? read/write i/o yes n14 siz1 pe3 synca transfer size i/o ye s 3 m16 siz0 pe2 syncb transfer size i/o ye s 4 m15 ts pe1 synca transfer start i/o ye s m14 tip pe0 syncb transfer in progress i/o ye s chip selects l16:l15:l14:l13 cs [3:0] pj[3:0] ? chip selects 3-0 i/o yes c6:b6:a5 a[23:21] pf[7:5] cs [6:4] chip selects 6-4 o yes sdram controller h15 sras psd5 ? sdram row address strobe i/o ? h16 scas psd4 ? sdram column address strobe i/o ? g15 dramw psd3 ? sdram write enable i/o ? h13:g16 sdram_cs [1:0] psd[2:1] ? sdram chip selects i/o ? h14 scke psd0 ? sdram clock enable i/o ? table 14-3. mcf5282 signals and pin numbers sorted by function (continued) mapbga pin pin functions description primary i/o internal pull-up 1 primary 2 secondary tertiary mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 signal descriptions freescale semiconductor 14-13 external interrupts port b15:b16:c14:c15: c16: d14:d15 irq [7:1] pnq[7:1] ? external interrupt request i/o ? ethernet for mcf5280, mcf5281 and mcf5282 only c10 emdio pas5 urxd2 management channel serial data i/o ? b10 emdc pas4 utxd2 management channel clock i/o ? a8 etxclk peh7 ? mac transmit clock i/o ? d6 etxen peh6 ? mac transmit enable i/o ? d7 etxd0 peh5 ? mac transmit data i/o ? b11 ecol peh4 ? mac collision i/o ? a10 erxclk peh3 ? mac receive clock i/o ? c8 erxdv peh2 ? mac receive enable i/o ? d9 erxd0 peh1 ? mac receive data i/o ? a11 ecrs peh0 ? mac carrier sense i/o ? a7:b7:c7 etxd[3:1] pel[7:5] ? mac transmit data i/o ? d10 etxer pel4 ? mac transmit error i/o ? a9:b9:c9 erxd[3:1] pel[3:1] ? mac receive data i/o ? b8 erxer pel0 ? mac receive error i/o ? gpio for mcf5214 and mcf5216 only c10 pas5 urxd2 ? gpio/serial data i/o ? b10 nc ? ? no connect ? ? a8 pel0 ? ? gpio i/o ? d6 nc ? ? no connect ? ? d7 nc ? ? no connect ? ? b11 nc ? ? no connect ? ? a10 pas4 utxd2 ? gpio/serial data i/o ? c8 nc ? ? no connect ? ? d9 nc ? ? no connect ? ? a11 nc ? ? no connect ? ? table 14-3. mcf5282 signals and pin numbers sorted by function (continued) mapbga pin pin functions description primary i/o internal pull-up 1 primary 2 secondary tertiary mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 signal descriptions 14-14 freescale semiconductor a7:b7:c7 pel[7:5] ? ? gpio i/o ? d10 pel4 ? ? gpio i/o ? a9:b9:c9 pel[3:1] ? ? gpio i/o ? b8 nc ? ? no connect ? ? flexcan d16 canrx pas3 urxd2 flexcan receive data i/o ? e13 cantx pas2 utxd2 flexcan transmit data i/o ? i 2 c e14 sda pas1 urxd2 i 2 c serial data i/o ye s 5 e15 scl pas0 utxd2 i 2 c serial clock i/o ye s 6 qspi f13 qspi_dout pqs0 ? qspi data out i/o ? e16 qspi_din pqs1 ? qspi data in i/o ? f14 qspi_clk pqs2 ? qspi clock i/o ? g14:g13:f16:f15 qspi_cs[3:0] pqs[6:3] ? qspi chip select i/o ? uarts r7 urxd1 pua3 ? u1 receive data i/o ? p7 utxd1 pua2 ? u1 transmit data i/o ? n6 urxd0 pua1 ? u0 receive data i/o ? t7 utxd0 pua0 ? u0 transmit data i/o ? d16 canrx pas3 urxd2 u2 receive data i/o ? e13 cantx pas2 utxd2 u2 transmit data i/o ? e14 sda pas1 urxd2 u2 receive data i/o ye s 5 e15 scl pas0 utxd2 u2 transmit data i/o ye s 6 k16 dtin3 ptc3 urts1 / urts0 u1/u0 request to send i/o ? k15 dtout3 ptc2 urts1 / urts0 u1/u0 request to send i/o ? k14 dtin2 ptc1 ucts1 / ucts0 u1/u0 clear to send i/o ? k13 dtout2 ptc0 ucts1 / ucts0 u1/u0 clear to send i/o ? table 14-3. mcf5282 signals and pin numbers sorted by function (continued) mapbga pin pin functions description primary i/o internal pull-up 1 primary 2 secondary tertiary mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 signal descriptions freescale semiconductor 14-15 j16 dtin1 ptd3 urts1 / urts0 u1/u0 request to send i/o ? j15 dtout1 ptd2 urts1 / urts0 u1/u0 request to send i/o ? j14 dtin0 ptd1 ucts1 / ucts0 u1/u0 clear to send i/o ? j13 dtout0 ptd0 ucts1 / ucts0 u1/u0 clear to send i/o ? note: the below two pins are for the mcf5280, mcf5281, and mcf5282 only. c10 emdio pas5 urxd2 u2 receive data i/o ? b10 emdc pas4 utxd2 u2 transmit data i/o ? note: the below two pins are for the mcf5214 and mcf5216 only. c10 pas5 urxd2 ? u2 receive data i/o ? b10 nc ? ? no connect i/o ? general purpose timers t13:r13:p13:n13 gpta[3:0] pta[3:0] ? timer a ic/oc/pai i/o ye s t12:r12:p12:n12 gptb[3:0] ptb[3:0] ? timer b ic/oc/pai i/o ye s n14 siz1 pe3 synca timer a synchronization input i/o ye s 3 m16 siz0 pe2 syncb timer b synchronization input i/o ye s 4 m15 ts pe1 synca timer a synchronization input i/o ye s m14 tip pe0 syncb timer b synchronization input i/o ye s dma timers k16 dtin3 ptc3 urts1 / urts0 timer 3 in i/o ? k15 dtout3 ptc2 urts1 / urts0 timer 3 out i/o ? k14 dtin2 ptc1 ucts1 / ucts0 timer 2 in i/o ? k13 dtout2 ptc0 ucts1 / ucts0 timer 2 out i/o ? j16 dtin1 ptd3 urts1 / urts0 timer 1 in i/o ? j15 dtout1 ptd2 urts1 / urts0 timer 1 out i/o ? table 14-3. mcf5282 signals and pin numbers sorted by function (continued) mapbga pin pin functions description primary i/o internal pull-up 1 primary 2 secondary tertiary mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 signal descriptions 14-16 freescale semiconductor j14 dtin0 ptd1 ucts1 / ucts0 timer 0 in i/o ? j13 dtout0 ptd0 ucts1 / ucts0 timer 0 out i/o ? queued analog-to-di gital converter (qadc) t3 an0 pqb0 anw analog channel 0 i/o ? r2 an1 pqb1 anx analog channel 1 i/o ? t2 an2 pqb2 any analog channel 2 i/o ? r1 an3 pqb3 anz analog channel 3 i/o ? r4 an52 pqa0 ma0 analog channel 52 i/o ? t4 an53 pqa1 ma1 analog channel 53 i/o ? p3 an55 pqa3 etrig1 analog channel 55 i/o ? r3 an56 pqa4 etrig2 analog channel 56 i/o ? p4 vrh ? ? high analog reference i ? t5 vrl ? ? low analog reference i ? debug and jtag test port control r9 jtag_en ? ? jtag enable i ? p9 dsclk trst ? debug clock / tap reset i ye s 7 t9 tclk ? ? tap clock i ye s 7 p10 bkpt tms ? breakpoint/tap test mode select i ye s 7 r10 dsi tdi ? debug data in / tap data in i ye s 7 t10 dso tdo ? debug data out / tap data out o ? c12:d12:a13:b13 ddata[3:0] pdd[7:4] ? debug data i/o ? c13:a14:b14:a15 pst[3:0] pdd[3:0] ? processor status data i/o ? test n10 test ? test mode pin i ? power supplies r5 vdda ? ? analog positive supply i ? p5:t1 vssa ? ? analog ground i ? p2 vddh ? ? esd positive supply i ? n8 vddpll ? ? pll positive supply i ? table 14-3. mcf5282 signals and pin numbers sorted by function (continued) mapbga pin pin functions description primary i/o internal pull-up 1 primary 2 secondary tertiary mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 signal descriptions freescale semiconductor 14-17 14.1.1 single-chip mode in single-chip mode, signals default to gpio inputs after a system reset. table 14-4 is a listing of signals that do not default to a gpio function. p8 vsspll ? ? pll ground i ? a6:c11 vpp ? ? flash (stress) programming voltage i ? a12:c5:d5:d11 vddf ? ? flash positive supply i ? b5:b12: vssf ? ? flash module ground i ? n11 vstby ? ? standby power i ? e6-e11:f5:f7-f10: f12:g5:g6:g11: g12:h5:h6:h11: h12:j5:j6:j11:j12: k5:k6:k11:k12:l5: l7-l10:l12: m6-m11 vdd ? ? positive supply i ? a1:a16:e5:e12:f6: f11:g7-g10:h7-h10 :j7-j10:k7-k10:l6: l11:m5:m12:t16 vss ? ? ground i ? 1 pull-ups are not active when gpio functions are selected for the pins. 2 the primary functionality of a pin is not necessarily its default functionality. pins that have gpio functionality will default to gpio inputs. 3 pull-up is active only with the synca function. 4 pull-up is active only with the syncb function. 5 pull-up is active only with the sda function. 6 pull-up is active only with scl function. 7 pull-up is active when jtag_en is driven high. table 14-4. pin reset states at reset (single-chip mode) signal reset i/o clock and reset signals rsti ?i rsto low o extal ? i xtal xtal o clkout clkout o table 14-3. mcf5282 signals and pin numbers sorted by function (continued) mapbga pin pin functions description primary i/o internal pull-up 1 primary 2 secondary tertiary mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 signal descriptions 14-18 freescale semiconductor 14.1.2 external boot mode when booting from external memory, th e address bus, data bus, and bus cont rol signals will default to their bus functionalities as shown in table 14-5 . as in single-chip mode, the signals listed in table 14-4 will operate as described above. all other signals will default to gpio inputs. 14.2 external signals the following sections describe th e external signals on the device. 14.2.1 external interface module (eim) signals these signals are used for doing tr ansactions on the external bus. debug support signals jtag_en ? i dsclk/trst ?i bkpt /tms ? i dsi/tdi ? i dso/tdo high o tclk ? i ddata[3:0] ddata{3:0] o pst[3:0] pst[3:0] o table 14-5. default signal functions after system reset (external boot mode) signal reset i/o a[23:0] a[23:0] o d[31:0] ? i/o bs [3:0] high o oe high o ta ?i tea ?i r/w high o siz[1:0] high o ts high o tip high o cs [6:0] high o table 14-4. pin reset states at reset (single-chip mode) (continued) signal reset i/o mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 signal descriptions freescale semiconductor 14-19 14.2.1.1 address bus (a[23:0]) the 24 dedicated address signals, a[ 23:0], define the address of ex ternal byte, word, longword and 16-byte burst accesses. these three- state outputs are the 24 ls bs of the internal 32-bit address bus. the address lines also serve as the sdram addressing, providing mu ltiplexed row and column address signals. these pins are configured for gpio ports f, g and h in single-chip mode. the a[23:21] pins can also be configured for cs [6:4]. 14.2.1.2 data bus (d[31:0]) these three-state bidirectional si gnals provide the general purpose da ta path between the mcu and all other devices. data is sampled by the processor on the rising clkout edge. th e data bus port width and wait states are initially defined fo r the external boot chip select, cs0 , by d[19:18] during chip configuration at reset. the port width for each chip select and sdram bank is programmable. the data bus uses a default configur ation if none of the chip selects or sdram bank matc h the address decode. the default configuration is a 32-bit port with external termination a nd burst-inhibited transfers. the data bus can transfer byte, word, or longw ord data widths. all 32 data bus signals are driven during writes, regardless of port width and operand size. d[26:24, 21, 19:16] are used during chip configuration as inputs to configure the functions as described in chapter 27, ?chip confi guration module (ccm).? these pins are configured as gpio ports a, b, c and d in single-chip mode. 14.2.1.3 byte strobes (bs [3:0]) the byte strobes (bs [3:0]) define the byte lane of data on the data bus. during ac cesses, these outputs act as the byte select signals th at indicate valid data is to be latched or driven onto a byte lane when driven low. for sram or fl ash devices, the bs [3:0] outputs should be connect ed to individual byte strobe signals. for sdram devices, the bs [3:0] should be connected to individual sdram dqm signals. note that most sdrams associate dqm3 with the msb, in which case bs3 is connected to the sdram's dqm3 input. these pins can also be c onfigured as gpio pj[7:4]. 14.2.1.4 output enable (oe ) this output signal indicates when an external devi ce can drive data during external read cycles. this pin can also be configured as gpio pe7. 14.2.1.5 transfer acknowledge (ta ) this signal indicates that the external data transfer is complete. during a read cycle, when the processor recognizes ta , it latches the data and then terminates the bus cycle. during a write cycle, when the processor recognizes ta , the bus cycle is terminated. if all bus cycles support fa st termination, ta can be tied low. this pin can also be configured as gpio pe6. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 signal descriptions 14-20 freescale semiconductor 14.2.1.6 transfer error acknowledge (tea ) this signal indicates an error conditio n exists for the bus tran sfer. the bus cycle is terminated and the cpu begins execution of the access error exception. this signal is an input in master mode. this pin can also be configured as gpio pe5. 14.2.1.7 read/write (r/w ) this output signal indicates the direction of the data tr ansfer on the bus. a logic 1 indicates a read from a slave device and a logic 0 indicat es a write to a slave device. this pin can also be configured as gpio pe4. 14.2.1.8 transfer size(siz[1:0]) when the device is in normal mode, static bus sizing lets the programme r change data bus width between 8, 16, and 32 bits for each chip sel ect. the siz[1:0] outputs specify the data access size of the current external bus reference as shown in table 14-6 . note that for misaligned transfers, siz[1:0] indicate the si ze of each transfer. for example, if a longword access occurs at a misali gned offset of 0x1, a byte is transferred first (siz[1:0] = 01), a word is next transferred at offset 0x2 (siz[1:0] = 10), then the final byte is transferred at offset 0x4 (siz[1:0] = 01). for aligned transfers larger than the port size, siz[1:0] behaves as follows: ? if bursting is used, siz[1:0] st ays at the size of transfer. ? if bursting is inhibited, siz[1:0] first shows the size of the tr ansfer and then s hows the port size. for burst-inhibited transfers, siz[1:0] changes with each ts assertion to reflect the next transfer size. for transfers to port sizes smaller than th e transfer size, siz[1:0] indicates the size of th e entire transfer on the first access and the size of the curren t port transfer on subsequent transf ers. for example, for a longword write to an 8-bit port, siz[1:0] = 00 for the first byte transfer and 01 for the next three. these pins can also be configured as gpio pe[3:2] or synca, syncb. 14.2.1.9 transfer start (ts ) the device asserts ts during the first clkout cycle of a tran sfer when address and attributes (tip , r/w , and siz[1:0]) are valid. ts is negated in the following clkout cycle. this pin can also be configured as gpio pe1 or synca. table 14-6. transfer size encoding siz[1:0] transfer size 00 longword 01 byte 10 word 11 16-byte line mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 signal descriptions freescale semiconductor 14-21 14.2.1.10 transfer in progress (tip ) the tip output is asserted indicating a bus transfer is in progress. it is negated during idle bus cycles. note that tip is held asserted on back-to-back cycles. note tip is not asserted during sdram accesses. this pin can also be configured as gpio pe0 or syncb. 14.2.1.11 chip selects (cs [6:0]) each chip select can be programmed for a base address location and for mask ing addresses, port size and burst-capability indication, wa it-state generation, and inte rnal/external termination. reset clears all chip select programming; cs 0 is the only chip select in itialized out of reset. cs 0 is also unique because it can function at reset as a global chip select that allows boot rom to be selected at any defined address space. the port size for boot cs 0 is set during chip configur ation by the levels on d[19:18] on the rising edge of rsti , as described in chapter 27, ?chip configuration module (ccm) .? the chip-select implementation is described in chapter 12, ?chip select module .? these pins can also be configur ed as a[23:21] and gpio pj[3:0]. 14.2.2 sdram controller signals these signals are used for sdram accesses. 14.2.2.1 sdram row address strobe (sras ) this output is the sdram synchronous row address strobe. this pin is configured as gp io psd5 in single-chip mode. 14.2.2.2 sdram column address strobe (scas ) this output is the sdram sync hronous column address strobe. this pin is configured as gp io psd4 in single-chip mode. 14.2.2.3 sdram write enable (dramw ) the dram write signal (dramw ) is asserted to signi fy that a dram write cycle is underway. a read cycle is indicated by the negation of dramw . this pin is configured as gp io psd3 in single-chip mode. 14.2.2.4 sdram bank selects (sdram_cs [1:0]) these signals interface to the chip-select lines of the sdrams within a memory block. thus, there is one sdram_cs line for each memory block (the proc essor supports two sdram memory blocks). these pins is configured as gpio psd[2:1] in single-chip mode. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 signal descriptions 14-22 freescale semiconductor 14.2.2.5 sdram clock enable (scke) this output is the sdram clock enable. this pin is configured as gp io psd0 in single-chip mode. 14.2.3 clock and reset signals the clock and reset signals configure the device and provide interface signals to the external system. 14.2.3.1 reset in (rsti ) asserting rsti causes the device to enter reset exception processing. when rsti is recognized the address bus, data bus, siz, r/w , as , and ts are three-stated. rsto is asserted auto matically when rsti is asserted. 14.2.3.2 reset out (rsto ) after rsti is asserted, the pll temporarily lo ses its lock, during which time rsto is asserted. when the pll regains its lock, rsto negates again. this signal can be used to reset external devices. 14.2.3.3 extal this input is driven by an external clock except when used as a connection to the external crystal when using the internal oscillator. 14.2.3.4 xtal this output is an internal oscillator connection to the external crystal. 14.2.3.5 clock output (clkout) the internal pll generates clkout. this ou tput reflects the internal system clock. 14.2.4 chip configuration signals 14.2.4.1 rcon if the external rcon signal is asserted, then various chip func tions, including the re set configuration pin functions after reset, are configur ed according to the levels driven onto the external data pins (see section 27.6, ?functional description ?). the internal configuration signals are driven to reflect the levels on the external configur ation pins to allow fo r module configuration. 14.2.4.2 clkmod[1:0] the state of the clkmod[1:0] pins during re set determines the clock mode after reset. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 signal descriptions freescale semiconductor 14-23 14.2.5 external interrupt signals 14.2.5.1 external interrupts (irq [7:1]) these inputs are the extern al interrupt sources. see chapter 11, ?edge port module (eport)? for more information on these interrupt source s and their corresponding registers. these pins are configured as gpio pnq[7:1] in single-chip mode. 14.2.6 ethernet module signals the following signals are used by the ethe rnet module for data and clock signals. note these signals are not availa ble on the mcf5214 and mcf5216. 14.2.6.1 management data (emdio) the bidirectional emdio signal transfers control information between the external phy and the media-access controller. data is synchronous to emdc and applies to mii mode operati on. this signal is an input after reset. when the fe c is operated in 10 mbps 7-wire interface mode, this signal should be connected to vss. this pin can also be configured as gpio pas5 or urxd2. 14.2.6.2 management data clock (emdc) emdc is an output clock which pr ovides a timing reference to the ph y for data transfers on the emdio signal and applies to mii mode operation. this pin can also be configured as gpio pas4 or utxd2. 14.2.6.3 transmit clock (etxclk) this is an input clock which provides a timing reference for etxen, et xd[3:0] and etxer. this pin can also be configured as gpio peh7. 14.2.6.4 transmit enable (etxen) the transmit enable (etxen) output indicates when valid nibbles are present on the mii. this signal is asserted with the first nibble of a preamble and is negated before the first etxclk following the final nibble of the frame. this pin can also be configured as gpio peh6. 14.2.6.5 transmit data 0 (etxd0) etxd0 is the serial output ethernet data and is only valid during the assertion of etxen. this signal is used for 10 mbps ethernet data. this signal is also used for mii m ode data in conjunction with etxd[3:1]. this pin can also be configured as gpio peh5. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 signal descriptions 14-24 freescale semiconductor 14.2.6.6 collision (ecol) the ecol input is asserted upon detect ion of a collision and remains asse rted while the collision persists. this signal is not defined for full-duplex mode. this pin can also be configured as gpio peh4. 14.2.6.7 receive clock (erxclk) the receive clock (erxclk) input provides a timing reference for er xdv, erxd[3:0], and erxer. this pin can also be configured as gpio peh3. 14.2.6.8 receive data valid (erxdv) asserting the receive data valid (e rxdv) input indicates that the phy has valid nibbles present on the mii. erxdv should remain assert ed from the first recovered nibbl e of the frame through to the last nibble. assertion of erxdv mu st start no later than the sfd and exclude any eof. this pin can also be configured as gpio peh2. 14.2.6.9 receive data 0 (erxd0) erxd0 is the ethernet input data transferred from the phy to th e media-access contro ller when erxdv is asserted. this signal is used for 10 mbps ethernet data. this signal is also used for mii mode ethernet data in conjunction with erxd[3:1]. this pin can also be configured as gpio peh1. 14.2.6.10 carrier r eceive sense (ecrs) ecrs is an input signal which, when asserted, signals that transmit or receive medium is not idle, and applies to mii mode operation. this pin can also be configured as gpio peh0. 14.2.6.11 transmit da ta 1?3 (etxd[3:1]) these pins contain the serial output ethernet data and are valid only duri ng assertion of etxen in mii mode. these pins can also be conf igured as gpio pel[7:5]. 14.2.6.12 transmit error (etxer) when the etxer output is asserted for one or more e_txclks while etxen is also asserted, the phy sends one or more illegal symbol s. etxer has no effect at 10 mbps or when etxen is negated, and applies to mii mode operation. these pins can also be c onfigured as gpio pel4. 14.2.6.13 receive data 1?3 (erxd[3:1]) these pins contain the ethernet i nput data transferred fro m the phy to the media-access controller when erxdv is asserted in mii mode operation. these pins can also be conf igured as gpio pel[3:1]. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 signal descriptions freescale semiconductor 14-25 14.2.6.14 receive error (erxer) erxer is an input signal which when asserted along with erxdv signals that the phy has detected an error in the current frame. when erxdv is not asserted erxer has no effect, and applies to mii mode operation. these pins can also be c onfigured as gpio pel0. 14.2.7 queued serial peripheral interface (qspi) signals 14.2.7.1 qspi synchronous se rial output (qspi_dout) the qspi_dout output provides the serial data from the qspi and ca n be programmed to be driven on the rising or falling edge of qspiclk. each byte is sent msb first. this pin can also be configured as gpio pqs0. 14.2.7.2 qspi synchronous seri al data input (qspi_din) the qspi_din input provides the serial data to th e qspi and can be program med to be sampled on the rising or falling edge of qspiclk. each byte is written to ram lsb first. this pin can also be configured as gpio pqs1. 14.2.7.3 qspi serial clock (qspi_clk) the qspi serial clock (qspi_clk) provides the serial clock from the qspi. the polarity and phase of qspi_clk are programmable. the output frequency is programmed according to the following formula, in which n can be any value between 2 and 255: qspi_clk = clkout/(2n). this pin can also be configured as gpio pqs2. 14.2.7.4 qspi chip selects (qspi_cs[3:0]) the synchronous peripheral chip select s (qspi_cs[3:0]) outputs provide qs pi peripheral chip selects that can be programmed to be active high or low. this pin can also be configured as gpio pqs[6:3]. 14.2.8 flexcan signals 14.2.8.1 flexcan transmit (cantx) controller area network transmit data output. this pin can also be configured as gpio pas2. 14.2.8.2 flexcan receive (canrx) controller area network transmit data input. this pin can also be configured as gpio pas3. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 signal descriptions 14-26 freescale semiconductor 14.2.9 i 2 c signals the i 2 c module acts as a two-wire, bidi rectional serial inte rface between the proc essor and peripherals with an i 2 c interface (such as lcd controller, a-to-d conve rter, or d-to-a converter). devices connected to the i 2 c must have open-drain or open-collector outputs. 14.2.9.1 serial clock (scl) this bidirectional open-drain sign al is the clock signal for the i 2 c interface. either it is driven by the i 2 c module when the bus is in the master mode or it becomes the clock input when the i 2 c is in the slave mode. this pin can also be configured as gpio pas0 or utxd2. 14.2.9.2 serial data (sda) this bidirectional open-drain signal is the data input/output for the i 2 c interface. this pin can also be configured as gpio pas1 or urxd2. 14.2.10 uart module signals the signals in the following sections are used to transfer serial data between three uart modules and external peripherals. 14.2.10.1 transmit serial data output (utxd[2:0]) utxd[2:0] are the transmitter seri al data outputs for the uart modul es. the output is held high (mark condition) when the transmitter is di sabled, idle, or in the local loopba ck mode. data is shifted out, lsb first, on this pin at the falling e dge of the serial clock source. the utxd[1:0] pins can be confi gured as gpio ports pua2 and p ua0. the utxd2 output is offered on 3 pins and is a secondary function of the em dc/ gpio port pas4 pin, cant x/gpio port pas2 pin, and scl/gpio port pas0 pin. 14.2.10.2 receive serial data input (urxd[2:0]) urxd[2:0] are the receiver serial data inputs for the uart modules. data received on these pins is sampled on the rising edge of the serial clock source lsb first. when the uart clock is stopped for power-down mode, any transition on this pin restarts it. the urxd[1:0] pins can be confi gured as gpio ports pua3 and pu a1. the urxd2 input is offered on 3 pins and is a secondary function of the emdio/gp io port pas5 pin, canrx/gpio port pas3 pin, and sda/gpio port pas1 pin. 14.2.10.3 clear-to-send (ucts [1:0]) the ucts [1:0] signals are the clear-to-send (cts ) inputs, indicating to the ua rt modules that they can begin data transmission. the ucts [1:0] inputs are each offered as secondary functions on four pins--dtin2, dtout2, dtin0 and dtout0. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 signal descriptions freescale semiconductor 14-27 14.2.10.4 request-to-send (urts [1:0]) the urts [1:0] signals are automatic request to send outputs from the uart modules. urts [1:0] can also be configured to be asserted and ne gated as a function of the rx fifo level. the urts [1:0] outputs are each offere d as secondary func tions on four pins: dtin3, dtout3, dtin1 and dtout1. 14.2.11 general purpose timer signals these pins provide the external interface to the general purpose timer functions. 14.2.11.1 gpta[3:0] these pins provide the external in terface to the timer a functions. these pins can also be conf igured as gpio pta[3:0]. 14.2.11.2 gptb[3:0] these pins provide the external in terface to the timer b functions. these pins can also be conf igured as gpio ptb[3:0]. 14.2.11.3 external cl ock input (synca/syncb) these pins are used to clear the clock for each of the two timers, and ar e provided as a means of synchronization to externally clocked or timed events. 14.2.12 dma timer signals this section describes the signals of the four dma timer modules. 14.2.12.1 dma timer 0 input (dtin0) the dma timer 0 input (dtin0) can be programmed to cause events to occur in dma timer 0. it can either clock the event counter or provide a trigger to the timer value capture logic. this pin can also be configured as gpio ptd1, seconda ry function ucts1 , or secondary function ucts0 . 14.2.12.2 dma timer 0 output (dtout0) the programmable dma timer output (dtout0) pulse or toggle on various timer events. this pin can also be configured as gpio ptd0, seconda ry function ucts1 , or secondary function ucts0 . 14.2.12.3 dma timer 1 input (dtin1) the dma timer 1 input (dtin1) can be programmed to cause events to occur in dma tim er 1. this can either clock the event counter or provide a trigger to the timer value capture logic. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 signal descriptions 14-28 freescale semiconductor this pin can also be configured as gpio ptd3, secondary function urts1 , or secondary function urts0 . 14.2.12.4 dma timer 1 output (dtout1) the programmable dma timer output (dtout1) pulse or toggle on various timer events. this pin can also be configured as gpio ptd2, secondary function urts1 , or secondary function urts0 . 14.2.12.5 dma timer 2 input (dtin2) the dma timer 2 input (dtin2) can be programmed to cause events to occur in dma timer 2. it can either clock the event counter or provide a trigger to the timer value capture logic. this pin can also be configured as gpio ptc1, secondary function ucts1 , or secondary function ucts0 . 14.2.12.6 dma timer 2 output (dtout2) the programmable dma timer output (dtout2) pulse or toggle on various timer events. this pin can also be configured as gpio ptc0, secondary function ucts1 , or secondary function ucts0 . 14.2.12.7 dma timer 3 input (dtin3) the dma timer 3 input (dtin3) can be programmed as an input that cause s events to occu r in dma timer 3. this can either clock the event count er or provide a trigger to the time r value capture logic. this pin can also be configured as gpio ptc3, secondary function urts1 , or secondary function urts0 . 14.2.12.8 dma timer 3 output (dtout3) the programmable dma timer output (dtout0) pulse or toggle on various timer events. this pin can also be configured as gpio ptc2, secondary function urts1 , or secondary function urts0 . 14.2.13 analog-to-digit al converter signals these pins provide the analog inputs to the qadc. the pqa and pqb pins may also be used as general purpose digital i/o. 14.2.13.1 qadc anal og input (an0/anw) this pqb signal is the direct anal og input an0. when using external multiplexing this pin can also be configured as multiplexed input anw. this pin can also be co nfigured as gpio pqb0. 14.2.13.2 qadc anal og input (an1/anx) this pqb signal is the direct anal og input an1. when using external multiplexing this pin can also be configured as multiplexed input anx. this pin can also be co nfigured as gpio pqb1. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 signal descriptions freescale semiconductor 14-29 14.2.13.3 qadc anal og input (an2/any) this pqb signal is the direct anal og input an2. when using external multiplexing this pin can also be configured as multiplexed input any. this pin can also be co nfigured as gpio pqb2. 14.2.13.4 qadc anal og input (an3/anz) this pqb signal is the direct anal og input an3. when using external multiplexing this pin can also be configured as multiplexed input anz. this pin can also be co nfigured as gpio pqb3. 14.2.13.5 qadc anal og input (an52/ma0) this pqa signal is the di rect analog input an52. when using external multiplexing this pin can also be configured as an output signal, ma0, to select the output of the external multiplexer. this pin can also be co nfigured as gpio pqa0. 14.2.13.6 qadc anal og input (an53/ma1) this pqa signal is the di rect analog input an53. when using external multiplexing this pin can also be configured as an output signal, ma1, to select the output of the external multiplexer. this pin can also be co nfigured as gpio pqa1. 14.2.13.7 qadc analog input (an55/trig1) this pqa signal is the direct anal og input an55. this pin can also be configured as an input signal, trig1, to trigger the execution of one of the two queues. this pin can also be co nfigured as gpio pqa3. 14.2.13.8 qadc analog input (an56/trig2) this pqa signal is the direct anal og input an56. this pin can also be configured as an input signal, trig2, to trigger the execution of one of the two queues. this pin can also be co nfigured as gpio pqa4. 14.2.14 debug support signals these signals are used as the inte rface to the on-chip jt ag controller and also to interface to the bdm logic. 14.2.14.1 jtag_en this input signal is used to se lect between multiple xed debug module and jtag signals at reset. if jtag_en is low, the part is in normal and background debug mode (bdm); if it is high, it is in normal and jtag mode. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 signal descriptions 14-30 freescale semiconductor 14.2.14.2 development serial clock/test reset (dsclk/trst ) debug mode operation: dsclk is select ed. dsclk is the development serial clock for the se rial interface to the debug module. the maximum dsclk frequency is 1/5 clkin. jtag mode operation: trst is selected. trst asynchronously resets the inte rnal jtag controller to the test logic reset state, causing the jtag instruction register to choos e the bypass instru ction. when this occurs, jtag logic is benign and does not in terfere with normal device functionality. although trst is asynchronous, freescale re commends that it makes an asserted-to-negated transition only while tms is held high. trst has an internal pull-up resistor so if it is not dr iven low, it defaults to a logic level of 1. if trst is not used, it can be tied to ground or, if tck is clocked, to v dd . tying trst to ground places the jtag contro ller in test logic reset stat e immediately. tying it to v dd causes the jtag controller (if tms is a logic level of 1) to eventually enter test l ogic reset state after 5 tck clocks. 14.2.14.3 breakpoint/test mode select (bkpt /tms) debug mode operation: if jtag_en is low, bkpt is selected. bkpt signals a hardware breakpoint to the processor in debug mode. jtag mode operation: tms is sele cted. the tms input provides information to determine the jtag test operation mode. the state of tms and the internal 16-state jtag contro ller state machine at the rising edge of tck determine whether the jt ag controller holds its current stat e or advances to the next state. this directly controls whether jt ag data or instructi on operations occur. tms has an internal pull-up resistor so that if it is not driven low, it defaults to a logic level of 1. but if tms is not used, it should be tied to v dd . 14.2.14.4 development serial input/test data (dsi/tdi) debug mode operation: if jtag_en is low, dsi is selected. dsi provides th e single-bit communication for debug module commands. jtag mode operation: tdi is select ed. tdi provides the serial data port for loading the various jtag boundary scan, bypass, and instructi on registers. shifting in data depends on the state of the jtag controller state machine and the inst ruction in the instruction register. shifts occur on the tck rising edge. tdi has an internal pul l-up resistor, so when not driven low it defaults to high. but if tdi is not used, it should be tied to v dd . 14.2.14.5 development serial ou tput/test data (dso/tdo) debug mode operation: dso is selected. dso provides single-bi t communication for debug module responses. jtag mode operation: tdo is selected. the tdo output provides the serial da ta port for outputting data from jtag logic. shifting out data depends on the jtag controller st ate machine and the instruction in the instruction register. data shifting occurs on the falling edge of tck. when tdo is not outputting test data, it is three-stated. td o can be three-stated to allow bused or parallel connections to other devices having jtag. 14.2.14.6 test clock (tclk) tck is the dedicated jtag test logic clock indepe ndent of the processor cl ock. various jtag operations occur on the rising or falling edge of tck. holdi ng tck high or low for an indefinite period does not cause jtag test logic to lose st ate information. if tck is not used, it must be tied to ground. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 signal descriptions freescale semiconductor 14-31 14.2.14.7 debug data (ddata[3:0]) debug data signals (ddata[3:0]) display captured pr ocessor addresses, data and breakpoint status. these pins can also be configured as gpio pdd[7:4]. 14.2.14.8 processor status outputs (pst[3:0]) pst[3:0] outputs indicate core status, as shown below in table 14-7 . debug mode timin g is synchronous with the processor clock; status is un related to the current bus transfer. these pins can also be configured as gpio pdd[3:0]. 14.2.15 test signals 14.2.15.1 test (test) this input signal is re served for factory testi ng only and should be conn ected to vss to prevent unintentional ac tivation of test functions. table 14-7. processor status encoding pst[3:0] definition 0000 continue execution 0001 begin execution of an instruction 0010 reserved 0011 entry into user mode 0100 begin execution of pulse and wddata instruction 0101 begin execution of taken branch 0110 reserved 0111 begin execution of rte instruction 1000 begin one-byte transfer on ddata 1001 begin two-byte transfer on ddata 1010 begin three-byte transfer on ddata 1011 begin four-byte transfer on ddata 1100 exception processing 1101 emulator-mode exception processing 1110 processor is stopped 1111 processor is halted mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 signal descriptions 14-32 freescale semiconductor 14.2.16 power and reference signals these signals provide system power, ground and references to the device. multiple pins are provided for adequate current capability. all power supply pi ns must have adequate bypass capacitance for high-frequency noise suppression. 14.2.16.1 qadc analog reference (vrh, vrl) these signals serve as the high (vrh) and low (vrl) reference potentials for th e analog converter in the qadc. 14.2.16.2 qadc analog supply (vdda, vssa) these are dedicated power supply si gnals to isolate the sensitive qad c analog circuitry from the normal levels of noise present on the digital power supply. 14.2.16.3 pll analog su pply (vddpll, vsspll) these are dedicated power supply si gnals to isolate the sensitive p ll analog circuitry from the normal levels of noise present on the digital power supply. 14.2.16.4 qadc posi tive supply (vddh) this pin supplies positive power to th e esd structures in the qadc pads. 14.2.16.5 power for flas h erase/program (vpp) this pin is used for flash stress testing and can be left unconnected in normal device operation. 14.2.16.6 power and ground fo r flash array (vddf, vssf) these signals supply a power and ground to the flash array. 14.2.16.7 standby power (vstby) this pin is used to provide standby vol tage to the ram array if vdd is lost. 14.2.16.8 positive supply (vdd) this pin supplies positive power to the core logic and i/o pads. 14.2.16.9 ground (vss) this pin is the negative supply (ground) to the chip. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor 15-1 chapter 15 synchronous dram controller module this chapter describes configurat ion and operation of the synchrono us dram (sdram) controller. it begins with a general description and brief glossary, and includes a description of signals involved in dram operations. the remainder of the chapter describes the progr amming model and signal timing, as well as the command set required for synchronous operations. it also in cludes extensive examples that the designer can follow to better understand how to configure th e dram controller for synchronous operations. 15.1 overview the synchronous dram controller module provides glueless integrat ion of sdram with the coldfire product. the key features of the dram controller include the following: ? support for two independent blocks of sdram ? interface to standard sdram components ? programmable sras , scas , and refresh timing ? support for 8-, 16-, and 32-bit wide sdram blocks 15.1.1 definitions the following terminology is used in this chapter: ? sdram block: any group of dram me mories selected by one of the sras [1:0] signals. thus, the processor can support two independent memory blocks. the base address of each block is programmed in the dram address and co ntrol registers (dacr0 and dacr1). ? sdram: rams that operate like asynchronous drams but with a synchronous clock, a pipelined, multiple-bank archite cture, and a faster speed. ? sdram bank: an internal partition in an sdram device. for example, a 64-mbit sdram component might be configured as four 512k x 32 banks. banks are selected through the sdram component?s bank select lines. 15.1.2 block diagram and major components the basic components of the sd ram controller are shown in figure 15-1 . mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 synchronous dram controller module 15-2 freescale semiconductor figure 15-1. synchronous dram controller block diagram the dram controller?s major components are as follows: ? dram address and control regi sters (dacr0 and dacr1)?the dr am controller consists of two configuration register units, one for each supported memory block. dacr0 is accessed at ipsbar + 0x048; dacr1 is accessed at ipsbar + 0x050. the re gister information is passed on to the hit logic. ? control logic and state machine?generates al l sdram signals, taking hit information and bus-cycle characteristic data from the block l ogic in order to generate sdram accesses. handles refresh requests from the refresh counter. ? dram control register (dcr)? contains data to control refresh operation of the dram controller. both memory blocks are refres hed concurrently as controlled by dcr[rc]. ? refresh counter?determines when refresh should occur; controlled by the value of dcr[rc]. it generates a refresh request to the control block. ? hit logic?compares address a nd attribute signals of a current sdram bus cycle to both dacrs to determine if an sdram block is being accessed. hits are passed to the control logic along with characteristics of the bus cycle to be generated. ? address multiplexing?multiplexes addresses to allow column and row addresses to share pins. this allows glueless interface to sdrams. ? data generation?controls the data input and data output transmission between th e on-platform and off-platform data buses. memory block 0 hit logic dram address/control register 0 (dacr0) a[23:0] internal address control logic and dramw dram controller module refresh counter scas sras scke state machine multiplexing dram control register (dcr) bus memory block 1 hit logic dram address/control register 1 (dacr1) a[23:0] sdram_cs [1:0] bs[3:0] data generation d[31:0] internal q[31:0] internal d[31:0] d[31:0] mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 synchronous dram controller module freescale semiconductor 15-3 15.2 sdram controller operation by running synchronously with the sy stem clock, sdram can (after an in itial latency peri od) be accessed on every clock; 5-1-1-1 is a typica l burst rate to the sdram. unlike the mcf5272, this processor does not have an independent sd ram clock signal. for this processor, the timing of the sd ram controller is controlled by the clkout signal. note that because the processor ca nnot have more than one page op en at a time, it does not support interleaving. sdram controllers are mo re sophisticated than asynchronous dram controll ers. not only must they manage addresses and data, but they must send sp ecial commands for such functions as precharge, read, write, burst, auto-refres h, and various combinations of these functions. table 15-1 lists common sdram commands. sdrams operate differently than asynchronous drams, particularly in the use of data pipelines and commands to initiate special actions. commands are issued to memory usi ng specific encodings on address and control pins. soon after system reset, a command must be sent to the sdram mode register to configure sdram operating parameters. table 15-1. sdram commands command definition actv activate. executed before read or write executes; sdram registers and decodes row address. mrs mode register set. nop no-op. does not affect sdram state machin e; dram controller control signals negated; sdram_cs [1:0] asserted. pall precharge all. precharges all internal banks of an sdram component; executed before new page is opened. read read access. sdram registers column address and decodes that a read access is occurring. ref refresh. refreshes internal bank rows of an sdram component. self self refresh. refreshes internal bank rows of an sdram component when it is in low-power mode. selfx exit self refresh. this command is sent to the dram controller when dcr[is] is cleared. write write access. sdram registers column address and decodes that a write access is occurring. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 synchronous dram controller module 15-4 freescale semiconductor 15.2.1 dram controller signals table 15-2 describes the behavior of dr am signals in synchronous mode. 15.2.2 memory map for sdramc registers the dram controller register s memory map is shown in table 15-3 . 15.2.2.1 dram control register (dcr) the dcr, shown in figure 15-2 , controls refresh logic. table 15-2. synchronous dram signal connections signal description sras synchronous row address strobe. indicates a valid sdram row address is present and can be latched by the sdram. sras should be connected to the corresponding sdram sras . scas synchronous column address strobe. indicates a valid column address is present and can be latched by the sdram. scas should be connected to the corresponding sdram scas . dramw dram read/write. asserted for write operations and negated for read operations. sdram_cs [1:0 ] row address strobe. select each memory block of sdrams connected to the processor. one sdram_cs signal selects one sdram block and connects to the corresponding cs signals. scke synchronous dram clock enable. connected directly to the cke (clock enable) signal of sdrams. enables and disables the clock internal to sdram. when cke is low, memory can enter a power-down mode in which operations are suspended or capable of entering self-refresh mode. scke functionality is controlled by dcr[coc]. for designs using external multiplexing, setting coc allows scke to provide command-bit functionality. bs[3:0] column address strobe. bs[3:0] function as byte enables to the sdrams. they connect to the bs signals (or mask qualifiers) of the sdrams. table 15-3. dram controller registers ipsbar offset [31:24] [23:16] [15:8] [7:0] 0x040 dram control register (dcr) [p. 15-4] ? 0x044 ? 0x048 dram address and control register 0 (dacr0) [p. 15-6] 0x04c dram mask register block 0 (dmr0) [p. 15-8] 0x050 dram address and control register 1 (dacr1) [p. 15-6] 0x054 dram mask register block 1 (dmr1) [p. 15-8] mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 synchronous dram controller module freescale semiconductor 15-5 table 15-4 describes dcr fields. 15 14 13 12 11 10 9 8 0 field ? nam coc is rtim rc reset uninitialized r/w r/w addr ipsbar + 0x040 figure 15-2. dram control register (dcr) table 15-4. dcr field descriptions bits name description 15-14 ? reserved, should be cleared. 13 nam no address multiplexing. some implementations require external multiplexing. for example, when linear addressing is required, the sdram should not multiplex addresses on sdram accesses. 0 the sdram controller multiplexes the external address bus to provide column addresses. 1 the sdram controller does not multiplex the ex ternal address bus to provide column addresses. 12 coc command on sdram clock enable (scke). implemen tations that use external multiplexing (nam = 1) must support command information to be multiplexed onto the sdram address bus. 0 scke functions as a clock enable; self-refresh is initiated by the sdram controller through dcr[is]. 1 scke drives command information. because scke is not a clock enable, self-refresh cannot be used (setting dcr[is]). thus, external logic must be used if this functionality is desired. external multiplexing is also responsible for putting the command information on the proper address bit. 11 is initiate self-refresh command. 0 take no action or issue a selfx command to exit self refresh. 1 if dcr[coc] = 0, the s dram controller sends a self command to both sdram blocks to put them in low-power, self-refresh state where they remain until is is cleared. when is is cleared, the controller sends a selfx command for the sdrams to exit se lf-refresh. the refresh counter is suspended while the sdrams are in self-refres h; the sdram controls the refresh period. 10?9 rtim refresh timing. determines the timing operation of auto-refresh in the sdram controller. specifically, it determines the number of bus clocks inserted between a ref command and the next possible actv command. this same timing is used for both memory blocks controlled by the sdram controller. this corresponds to t rc in the sdram specifications. 00 3 clocks 01 6 clocks 1x 9 clocks 8?0 rc refresh count. controls refresh frequency. the number of bus clocks between refresh cycles is (rc + 1) x 16. refresh can range from 16?8192 bus clocks to accommodate both standard and low-power sdrams with bus clock operation from less than 2 mhz to greater than 50 mhz. the following example calculates rc for an auto-refresh period for 4096 rows to receive 64 ms of refresh every 15.625 s for each row (1031 bus clocks at 66 mhz). this operation is the same as in asynchronous mode. # of bus clocks = 1031 = (rc field + 1) x 16 rc = (1031 bus clocks/16) -1 = 63.44, which rounds to 63; therefore, rc = 0x3f. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 synchronous dram controller module 15-6 freescale semiconductor 15.2.2.2 dram address and control registers (dacr0/dacr1) the dacr n registers, shown in figure 15-3, contain the base address comp are value and the control bits for memory blocks 0 and 1 of the sdram controller. address a nd timing are also c ontrolled by bits in dacr n. table 15-5 describes dacr n fields. 31 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 field ba ? re ? casl ? cbm ? imrs ps ip ? reset uninitialized 0 uninitialized 0 uninitialized r/w r/w address ipsbar+0x048 (dacr0); 0x050 (dacr1) figure 15-3. dram address a nd control register (dacr n ) table 15-5. dacr n field descriptions bit name description 31?18 ba base address register. with dcmr[bam], determines the address range in which the associated dram block is located. each ba bit is compared with the corresponding address of the current bus cycle. if all unmasked bits match, the address hits in the associated dram block. ba functions the same as in asynchronous operation. 17?16 ? reserved, should be cleared. 15 re refresh enable. determines when the dram controller generates a refresh cycle to the dram block. 0 do not refresh associated dram block 1 refresh associated dram block 14 ? reserved, should be cleared. 13?12 casl cas latency. affects the following sdram timing sp ecifications. timing nomenclature varies with manufacturers. refer to the sdram specificat ion for the appropriate timing nomenclature: parameter number of bus clocks casl= 00 casl = 01 casl= 10 casl= 11 t rcd ?sras assertion to scas assertion 1 2 3 3 t casl ?scas assertion to data out 1 2 3 3 t ras ? actv command to precharge command 2 4 6 6 t rp ?precharge command to actv command 1 2 3 3 t rwl , t rdl ?last data input to precharge command 1111 t ep ?last data out to precharge command 1 1 1 1 11 ? reserved, should be cleared. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 synchronous dram controller module freescale semiconductor 15-7 10?8 cbm command and bank mux [2:0]. because differen t sdram configurations cause the command and bank select lines to correspond to different addresses, these resources are programmable. cbm determines the addresses onto which these functions are multiplexed. note: it is important to set cbm according to the location of the command bit. this encoding and the address multiplexing sc heme handle common sdram organizations. bank select bits include a base bit and all address bits above for sdrams with multiple bank select bits. 7 ? reserved, should be cleared. 6 imrs initiate mode register set ( mrs ) command. setting imrs generates a mrs command to the associated sdrams. in initialization, imrs should be set only after all dram controller registers are initialized and pall and refresh commands have been issued. after imrs is set, the next access to an sdram block programs the sdram?s mode register. thus, the address of the access should be programmed to place the correct mode information on the sdram address pins. because the sdram does not register this information, it doesn?t matter if the imrs access is a read or a write or what, if any, data is put onto the data bus. the dram controller clears imrs after the mrs command finishes. 0 take no action 1 initiate mrs command 5?4 ps port size. indicates the port size of the associated block of sdram, which allows for dynamic sizing of associated sdram accesses. ps functions the same in asynchronous operation. 00 32-bit port 01 8-bit port 1x 16-bit port 3 ip initiate precharge all ( pall ) command. the dram contro ller clears ip after the pall command is finished. accesses via ip should be no wider than the port size programmed in ps. 0 take no action. 1a pall command is sent to the associated sdram bloc k. during initialization, this command is executed after all dram controller registers are prog rammed. after ip is set, the next write to an appropriate sdram address generates the pall command to the sdram block. 2?0 ? reserved, should be cleared. table 15-5. dacr n field descriptions (continued) bit name description cbm command bit bank select bits 000 17 18 and up 001 18 19 and up 010 19 20 and up 011 20 21 and up 100 21 22 and up 101 22 23 and up 110 23 24 and up 111 24 25 and up mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 synchronous dram controller module 15-8 freescale semiconductor 15.2.2.3 dram controller mask registers (dmr0/dmr1) the dmr n, figure 15-4 , includes mask bits for the base address and for address attributes. table 15-6 describes dmr n fields. 31 1817 9876543210 field bam ? wp ? c/i am sc sd uc ud v reset uninitialized 0 r/w r/w addr ipsbar + 0x04c (dmr0), 0x054 (dmr1) figure 15-4. dram controller mask registers (dmr n ) table 15-6. dmr n field descriptions bits name description 31?18 bam base address mask. masks the associated dacr n [ba]. lets the dram controller connect to various dram sizes. mask bits need not be contiguous (see section 15.3, ?sdram example .? ) 0 the associated address bit is used in decoding the dram hit to a memory block. 1 the associated address bit is not used in the dram hit decode. 17?9 ? reserved, should be cleared. 8 wp write protect. determines whether the asso ciated block of dram is write protected. 0 allow write accesses 1 ignore write accesses. the dram controller ignores write accesses to the memory block and an address exception occurs. write accesses to a writ e-protected dram region are compared in the chip select module for a hit. if no hit occurs, an external bus cycle is generated. if this external bus cycle is not acknowledged, an access exception occurs. 7 ? reserved, should be cleared. 6?1 am x address modifier masks. determine which accesses can occur in a given dram block. 0 allow access type to hit in dram 1 do not allow access type to hit in dram bit associated access type access definition c/i cpu space/interrupt acknowledge movec instruction or interr upt acknowledge cycle am alternate master dma master sc supervisor code any supervisor-only instruction access sd supervisor data any data fetched during the instruction access uc user code any user instruction ud user data any user data 0 v valid. cleared at reset to ensure that the dram block is not erroneously decoded. 0 do not decode dram accesses. 1 registers controlling the dram block are initialized; dram accesses can be decoded. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 synchronous dram controller module freescale semiconductor 15-9 15.2.3 general synchronous operation guidelines to reduce system logic and to s upport a variety of sdram sizes, th e dram controller provides sdram control signals as well as a multiplexed row address and column address to the sdram. 15.2.3.1 address multiplexing table 15-7 shows the generic address mu ltiplexing scheme for sdram configurations. all possible address connection confi gurations can be deri ved from this table. note because the processor has 24 exterm al address lines, the maximum sdram address size is 128 mbits. the following tables provide a more comprehensive, step-by-step way to determine the correct address line connections for interfacing the coldfire processor to the sdram. to use the tables, find the one that corresponds to the number of column address lines on the sdram and to the port size as seen by the processor, which is not necessarily the sdram po rt size. for example, if two 1m x 16-bit sdrams together form a 1m x 32-bit memory , the port size is 32 bits. most sd rams likely have fewer address lines than are shown in the tables, so follow only the connections shown until all sdram address lines are connected. table 15-7. generic address multiplexing scheme address pin row address column address notes relating to port sizes 17 17 0 8-bit port only 16 16 1 8- and 16-bit ports only 15 15 2 14 14 3 13 13 4 12 12 5 11 11 6 10 10 7 99 8 17 17 16 32-bit port only 18 18 17 16-bit port only or 32-bit port with only 8 column address lines 19 19 18 16-bit port only when at least 9 column address lines are used 20 20 19 21 21 20 22 22 21 23 23 22 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 synchronous dram controller module 15-10 freescale semiconductor table 15-8. processor to sdram interface (8-bit port, 9-column address lines) process or pins a17 a16 a15 a14 a13 a12 a11 a 10 a9 a18 a19 a20 a21 a22 a23 row 17 16 15 14 13 12 11 10 9 18 19 20 21 22 23 column 012345678 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 table 15-9. processor to sdram interfac e (8-bit port,10-column address lines) process or pins a17 a16 a15 a14 a13 a12 a11 a10 a9 a19 a20 a21 a22 a23 row 17 16 15 14 13 12 11 10 9 19 20 21 22 23 column 01234567818 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 table 15-10. processor to sdram interface (8-bit port,11-column address lines) processo r pins a17 a16 a15 a14 a13 a12 a11 a10 a9 a19 a21 a22 a23 row 17 16 15 14 13 12 11 10 9 19 21 22 23 column 0123456781820 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 table 15-11. processor to sdram interface (8-bit port,12-column address lines) processor pins a17 a16 a15 a14 a13 a12 a11 a10 a9 a19 a21 a23 row 17 16 15 14 13 12 11 10 9 19 21 23 column 012345678182022 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 table 15-12. processor to sdram interface (8-bit port,13-column address lines) process or pins a17 a16 a15 a14 a13 a12 a11 a10 a9 a19 a21 a23 row 17 16 15 14 13 12 11 10 9 19 21 23 column 012345678182022 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 synchronous dram controller module freescale semiconductor 15-11 table 15-13. processor to sdram interface (16-bit port, 8-column address lines) process or pins a16 a15 a14 a13 a12 a11 a10 a9 a17 a18 a19 a20 a21 a22 a23 row 16 15 14 13 12 11 10 9 17 18 19 20 21 22 23 column 12345678 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 table 15-14. processor to sdram interface (16-bit port, 9-column address lines) processo r pins a16 a15 a14 a13 a12 a11 a10 a9 a18 a19 a20 a21 a22 a23 row 16 15 14 13 12 11 10 9 18 19 20 21 22 23 column 1234567817 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 table 15-15. processor to sdram interfac e (16-bit port, 10-column address lines) processo r pins a16 a15 a14 a13 a12 a11 a10 a9 a18 a20 a21 a22 a23 row 16 15 14 13 12 11 10 9 18 20 21 22 23 column 123456781719 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 table 15-16. processor to sdram interfa ce (16-bit port, 11-c olumn address lines) processo r pins a16 a15 a14 a13 a12 a11 a10 a9 a18 a20 a22 a23 row 16 15 14 13 12 11 10 9 18 20 22 23 column 12345678171921 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 table 15-17. processor to sdram interfa ce (16-bit port, 12-c olumn address lines) processor pins a16 a15 a14 a13 a12 a11 a10 a9 a18 a20 a22 row 16 15 14 13 12 11 10 9 18 20 22 column 12345678171921 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 synchronous dram controller module 15-12 freescale semiconductor table 15-18. processor to sdram interface (16-bit port, 13-column-address lines) processo r pins a16 a15 a14 a13 a12 a11 a10 a9 a18 a20 a22 row 16 15 14 13 12 11 10 9 18 20 22 column 12345678171921 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 table 15-19. processor to sdram interface (32-bit port, 8-column address lines) processo r pins a15 a14 a13 a12 a11 a10 a9 a17 a18 a19 a20 a21 a22 a23 row 151413121110 9 17181920212223 column 234567816 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 table 15-20. processor to sdram interface (32-bit port, 9-column address lines) processor pins a15 a14 a13 a12 a11 a10 a9 a17 a19 a20 a21 a22 a23 row 151413121110 9 171920212223 column 23456781618 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 table 15-21. processor to sdram interface (32-bit po rt, 10-column address lines) processor pins a15 a14 a13 a12 a11 a10 a9 a17 a19 a21 a22 a23 row 15 14 13 12 11 10 9 17 19 21 22 23 column 2345678161820 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 table 15-22. processor to sdram interfa ce (32-bit port, 11-c olumn address lines) processor pins a15 a14 a13 a12 a11 a10 a9 a17 a19 a21 a23 row 15 14 13 12 11 10 9 17 19 21 23 column 234567816182022 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 synchronous dram controller module freescale semiconductor 15-13 15.2.3.2 sdram byte strobe connections figure 15-5 shows sdram connections for po rt sizes of 32, 16, or 8 bits. figure 15-5. connections for ex ternal memory port sizes 15.2.3.3 interfacing example the tables in the previous section can be used to configure the interface in the following example. to interface one 2m x 32-bit x 4 ba nk sdram component (8 columns) , use the connections shown in table 15-24 . 15.2.3.4 burst page mode sdram can efficiently provide data when an sdram page is opened. as soon as scas is issued, the sdram accepts a new address and asserts scas every clkout for as long as accesses occur in that page. in burst page mode, there are multiple read or write operations for every actv command in the sdram if the requested transfer size exceeds the port size of the associated sdram. the primary cycle of the transfer generates the actv and read or write commands; secondary cycles generate only read or write commands. as soon as the transfer completes, the pall command is generated to prepare for the next access. table 15-23. processor to sdram interfa ce (32-bit port, 12-c olumn address lines) processor pins a15 a14 a13 a12 a11 a10 a9 a17 a19 a21 a23 row 15 14 13 12 11 10 9 17 19 21 23 column 234567816182022 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 table 15-24. sdram hardware connections sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 = cmd ba0 ba1 processor pins a15 a14 a13 a12 a11 a10 a9 a17 a18 a19 a20 a21 a22 processor data bus byte 0 8-bit port 16-bit port 32-bit port byte 1 byte 2 byte 3 byte 0 byte 1 byte 2 byte 3 byte 0 byte 1 byte 2 byte 3 d[31:24] d[23:16] d[15:8] d[7:0] external memory memory memory byte enable bs3 bs2 bs1 bs0 driven with indeterminate values driven with indeterminate values mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 synchronous dram controller module 15-14 freescale semiconductor note that in synchronous operation, burst mode a nd address incrementing during burst cycles are controlled by the dram co ntroller. thus, instead of the sdram en abling its internal burst incrementing capability, the processor controls th is function. this means that the burst function that is enabled in the mode register of sdrams must be disabled when interfacing to the processor. figure 15-6 shows a burst read operation. in this example, dacr[casl] = 01 for an sras -to-scas delay (t rcd ) of 2 system clock cycles. because t rcd is equal to the read cas latency (scas assertion to data out), this value is also 2 system clock cycles. notice that nop s are executed until th e last data is read. a pall command is executed one cycle after the last data transfer. figure 15-6. burst read sdram access figure 15-7 shows the burst write operation. in this example, dacr[casl] = 01, which creates an sras -to-scas delay (t rcd ) of 2 system clock cycles. note that data is available upon scas assertion and a burst write cycle completes two cycles s ooner than a burst read cycle with the same t rcd. the next bus cycle is initiate d sooner, but cannot begin an sd ram cycle until the precharge-to- actv delay completes. a[23:0] sras scas dramw d[31:0] t casl = 2 actv read nop nop sdram_cs [0] or [1] bs[3:0] nop pall row column column column column t rcd = 2 t ep clkout read read read mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 synchronous dram controller module freescale semiconductor 15-15 figure 15-7. burst write sdram access accesses in synchronous burst page mode always cause the following sequence: 1. actv command 2. nop commands to assure sras -to-scas delay (if cas latency is 1, there are no nop commands). 3. required number of read or write commands to service the transf er size with the given port size. 4. some transfers need more nop commands to assure the actv -to-precharge delay. 5. pall command 6. required number of idle clocks in serted to assure precharge-to- actv delay. 15.2.3.5 auto-refresh operation the dram controller is equipped with a refresh co unter and control. this logic is responsible for providing timing and control to refr esh the sdram without user intera ction. once the refresh counter is set, and refresh is enabled, the counter counts to zero. at this time, an internal refr esh request flag is set and the counter begins counting dow n again. the dram controller completes any active burst operation and then performs a pall operation. the dram controller then in itiates a refresh cycle and clears the refresh request flag. this refresh cycle includes a de lay from any precharge to the auto-refresh command, the auto-refresh command, a nd then a delay until any actv command is allowe d. any sdram access initiated during the auto-refresh cycle is delayed until the cycle is completed. a[23:0] sras scas dramw d[31:0] actv write pall nop sdram_cs [0] or [1] bs[3:0] t casl = 2 row column column column column t rp t rwl clkout nop write write write mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 synchronous dram controller module 15-16 freescale semiconductor figure 15-8 shows the auto-refresh timing. in this case, there is an sdram access when the refresh request becomes active. the request is delayed by the precharge to actv delay programmed into the active sdram bank by the cas bits. the ref command is then generate d and the delay required by dcr[rtim] is inserted before the next actv command is generated. in this example, the next bus cycle is initiated, but does not gene rate an sdram access until t rc is finished. because both chip selects are active during the ref command, it is passed to both blocks of external sdram. figure 15-8. auto-refresh operation 15.2.3.6 self-refresh operation self-refresh is a method of allowi ng the sdram to enter into a low-pow er state, while at the same time to perform an internal refresh operation and to maintain the integrity of the data stored in the sdram. the dram controller supports self-refresh with dcr[is]. when is is set, the self command is sent to the sdram. when is is cleared, the selfx command is sent to the dram controller. figure 15-9 shows the self-refresh operation. a[23:0] sras scas dramw pall sdram_cs [0] or [1] ref actv t rcd = 2 t rc = 6 clkout mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 synchronous dram controller module freescale semiconductor 15-17 figure 15-9. self-refresh operation 15.2.4 initialization sequence synchronous drams have a prescribed initialization sequence. the dram controller supports this sequence with the following procedure: 1. sdram control signals are reset to idle state. wa it the prescribed period after reset before any action is taken on the sdrams. this is normally around 100 s. 2. initialize the dcr, dacr, and dmr in their operational configuration. do not yet enable pall or ref commands. 3. issue a pall command to the sdrams by setting dac r[ip] and accessing a sdram location. wait the time (determined by t rp ) before any other execution. 4. enable refresh (set dacr[re]) and wa it for at least 8 refreshes to occur. 5. before issuing the mrs command, determine if the dmr mask bits need to be modified to allow the mrs to execute properly 6. issue the mrs command by setting dacr[imrs] and acces sing a location in the sdram. note that mode register settings are driven on the sdram address bus, so care must be taken to change dmr[bam] if the mode register configuration does not fall in the address range determined by the address mask bits. after the m ode register is set, dmr mask bits can be restored to their desired configuration. sras scas dramw pall sdram_cs [0] or [1] self first scke possible actv selfx self- refresh active t rcd = 2 t rc = 6 clkout (dcr[coc] = 0) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 synchronous dram controller module 15-18 freescale semiconductor 15.2.4.1 mode register settings it is possible to configure the operation of sdrams, namely their burst operation and cas latency, through the sdram component ?s mode register. cas latency is a function of the speed of the sdram and the bus clock of the dr am controller. the dram c ontroller operates at a cas latency of 1, 2, or 3. although the dram controller supports bursting operations, it does not use the bursting features of the sdrams. because the proces sor can burst operand sizes of 1, 2, 4, or 16 bytes long, the c oncept of a fixed burst length in the sdrams mode register becomes problematic. therefore, the processor dram controller generates the burst cycles rather than the sdram device. because the processor generates a new address and a read or write command for each transfer within the burst, the sdram mode register should be set either not to burst or to a burst length of one. this allows bursting to be controlled by the processor. the sdram mode register is writ ten by setting the associated bloc k?s dacr[imrs]. first, the base address and mask registers must be set to the appropriate configur ation to allow the mode register to be set. note that improperly set dmr mask bits may pr event access to the mode re gister address. thus, the user should determine the mapping of the mode register address to the pr ocessor address bits to find out if an access is blocked. if th e dmr setting prohibits mode register access, the dm r should be reconfigured to enable the access and then set to its necessary configuration after the mrs command executes. the associated cbm bits should also be initialized. after dacr[imrs] is set, the next access to the sdram address space generates the mrs command to that sdram. the address of the access should be selected to place the correct mode information on the sdram address pi ns. the address is not multiplexed for the mrs command. the mrs access can be a read or write. the important thing is that the address output of that access needs the correc t mode programming informati on on the correct address bits. figure 15-10 shows the mrs command, which occurs in the first clock of the bus cycle. figure 15-10. mode register set ( mrs ) command 15.3 sdram example this example interfaces a 512k x 32-bit x 4 bank sdram component to proc essor operating at 40 mhz. table 15-25 lists design specificat ions for this example. a[23:0] sras , scas dramw d[31:0] mrs sd_cs [1] or [0] clkout mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 synchronous dram controller module freescale semiconductor 15-19 table 15-25. sdram example specifications parameter specification speed grade (-8e) 40 mhz (25-ns period) 10 rows, 8 columns two bank-select lines to access four internal banks actv -to-read/write delay (t rcd ) 20 ns (min.) period between auto-refresh and actv command (t rc ) 70 ns actv command to precharge command (t ras ) 48 ns (min.) precharge command to actv command (t rp ) 20 ns (min.) last data input to pall command (t rwl ) 1 bus clock (25 ns) auto-refresh period for 4096 rows (t ref )6 4 m s mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 synchronous dram controller module 15-20 freescale semiconductor 15.3.1 sdram interface configuration to interface this component to the dram controller , use the connection table that corresponds to a 32-bit port size with 8 columns ( table 15-24 ). two pins select one of four banks when the part is functional. table 15-26 shows the proper hardware connections. 15.3.2 dcr initialization at power-up, the dcr has the fo llowing configuration if synchr onous operation and sdram address multiplexing are desired. this configuration results in a value of 0x0026 for dcr, as shown in table 15-27 . 15.3.3 dacr initialization as shown in figure 15-12 , the sdram is programme d to access only the sec ond 512-kbyte block of each 1-mbyte partition in the sdram (each 16 mbytes). the starting a ddress of the sdram is 0xff88_0000. continuous page mode feature is used. table 15-26. sdram hardware connections processor pins a15 a14 a13 a12 a11 a10 a9 a17 a18 a19 a20 a21 a22 sdram pins a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 = cmd ba0 ba1 15 14 13 12 11 10 9 8 0 field ? ? nam coc is rtim rc setting 0000_0000_0010_0110 (hex) 0026 figure 15-11. initialization values for dcr table 15-27. dcr initialization values bits name setting description 15 ? 0 reserved. 14 ? 0 reserved. 13 nam 0 indicating sdram controller multiplexes address lines internally 12 coc 0 scke is used as clock enable instead of command bit because user is not multiplexing address lines externally and requires external command feed. 11 is 0 at power-up, allowing power self-refresh state is not appropriate because registers are being set up. 10?9 rtim 00 because t rc value is 70 ns, indicating a 3-clock refresh-to- actv timing. 8?0 rc 0x26 specification indicates auto-refresh period for 4096 rows to be 64 ms or refresh every 15.625 s for each row, or 625 bus clocks at 40 mhz. because dcr[rc] is incremented by 1 and multiplied by 16, rc = (625 bus clocks/16) -1 = 38.06 = 0x38 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 synchronous dram controller module freescale semiconductor 15-21 figure 15-12. sdram configuration the dacrs should be programmed as shown in figure 15-13 . this configuration result s in a value of dacr0 = 0xff88_0300, as described in table 15-28 . dacr1 initialization is not needed beca use there is only one block. subse quently, dacr1[re, imrs,ip] should be cleared; everything else is a don?t care. 31 18 17 16 field ba ? setting 1111_1111_1000_10xx (hex) f f 8 8 151413121110 876543210 field re ? casl ? cbm ? imrs ps ip ? setting 0000_x011_x000_0000 (hex) 0300 figure 15-13. dacr register configuration table 15-28. dacr initialization values bits name setting description 31?18 ba 1111_1111_ 1000_10 base address. so dacr0[31?16] = 0xff88, placing the starting address of the sdram accessible memory at 0xff88_0000. 17?16 ? reserved. don?t care. 15 re 0 keeps auto-refresh disabled because registers are being set up at this time. 14 ? reserved. don?t care. 13?12 casl 00 indicates a delay of data 1 cycle after s cas is asserted 11 ? reserved. don?t care. 10?8 cbm 011 command bit is pin 20 and bank selects are 21 and up. 7 ? reserved. don?t care. 6 imrs 0 indicates mrs command has not been initiated. 5?4 ps 00 32-bit port. bank 0 1 mbyte 512 kbyte 512 kbyte sdram component accessible memory bank 1 1 mbyte 512 kbyte 512 kbyte bank 2 1 mbyte 512 kbyte 512 kbyte bank 3 1 mbyte 512 kbyte 512 kbyte mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 synchronous dram controller module 15-22 freescale semiconductor 15.3.4 dmr initialization again, in this example only the se cond 512-kbyte block of each 1-m byte space is accessed in each bank. in addition, the sdram component is mapped only to readable and writable supervisor and user data. the dmrs have the following configuration. with this configuration, the dmr0 = 0x0074_0075, as described in table 15-29 . 3 ip 0 indicates precharge has not been initiated. 2?0 ? reserved. don?t care. 31 18 17 16 field bam ? setting 0000_0000_0111_01xx (hex) 0 074 15 9876543210 field ? wp ? c/i am sc sd uc ud v setting xxxx_xxx0_x111_0101 (hex) 0075 figure 15-14. dmr0 register table 15-29. dmr0 initialization values bits name setting description 31?18 bam with bits 17 and 16 as don?t cares, bam = 0x0074, which leaves bank select bits and upper 512k select bits unmasked. note that bits 22 and 21 are set because they are used as bank selects; bit 20 is set because it controls the 1-mbyte boundary address. 17?16 ? reserved. don?t care. 15?9 ? reserved. don?t care. 8 wp 0 allow reads and writes 7 ? reserved. don?t care. 6 c/i 1 disable cpu space access. 5 am 1 disable alternate master access. 4 sc 1 disable supervis or code accesses. 3 sd 0 enable supervisor data accesses. 2 uc 1 disable user code accesses. 1 ud 0 enable user data accesses. 0 v 1 enable accesses. table 15-28. dacr initialization values (continued) bits name setting description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 synchronous dram controller module freescale semiconductor 15-23 15.3.5 mode register initialization when dacr[imrs] is set, a bus cycle initializes the mode register. if th e mode register se tting is read on a[10:0] of the sdram on the first bus cycle, the bit settings on th e corresponding processor address pins must be determined while bei ng aware of masking requirements. table 15-30 lists the desired initialization setting: next, this information is mapped to an address to determine th e hexadecimal value. although a[31:20] corresponds to the address programmed in dacr0, according to how dacr0 and dmr0 are initialized, bit 19 must be set to hit in the sdram. thus, before the mode re gister bit is set, dmr0[19] must be set to enable masking. 15.3.6 initialization code the following assembly code initializes the sdram example. table 15-30. mode register initialization processor pins sdram pins mode register initialization a20 a10 reserved x a19 a9 wb 0 a18 a8 opmode 0 a17 a7 opmode 0 a9 a6 casl 0 a10 a5 casl 0 a11 a4 casl 1 a12 a3 bt 0 a13 a2 bl 0 a14 a1 bl 0 a15 a0 bl 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 field setting xxxx_xxxx_xxxx_000x (hex) 0000 1514131211109876543210 field v setting 0000_100x_xxxx_xxxx (hex) 0800 table 15-31. mode register mapping to a[31:0] mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 synchronous dram controller module 15-24 freescale semiconductor power-up sequence: move.w #0x0026, d0//initialize dcr move.w d0, dcr move.l #0xff880300, d0 //initialize dacr0 move.l d0, dacr0 move.l #0x00740075, d0//initialize dmr0 move.l d0, dmr0 precharge sequence: move.l #0xff880308, d0//set dacr0[ip] move.l d0, dacr0 move.l #0xbeaddeed, d0//write and value to memory location to init. precharge move.l d0, 0xff880000 refresh sequence: move.l #0xff888300, d0//enable refresh bit in dacr0 move.l d0, dacr0 mode register ini tialization sequence: move.l #0x00600075, d0//mask bit 19 of address move.l d0, dmr0 move.l #0xff888340, d0//enable dacr0[imrs]; dacr0[re] remains set move.l d0, dacr0 move.l #0x00000000, d0//access sdram address to initialize mode register move.l d0, 0xff800800 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor 16-1 chapter 16 dma controller module this chapter describes the direct memory access (dma ) controller module. it pr ovides an overview of the module and describes in detail its signals and registers. the latter sections of this chapter describe operations, features, and supported da ta transfer modes in detail. note the designation ? n? is used throughout this sect ion to refer to registers or signals associated with one of the four identical dma channels: dma0, dma1, dma2 or dma3. 16.1 overview the dma controller module provides an efficient way to move blocks of data with minimal processor interaction. the dma module, shown in figure 16-1 , provides four channels that allow byte, word, longword, or 16-byte burst data tran sfers. each channel has a dedica ted source address register (sar n), destination address register (dar n), byte count register (bcr n ), control register (dcr n), and status register (dsr n ). transfers are dual address to on-chip devices, such as uart, sdram controller, and gpios. figure 16-1. dma signal diagram mux arbitration/ bus interface data path control internal external channel channel mux registered data path sar0 dar0 bcr0 dcr0 dsr0 channel 0 interrupts sar1 dar1 bcr1 dcr1 dsr1 channel 1 sar2 dar2 bcr2 dcr2 dsr2 channel 2 sar3 dar3 bcr3 dcr3 dsr3 channel 3 bus requests attributes current master attributes write data bus read data bus system bus address system bus size channel enables requests bus signals control control mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 dma controller module 16-2 freescale semiconductor note throughout this chapter ?ext ernal request? and dreq are used to refer to a dma request from one of the on-chip uarts or dma timers. for details on the connections associated with dma request inputs, see section 16.2, ?dma request control (dmareqc) .? 16.1.1 dma module features the dma controller module features are as follows: ? four independently programmab le dma controller channels ? auto-alignment feature for source or destination accesses ? dual-address transfers ? channel arbitration on transfer boundaries ? data transfers in 8-, 16-, 32-, or 128-bit blocks using a 16-byte buffer ? continuous-mode or cycle-steal transfers ? independent transfer widths for source and destination ? independent source and dest ination address registers 16.2 dma request control (dmareqc) the dmareqc register provides a so ftware-controlled connection matrix for dma requests. it logically routes dma requests from the dma timers and uarts to the four ch annels of the dma controller. writing to this register determines the exact routing of the dma request to the four channels of the dma modules. if dcr n [eext] is set and the channel is idle , the assertion of the appropriate dreq n activates channel n. 31 20 19 16 field ? ? reset 0000_0000_0000_0000 r/w r/w 15 12 11 8 7 4 3 0 field dmac3 dmac2 dmac1 dmac0 reset 0000_0000_0000_0000 r/w r/w ipsbar + 0x014 figure 16-2. dma request control register (dmareqc) table 16-1. dmareqc field description bits name description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 dma controller module freescale semiconductor 16-3 31?16 ? reserved. should be cleared. 15?0 dmac n dma channel n . each four bit field defines the logica l connection between the dma requestors and that dma channel. there are seven possible requesters (4 dma timers and 3 uarts). any request can be routed to any of the dma channels. effectively, the dmareqc provides a software-controlled routing matrix of the 7 dm a request signals to the 4 channels of the dma module. dmac3 controls dma channel 3. dmac2 controls dma channel 2. dmac1 controls dma channel 1. dmac0 controls dma channel 0. 1000 uart0. 1001 uart1. 1010 uart2. 0100 dma timer 0. 0101 dma timer 1. 0110 dma timer 2. 0111 dma timer 3. all other values are reserved and will not generate a dma request. table 16-1. dmareqc fiel d description (continued) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 dma controller module 16-4 freescale semiconductor 16.3 dma transfer overview the dma module can transfer data faster than the coldfire core. the term ?direct memory access? refers to a fast method of movi ng data within system memory (incl uding memory and peripheral devices) with minimal processor intervention, gr eatly improving over all system performance. the dma module consists of four independent, functi onally equivalent channels, so refere nces to dma in this chapter apply to any of the channels. it is not possible to implicitly address all four channels at once. the processor generates dma requests internally by setting dcr[start]; the uart modules and dma timers can generate a dma request by asserting internal dreq signa ls. the processor can program bus bandwidth for each channel. the channels support cycle-steal and continuous transfer modes; see section 16.5.1, ?transfer requests (cyc le-steal and continuous modes) .? the dma controller supports dual-address transfer s. the dma channels support up to 32 data bits. ? dual-address transfers?a dual-addr ess transfer consists of a r ead followed by a write and is initiated by an internal request using the start bi t or by asserting dreq. two types of transfer can occur: a read from a source device or a write to a destination device. see figure 16-3 for more information. figure 16-3. dual-address transfer any operation involving the dma module follows the same three steps: 1. channel initialization?channel registers are loaded with control information, address pointers, and a byte-transfer count. 2. data transfer?the dma accepts requests for operand transfers and provides addressing and bus control for the transfers. 3. channel termination?occurs after the operation is fi nished, either successfully or due to an error. the channel indicates the operation status in the channel?s dsr, described in section 16.4.5, ?dma status registers (dsr0?dsr3) .? 16.4 dma controller module programming model this section describes each internal register and its bit assignment. note that modifying dma control registers during a dma transfer can result in undefined operation. table 16-2 shows the mapping of dma controller registers. note the differences for the byte count re gisters depending on the value of mpark[bcr24bit]. see section 8.5.3, ?bus master park register (mpark) ? for further information. dma dma memory/ peripheral memory/ peripheral control and data control and data mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 dma controller module freescale semiconductor 16-5 16.4.1 source address registers (sar0?sar3) sar n, shown in figure 16-4 , contains the address from which the dma controller requests data. table 16-2. memory map for dma controller module registers dma channel ipsbar offset [31:24] [23:16] [15:8] [7:0] 0 0x100 source address register 0 (sar0) [p. 16-5] 0x104 destination address register 0 (dar0) [p. 16-6] 0x108 dma control register 0 (dcr0) [p. 16-7] 0x10c byte count register 0 (bcr24bit = 0) 1 1 the dma module originally supported a left-justified 16- bit byte count register (bcr). this function was later reimplemented as a right-justified 24-bit bcr. the operati on of the dma and the interpretation of the bcr is controlled by the mpark[bcr24bit]. see section 8.5.3, ?bus master park register (mpark) " for more details. reserved 0x10c reserved byte count r egister 0 (bcr24bit = 1) 1 (bcr0) [p. 16-7] 0x110 dma status register 0 (dsr0) [p. 16-10] reserved 1 0x140 source address register 1 (sar1) [p. 16-5] 0x144 destination address register 1 (dar1) [p. 16-6] 0x148 dma control register 1 (dcr1) [p. 16-7] 0x14c byte count register 1 (bcr24bit = 0) 1 reserved 0x14c reserved byte count register 1 (bcr24bit = 1) 1 (bcr1) [p. 16-7] 0x150 dma status register 1 (dsr1) [p. 16-10] reserved 2 0x180 source address register 2 (sar2) [p. 16-5] 0x184 destination address register 2 (dar2) [p. 16-6] 0x188 dma control register 2 (dcr2) [p. 16-7] 0x18c byte count register 2 (bcr24bit = 0) 1 reserved 0x18c reserved byte count r egister 2 (bcr24bit = 1) 1 (bcr2) [p. 16-7] 0x190 dma status register 2 (dsr2) [p. 16-10] reserved 3 0x1c0 source address register 3 (sar3) [p. 16-5] 0x1c4 destination address register 3 (dar3) [p. 16-6] 0x1c8 dma control register 3 (dcr3) [p. 16-7] 0x1cc byte count regist er 3 (bcr24bit = 0) 1 reserved 0x1cc reserved byte count register 3 (bcr24bit = 1) 1 (bcr3) [p. 16-7] 0x1d0 dma status register 3 (dsr3) [p. 16-10] reserved mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 dma controller module 16-6 freescale semiconductor note the backdoor enable bit must be set in both the core and scm in order to enable backdoor accesses fr om the dma to sram. see section 8.4.2, ?memory base address register (rambar) ? for more details. note flash accesses (reads/writ es) by a bus master ot her than the core (dma controller or fast ethernet controller), or writes to flash by the core during programming, must use the backdoor fl ash address of ipsbar plus an offset of 0x0400_0000. for example, fo r a dma transfer from the first flash location when ipsbar is stil l at its default location of 0x4000_0000, the source register would be loaded with 0x4400_0000. backdoor flash read accesses can be made with the bus master, but it takes two cycles longer than a direct read of the flash when using the flashbar address. 16.4.2 destination address registers (dar0?dar3) dar n, shown in figure 16-5 , holds the address to which th e dma controller sends data. figure 16-5. destination address registers (dar n ) note the dma does not maintain coherency with the cache. therefore, dmas should not transfer data to cacheable memory unless software is used to maintain the cache coherency. note the dma should not be used to writ e data to the uar t transmit fifo in cycle steal mode. when the uart inte rrupt is used as a dma request it does not negate fast enough to get a single transfer. the uart transmit fifo only has one entry so the data from the second byte would be lost. 31 0 field sar reset 0000_0000_0000_0000_0000_0000_0000_0000 r/w r/w address ipsbar + 0x100, 0x140, 0x180, 0x1c0 figure 16-4. source address registers (sar n ) 31 0 field dar reset 0000_0000_0000_0000_0000_0000_0000_0000 r/w r/w address ipsbar + 0x104, 0x144, 0x184, 0x1c4 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 dma controller module freescale semiconductor 16-7 16.4.3 byte count re gisters (bcr0?bcr3) bcr n, shown in figure 16-6 and figure 16-7, hold the number of byt es yet to be transferred for a given block. the offset within the memory map is based on the value of mpark[bcr24bit]. bcr n decrements on the successful completion of th e address transfer of a write transfer. bcr n decrements by 1, 2, 4, or 16 for byte, word, longw ord, or line accesses, respectively. figure 16-6 shows bcr n for bcr24bit = 1. figure 16-6. byte count registers (bcr n )?bcr24bit = 1 figure 16-7 shows bcr n for bcr24bit = 0. figure 16-7. byte count registers (bcr n) ?bcr24bit = 0 dsr n[done], shown in figure 16-9, is set when the block transfer is complete. when a transfer sequenc e is initiated and bcr n[bcr] is not a multiple of 16, 4, or 2 when the dma is configured for line, longword, or wo rd transfers, respectively, dsr n[ce] is set and no tr ansfer occurs. see section 16.4.5, ?dma status registers (dsr0?dsr3) .? 16.4.4 dma control re gisters (dcr0?dcr3) dcr n, shown in figure 16-8 , is used for configuring the dma controller module. note that dcr n [at] is available only if mpark[ bcr24bit] is set. see section 8.5.3, ?bus master park register (mpark) ? for more information. 31 24 23 0 field ? bcr reset ? 0000_0000_0000_0000_0000_0000 r/w r/w address ipsbar + 0x10c, 0x14c, 0x18c, 0x1cc 15 0 field bcr reset 0000_0000_0000_0000 r/w r/w address ipsbar + 0x10c, 0x14c, 0x18c, 0x1cc mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 dma controller module 16-8 freescale semiconductor table 16-3 describes dcr n fields. 31 30 29 28 27 25 24 23 22 21 20 19 18 17 16 field int eext cs aa bwc ? ? sinc ssize dinc dsize start reset 0000_0000_0000_0000 r/w r/w 15 14 0 field at 1 1 available only if bcr24bit = 1, otherwise reserved. ? reset 0 n/a r/w r/w address ipsbar + 0x108, 0x148, 0x188, 0x1c8 figure 16-8. dma cont rol registers (dcr n ) table 16-3. dcr n field descriptions bits name description 31 int interrupt on completion of transfer. determines whether an interrupt is generated by completing a transfer or by the occurrence of an error condition. 0 no interrupt is generated. 1 internal interrupt signal is enabled. 30 eext enable external request. care should be taken because a collision can occur between the start bit and dreq when eext = 1. 0 external request is ignored. 1 enables external request to initiate transfer. the internal request (initiated by setting the start bit) is always enabled. 29 cs cycle steal. 0 dma continuously makes read/write tr ansfers until the bcr decrements to 0. 1 forces a single read/write transfer per request. t he request may be internal by setting the start bit, or external by asserting dreq. 28 aa auto-align. aa and size determine whether the source or destination is auto-aligned, that is, transfers are optimized based on the address and size. see section 16.5.4.1, ?auto-alignment .? 0 auto-align disabled 1 if ssize indicates a transfer no smaller than dsize, source accesses are aut o-aligned; otherwise, destination accesses are auto-aligned. source alignment takes precedence over destination alignment. if auto-alignment is enabled, the appr opriate address register increments, regardless of dinc or sinc. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 dma controller module freescale semiconductor 16-9 27?25 bwc bandwidth control. indicates the number of byte s in a block transfer. when the byte count reaches a multiple of the bwc value, the dma releases the bu s. for example, if bcr24bit is 0, bwc is 001 (512 bytes or value of 0x0200), and bcr is 0x1000, the bus is relinquished after bcr values of 0x0e00, 0x0c00, 0x0a00, 0x0800, 0x 0600, 0x0400, and 0x0200. if bcr24bit is 0, bwc is 110, and bcr is 33000, the bus is released after 232 bytes because the bcr is at 32768, a multiple of 16384. 24?23 ? reserved, should be cleared. 22 sinc source increment. controls whether a source address increments afte r each successful transfer. 0 no change to sar after a successful transfer. 1 the sar increments by 1, 2, 4, or 16, as determined by the transfer size. 21?20 ssize source size. determines the data size of the source bus cycle for the dma control module. 00 longword 01 byte 10 word 11 line (16-byte burst) 19 dinc destination increment. controls whether a dest ination address increments after each successful transfer. 0 no change to the dar after a successful transfer. 1 the dar increments by 1, 2, 4, or 16, depending upon the size of the transfer. 18?17 dsize destination size. determines the data size of the destination bus cycle for the dma controller. 00 longword 01 byte 10 word 11 line (16-byte burst) 16 start start transfer. 0dma inactive 1 the dma begins the transfer in accordance to the va lues in the control registers. start is cleared automatically after one system clock and is always read as logic 0. table 16-3. dcr n field descriptions (continued) bits name description encoding bcr24bit = 0 bcr24bit = 1 000 dma has priority and does not negate its request until transfer completes. 001 512 16384 010 1024 32768 011 2048 65536 100 4096 131072 101 8192 262144 110 16384 524288 111 32768 1048576 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 dma controller module 16-10 freescale semiconductor 16.4.5 dma status registers (dsr0?dsr3) in response to an event, the dma controller writes to the appropriate dsr n bit, figure 16-9. only a write to dsr n[done] results in action. table 16-4 describes dsr n fields. 15 at at is available only if mpark[bcr24bit] = 1. dma acknowledge type. controls whether acknowledge information is provided for the entire transfer or only the final transfer. 0 entire transfer. dma acknowledge information is displayed anytime the channel is selected as the result of an external request. 1 final transfer (when bcr reaches zero). for dual-address transfer, the acknowledge information is displayed for both the read and write cycles. 14?0 ? reserved, should be cleared. 76543210 field ? ce bes bed ? req bsy done reset 0000_0000 r/w r/w address ipsbar + 0x110, 0x150, 0x190, 0x1d0 figure 16-9. dma status registers (dsr n ) table 16-4. dsr n field descriptions bits name description 7 ? reserved, should be cleared. 6 ce configuration error. occurs when bcr, sar, or dar does not match the requested transfer size, or if bcr = 0 when the dma receives a start condition . ce is cleared at hardware reset or by writing a 1 to dsr[done]. 0 no configuration error exists. 1 a configuration error has occurred. 5 bes bus error on source 0 no bus error occurred. 1 the dma channel terminated with a bus error during the read portion of a transfer. 4 bed bus error on destination 0 no bus error occurred. 1 the dma channel terminated with a bus error during the write portion of a transfer. 3 ? reserved, should be cleared. 2 req request 0 no request is pending or the channel is currently active. cleared when the channel is selected. 1 the dma channel has a transfer remaining and the channel is not selected. table 16-3. dcr n field descriptions (continued) bits name description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 dma controller module freescale semiconductor 16-11 16.5 dma controller module functional description in the following discussion, the term ?dma request? implies that dcr n [start] or dcr n [eext] is set, followed by assertion of dreq n . the start bit is cleared when the channel begins an internal access. before initiating a dual-address access, the dma module verifies that dcr n[ssize,dsize] are consistent with the source and destin ation addresses. if they are not cons istent, the configuration error bit, dsr n [ce], is set. if misalignment is detected, no transfer occurs, dsr n[ce] is set, and, depending on the dcr configuration, an interrupt event is issued. note that if the auto-align bit, dcr n [aa], is set, error checking is performed on th e appropriate registers. a read/write transfer reads bytes fr om the source address a nd writes them to the de stination address. the number of bytes is the larger of the sizes specified by dcr n[ssize] and dcr n[dsize]. see section 16.4.4, ?dma control registers (dcr0?dcr3) .? source and destination address registers (sar n and dar n) can be programmed in the dcr n to increment at the completion of a successful transfer. 16.5.1 transfer requests (cycle -steal and cont inuous modes) the dma channel supports internal and external requests. a request is issued by setting dcr n [start] or by asserting dreq n. setting dcr n[eext] enables recognition of ex ternal dma requests. selecting between cycle-steal and continuous modes minimizes bus usage for either internal or external requests. ? cycle-steal mode (dcr n[cs] = 1)?only one comple te transfer from source to destination occurs for each request. if dcr n[eext] is set, a request can be either internal or external. an internal request is selected by setting dcr n [start]. an external request is initiated by asserting dreq n while dcr n [eext] is set. note that multiple transfers will occur if dreq n is continuously asserted. ? continuous mode (dcr n[cs] = 0)?after an internal or ex ternal request, the dma continuously transfers data until bcr n reaches zero or a multiple of dcr n[bwc] or until dsrn [done] is set. if bcr n is a multiple of bwc, the dma request signa l is negated until the bus cycle terminates to allow the internal arbite r to switch masters. dcr n[bwc] = 000 specifies the maximum transfer rate; other values specify a transfer rate limit. the dma performs the specified number of transfers, then relinquishes bus control. the dma negates its internal bus request on the last transfer before bcr n reaches a multiple of the boundary specified in bwc. on completion, the dma reasserts its bus request to regain mastership at the earliest opportunity. the dma loses bus c ontrol for a minimum of one bus cycle. 1 bsy busy 0 dma channel is inactive. cleared when the dma has finished the last transaction. 1 bsy is set the first time the channel is enabled after a transfer is initiated. 0 done transactions done. set when all dma controller transactions complete, as determined by transfer count or error conditions. when bcr reaches zero, done is set when the final transfer completes successfully. done can also be used to abort a trans fer by resetting the status bits. when a transfer completes, software must clear done before reprogramming the dma. 0 writing or reading a 0 has no effect. 1 dma transfer completed. writing a 1 to this bit clears all dma status bits and can be used in an interrupt handler to clear the dma interrupt and error bits. table 16-4. dsr n field descriptions (continued) bits name description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 dma controller module 16-12 freescale semiconductor 16.5.2 data transfer modes each channel supports dual-address transf ers, described in the next section. 16.5.2.1 dual-address transfers dual-address transfers consist of a source data read and a destination data writ e. the dma controller module begins a dual-addr ess transfer sequence du ring a dma request. if no error condition exists, dsr n [req] is set. ? dual-address read?the dma controller drives the sar n value onto the internal address bus. if dcr n [sinc] is set, the sar n increments by the appropriate number of bytes upon a successful read cycle. when the appropriate number of read cy cles complete (multiple reads if the destination size is larger than the source), the dma in itiates the write portion of the transfer. if a termination error occurs, dsr n[bes,done] are set and dma transactions stop. ? dual-address write?the dma controller drives the dar n value onto the address bus. if dcr n [dinc] is set, dar n increments by the appr opriate number of bytes at the completion of a successful write cycle. bcr n decrements by the approp riate number of bytes. dsr n [done] is set when bcr n reaches zero. if the bcr n is greater than zero, another r ead/write transfer is initiated. if the bcr n is a multiple of dcr n [bwc], the dma request signal is negated until termination of the bus cycle to allow the internal arbiter to switch masters. if a termination error occurs, dsr n[bes,done] are set and dma transactions stop. 16.5.3 channel initialization and startup before a block transfer starts, channel registers must be initia lized with information describing configuration, request-generation method, and the data block. 16.5.3.1 channel prioritization the four dma channels are prioriti zed in ascending order (channel 0 ha ving highest priority and channel 3 having the lowest) or in an order determined by dcr n [bwc]. if the bwc encoding for a dma channel is 000, that channel has priority only over the channel immediately preced ing it. for example, if dcr3[bwc] = 000, dma channel 3 has priority over dma channel 2 (assuming dcr2[bwc] 000) but not over dma channel 1. if dcr0[bwc] = dcr1[bwc] = 000, dma0 still has priority over dm a1. in this case, dcr1[bwc] = 000 does not affect prioritization. simultaneous external requests are prioritized either in ascending order or in an order determined by each channel?s dcr n [bwc] bits. 16.5.3.2 programming the dma controller module note the following general guidelines for programming the dma: ? no mechanism exists within the dma module itself to prevent writes to control registers during dma accesses. ?if the dcr n [bwc] value of sequential channels are equal, the channels are prioritized in ascending order. the sar n is loaded with the source (read) address. if the transfer is from a periph eral device to memory, the source address is the location of th e peripheral data register. if the tran sfer is from memory to either a mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 dma controller module freescale semiconductor 16-13 peripheral device or memory, the source address is the starting a ddress of the data block. this can be any aligned byte address. the dar n should contain the destin ation (write) address. if the transfer is from a peripheral device to memory, or from memory to memory, the dar n is loaded with the starting a ddress of the data block to be written. if the transfer is from memory to a peripheral device, dar n is loaded with the address of the peripheral data register. this addr ess can be any aligned byte address. sar n and dar n change after each cycle depending on dcrn[ssize,dsize, sinc,dinc] and on the starting address. increment values can be 1, 2, 4, or 16 for byte, word, longword, or 16-byte line transfers, respectively. if the address regist er is programmed to remain unchange d (no count), the register is not incremented after the data transfer. bcr n[bcr] must be loaded with the number of byte tran sfers to occur. it is decremented by 1, 2, 4, or 16 at the end of each transfer, depending on the transfer size. dsr n[done] must be cleared for channel startup. as soon as the channel has been initiali zed, it is started by writing a one to dcr n [start] or asserting dreq n, depending on the status of dcr n[eext]. programming the channel for internal requests causes the channel to request the bus and start transferring data immediately. if the channel is programmed for external request, dreq n must be asserted before the channel requests the bus. changes to dcr n are effective immediately while the channel is active. to avoid pr oblems with changing a dma channel setup, write a one to dsr n[done] to stop the dma channel. 16.5.4 data transfer this section describes au to-alignment and bandwidth control for dma transfers. 16.5.4.1 auto-alignment auto-alignment allows block transfers to occur at the optimal size based on th e address, byte count, and programmed size. to us e this feature, dcr n[aa] must be set. the sour ce is auto-aligned if dcr n [ssize] indicates a transfer size larger than dcr n[dsize]. source alignmen t takes precedence over the destination when the source and dest ination sizes are equal. otherwise, the destination is auto-aligned. the address register chosen fo r alignment increments regardless of th e increment value. configuration error checking is performed on registers not chosen for alignment. if bcr n is greater than 16, the address de termines transfer size . bytes, words, or longwords are transferred until the address is aligned to the programm ed size boundary, at which ti me accesses begin using the programmed size. if bcr n is less than 16 at the start of a transfer, the num ber of bytes remaining dict ates transfer size. for example, aa = 1, sar n = 0x0001, bcr n = 0x00f0, ssize = 00 (longword) , and dsize = 01 (byte). because ssize > dsize, the source is auto-aligned. error checking is pe rformed on destination registers. the access sequence is as follows: 1. read byte from 0x0001?write 1 byte, increment sar n. 2. read word from 0x0002?write 2 bytes, increment sar n. 3. read longword from 0x0004?write 4 bytes, increment sar n. 4. repeat longwords until sar n = 0x00f0. 5. read byte from 0x00f0?write byte, increment sar n. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 dma controller module 16-14 freescale semiconductor if dsize is another size, data writ es are optimized to wr ite the largest size allo wed based on the address, but not exceeding the configured size. 16.5.4.2 bandwidth control bandwidth control makes it possible to force the dma off the bus to allow access to another device. dcr n[bwc] provides seven le vels of block transfer sizes. if the bcr n decrements to a multiple of the decode of the bwc, the dma bus re quest negates until the bus cycle te rminates. if a request is pending, the arbiter may then pass bus ma stership to another device. if auto-alignment is enabled, dcr n[aa] = 1, the bcr n may skip over the programmed boundary, in whic h case, the dma bus request is not negated. if bwc = 000, the request signa l remains asserted until bcr n reaches zero. dma has priority over the core. note that in this scheme , the arbiter can always force the dma to relinquish the bus. see section 8.5.3, ?bus master park register (mpark) .? 16.5.5 termination an unsuccessful transfer can terminate for one of the following reasons: ? error conditions?when the processo r encounters a read or write cy cle that terminates with an error condition, dsr n [bes] is set for a read and dsr n [bed] is set for a write before the transfer is halted. if the error occurred in a write cycle, data in the internal holding register is lost. ? interrupts?if dcr n [int] is set, the dma drives the appropriate internal interrupt signal. the processor can read dsr n to determine whether the transfer terminated successfully or with an error. dsr n[done] is then writte n with a one to clear the interr upt and the done and error bits. ? mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor 17-1 chapter 17 fast ethernet controller (fec) 17.1 introduction this chapter provides a feature-set overview, a functional block diagram, a nd transceiver connection information for the 10 and 100 mbps mii (media indepe ndent interface), as well as the 7-wire serial interface. additionally, detailed descriptions of operation and the programming model are included. note the mcf5214 and mcf5216 do not contain an fec module. 17.1.1 overview the ethernet media access controller (mac) s upports 10 and 100 mbps ethernet/ieee 802.3 networks. an external transceiver interface and transceiver f unction are required to complete the interface to the media. the fec supports three different standard mac-phy (physical) interfaces for connection to an external ethernet transceiver. the fec supports the 10/100 mbps mii and the 10 mbps-only 7-wire interface. note the gpio module must be configured to enable the peripheral function of the appropriate pins (refer to chapter 26, ?general purpose i/o module? ) prior to configuring the fec. 17.1.2 block diagram figure 17-1 shows the block diagram of the fec. the fec is implemented with a combination of hardware and microcode. the off-c hip (ethernet) interfaces are co mpliant with industry and ieee 802.3 standards. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) 17-2 freescale semiconductor figure 17-1. fec block diagram the descriptor controller is a risc-based c ontroller providing these functions in the fec: ? initialization (those internal regist ers not initialized by you or hardware) ? high level control of the dma ch annels (initiating dma transfers) ? interpreting buffer descriptors ? address recognition for receive frames ? random number generation for tr ansmit collision backoff timer note dma references in this section refe r to the fec?s dma engine. this dma engine transfers fec data only and is not related to the edma controller described in chapter 16, ?dma controller module ,? nor to the dma timers described in chapter 21, ?dma timers (dtim0?dtim3).? the ram is the focal point of all data flow in the fa st ethernet controller a nd divides into transmit and receive fifos. the fifo boundaries are programmable using th e frsr register. user data flows to/from the dma block from/to the receive/tr ansmit fifos. transmit data flows from the transmit fifo into the transmit block, and receive data flows from the receive block into the receive fifo. fifo fec dma mii receive transmit controller i/o pa d mdo mden mdi mii/7-wire data fifo ram fec bus option fec_txen fec_txd[3:0] fec_txer fec_txclk fec_crs fec_col fec_rxclk fec_rxdv fec_rxd[3:0] fec_rxer fec_mdc fec_mdio ram internal bus control/status descriptor controller bus controller (risc + microcode) registers interface internal bus crossbar switch master bus interface mib counter ram mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) freescale semiconductor 17-3 you control the fec by writing into control registers located in each block. the csr (control and status registers) block provides global c ontrol (ethernet reset and enable) and interrupt managing registers. the mii block provides a serial cha nnel for control/status communication with the external physical layer device (transceiver). this serial channel consists of the fec_md c (management data clock) and fec_mdio (management data input/ output) lines of the mii interface. the fec dma block (not to be conf used with the device?s edma contro ller) provides multiple channels allowing transmit data, transmit descriptor, re ceive data and receive de scriptor accesses to run independently. the transmit and receive blocks provide the ethernet mac functionality (w ith some assist from microcode). the message information block (mib) maintains counters for a variety of network events and statistics. it is not necessary for operation of the fec, but provides valuable counters fo r network management. the counters supported are the rmon (r fc 1757) ethernet statistics group and some of the ieee 802.3 counters. see section 17.4.1, ?mib block counters memory map,? for more information. 17.1.3 features the fec incorporates the following features: ? support for three different et hernet physical interfaces: ? 100-mbps ieee 802.3 mii ? 10-mbps ieee 802.3 mii ? 10-mbps 7-wire inte rface (industry standard) ? ieee 802.3 full duplex flow control ? programmable max frame length supports ieee 802.1 vlan tags and priority ? support for full-duplex operation (200 mbps throughput) with a mini mum internal bus clock rate of 50 mhz ? support for half-duplex operation (100 mbps throughput ) with a minimum internal bus clock rate of 50 mhz ? retransmission from transmit fifo following a collision (no processor bus utilization) ? automatic internal flushing of the receive fifo for runts (c ollision fragments) and address recognition rejects (no pr ocessor bus utilization) ? address recognition ? frames with broadcast a ddress may be always accepted or always rejected ? exact match for single 48-bit individual (unicast) address ? hash (64-bit hash) check of individual (unicast) addresses ? hash (64-bit hash) check of group (multicast) addresses ? promiscuous mode mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) 17-4 freescale semiconductor 17.2 modes of operation the primary operational modes ar e described in this section. 17.2.1 full and half duplex operation full duplex mode is for use on point -to-point links between switches or end node to switch. half duplex mode works in connections between an end node an d a repeater or betwee n repeaters. tcr[fden] controls duplex mode selection. when configured for full duplex mode, flow control may be enabled. refer to the tcr[rfc_pause,tfc_pause] bits, the rcr[fce] bit, and section 17.5.11, ?full duplex flow control ,? for more details. 17.2.2 interface options the following interface options are supported. a detailed di scussion of the interface configurations is provided in section 17.5.6, ?network interface options.? 17.2.2.1 10 mbps and 100 mbps mii interface the ieee 802.3 standard defines the media independe nt interface (mii) for 10/100 mbps operation. the mac-phy interface may be configured to opera te in mii mode by setting rcr[mii_mode]. fec_txclk and fec_rxclk pins driven by the exte rnal transceiver determine the operation speed. the transceiver auto-negotiates the speed or software controls it via the serial management interface (fec_mdc/fec_mdio pins) to the transceiver. refer to the mmfr and mscr register descriptions, as well as the section on the mii, for a description of how to read and wr ite registers in the transceiver via this interface. 17.2.2.2 10 mpbs 7-wire interface operation the fec supports 7-wire interface used by many 10 mbps ethernet transceivers. the rcr[mii_mode] bit controls this functionality. if this bit is cleared, mii mode is disabled and th e 10 mbps 7-wire mode is enabled. 17.2.3 address recognition options the address options supported are promiscuous, broadcast reject , individual address (h ash or exact match), and multicast hash match. a ddress recognition options are discussed in detail in section 17.5.9, ?ethernet address recognition.? 17.2.4 internal loopback internal loopback mode is selected via rcr[loop]. loopback mode is discussed in detail in section 17.5.14, ?mii internal and external loopback.? mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) freescale semiconductor 17-5 17.3 external signal description table 17-1 describes the various fec signals, as well as indicating which signals work in available modes. 17.4 memory map/register definition the fec is programmed by a combination of control/st atus registers (csrs) and buffer descriptors. the csrs control operation mode s and extract global status information. the descriptors pass data buffers and related buffer information betwee n the hardware and software. each fec implementation requires a 1- kbyte memory map space, which is divided into two sections of 512 bytes each for: table 17-1. fec signal descriptions signal name mii 7-wire description fec_col x x asserted upon detection of a collision and remains asserted while the collision persists. this signal is not defined for full-duplex mode. fec_crs x ? when asserted, indicates that transmit or receive medium is not idle. fec_mdc x ? output clock which provides a timing refere nce to the phy for data transfers on the fec_mdio signal. fec_mdio x ? transfers control information between the external phy and the media-access controller. data is synchronous to fec_mdc. this signal is an input after reset. when the fec is operated in 10mbps 7-wire interface mode, this signal should be connected to vss. fec_rxclk x x provides a timing reference for fec_rxdv, fec_rxd[3:0], and fec_rxer. fec_rxdv x x asserting the fec_rxdv input indicates that the phy has valid nibbles present on the mii. fec_rxdv should remain asserted from the first recovered nibble of the frame through to the last nibble. assertion of fec_rxdv must start no later than the sfd and exclude any eof. fec_rxd0 x x this pin contains the ethernet input data transferred from the phy to the media-access controller when fec_rxdv is asserted. fec_rxd1 x ? this pin contains the ethernet input data transferred from the phy to the media access controller when fec_rxdv is asserted. fec_rxd[3:2] x ? these pins contain t he ethernet input data transferred from the phy to the media access controller when fec_rxdv is asserted. fec_rxer x ? when asserted with fec_rxdv, indicates that the phy has detected an error in the current frame. when fec_rxdv is not asserted fec_rxer has no effect. fec_txclk x x input clock which provides a timing refe rence for fec_txen, fec_txd[3:0] and fec_txer. fec_txd0 x x the serial output ethernet data and is only valid during the assertion of fec_txen. fec_txd1 x ? this pin contains the serial output ethe rnet data and is valid only during assertion of fec_txen. fec_txd[3:2] x ? these pins contain t he serial output ethernet data and are valid only during assertion of fec_txen. fec_txen x x indicates when valid nibbles are present on the mii. this signal is asserted with the first nibble of a preamble and is negated before the first fe c_txclk following the final nibble of the frame. fec_txer x ? when asserted for one or more clock cycles while fec_txen is also asserted, the phy sends one or more illegal symbols. fec_txer has no effect at 10 mbps or when fec_txen is negated. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) 17-6 freescale semiconductor ? control/status registers ? event/statistic counters held in the mib block table 17-2 defines the top level memory map. table 17-3 shows the fec register memory map. table 17-2. module memory map address function ipsbar + 0x1000 ? 11ff control/status registers ipsbar + 0x1200 ? 12ff mib block counters table 17-3. fec register memory map ipsbar offset register width (bits) access reset value section/page 0x1004 interrupt event register (eir) 32 r/w 0x0000_0000 17.4.2/17-9 0x1008 interrupt mask register (eimr) 32 r/w 0x0000_0000 17.4.3/17-10 0x1010 receive descriptor active register (rdar) 32 r/w 0x0000_0000 17.4.4/17-11 0x1014 transmit descriptor active register (tdar) 32 r/w 0x0000_0000 17.4.5/17-12 0x1024 ethernet control regi ster (ecr) 32 r/w 0xf000_0000 17.4.6/17-12 0x1040 mii management frame register (mmfr) 32 r/w undefined 17.4.7/17-13 0x1044 mii speed control register (mscr) 32 r/w 0x0000_0000 17.4.8/17-15 0x1064 mib control/status register (mibc) 32 r/w 0x0000_0000 17.4.9/17-16 0x1084 receive control register (rcr) 32 r/w 0x05ee_0001 17.4.10/17-16 0x10c4 transmit control regi ster (tcr) 32 r/w 0x0000_0000 17.4.11/17-17 0x10e4 physical address low register (palr) 32 r/w undefined 17.4.12/17-18 0x10e8 physical address high register (paur) 32 r/w see section 17.4.13/17-19 0x10ec opcode/pause duration (opd) 32 r/w see section 17.4.14/17-19 0x1118 descriptor individual upper address register (iaur) 32 r/w undefined 17.4.15/17-20 0x111c descriptor individual lower address register (ialr) 32 r/w undefined 17.4.16/17-20 0x1120 descriptor group upper address register (gaur) 32 r/w undefined 17.4.17/17-21 0x1124 descriptor group lower address register (galr) 32 r/w undefined 17.4.18/17-21 0x1144 transmit fifo watermark (tfwr) 32 r/w 0x0000_0000 17.4.19/17-22 0x114c fifo receive bound register (frbr) 32 r 0x0000_0600 17.4.20/17-22 0x1150 fifo receive fifo start register (frsr) 32 r 0x0000_0500 17.4.21/17-23 0x1180 pointer to receive descriptor ring (erdsr) 32 r/w undefined 17.4.22/17-23 0x1184 pointer to transmit descriptor ring (etdsr) 32 r/w undefined 17.4.23/17-24 0x1188 maximum receive buffer size (emrbr) 32 r/w undefined 17.4.24/17-24 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) freescale semiconductor 17-7 17.4.1 mib block counters memory map the mib counters memory map ( table 17-4 ) defines the locations in the mib ram space where hardware-maintained counters reside. the counters are divided into two groups: ? rmon counters include the ethernet statistics counters defined in rfc 1757 ? a counter is included to count truncated fram es since only frame lengths up to 2047 bytes are supported the transmit and receive rmon counter s are independent, which ensures a ccurate network statistics when operating in full duplex mode. the included ieee counters support the mandatory a nd recommended counter packages defined in section 5 of ansi/ieee std. 802.3 (1998 edition). th e fec supports ieee basic package objects, but these do not require counters in the mib block. in addition, some of the recommended package objects supported do not require mib c ounters. counters for transmit and recei ve full duplex flow control frames are also included. table 17-4. mib counters memory map ipsbar offset register 0x1200 count of frames not counted correctly (rmon_t_drop) 0x1204 rmon tx packet count (rmon_t_packets) 0x1208 rmon tx broadcast packets (rmon_t_bc_pkt) 0x120c rmon tx multicast packets (rmon_t_mc_pkt) 0x1210 rmon tx packets with crc/align error (rmon_t_crc_align) 0x1214 rmon tx packets < 64 bytes, good crc (rmon_t_undersize) 0x1218 rmon tx packets > max_fl bytes, good crc (rmon_t_oversize) 0x121c rmon tx packets < 64 bytes, bad crc (rmon_t_frag) 0x1220 rmon tx packets > max_fl bytes, bad crc (rmon_t_jab) 0x1224 rmon tx collision count (rmon_t_col) 0x1228 rmon tx 64 byte packets (rmon_t_p64) 0x122c rmon tx 65 to 127 byte packets (rmon_t_p65to127) 0x1230 rmon tx 128 to 255 byte packets (rmon_t_p128to255) 0x1234 rmon tx 256 to 511 byte packets (rmon_t_p256to511) 0x1238 rmon tx 512 to 1023 byte packets (rmon_t_p512to1023) 0x123c rmon tx 1024 to 2047 byte packets (rmon_t_p1024to2047) 0x1240 rmon tx packets with > 2048 bytes (rmon_t_p_gte2048) 0x1244 rmon tx octets (rmon_t_octets) 0x1248 count of transmitted frames not counted correctly (ieee_t_drop) 0x124c frames transmitted ok (ieee_t_frame_ok) 0x1250 frames transmitted with single collision (ieee_t_1col) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) 17-8 freescale semiconductor 0x1254 frames transmitted with multiple collisions (ieee_t_mcol) 0x1258 frames transmitted after deferral delay (ieee_t_def) 0x125c frames transmitted with late collisio n (ieee_t_lcol) 0x1260 frames transmitted with e xcessive collisio ns (ieee_t_excol) 0x1264 frames transmitted with tx fifo underrun (ieee_t_macerr) 0x1268 frames transmitted with ca rrier sense error (ieee_t_cserr) 0x126c frames transmitted wi th sqe error (ieee_t_sqe) 0x1270 flow control pause fram es transmitted (ieee_t_fdxfc) 0x1274 octet count for fr ames transmitted without error (ieee_t_octets_ok) 0x1280 count of received frames not counted correctly (rmon_r_drop) 0x1284 rmon rx packet count (rmon_r_packets) 0x1288 rmon rx broadcast packets (rmon_r_bc_pkt) 0x128c rmon rx multicast packets (rmon_r_mc_pkt) 0x1290 rmon rx packets with crc/ align error (rmon_r_crc_align) 0x1294 rmon rx packets < 64 bytes, good crc (rmon_r_undersize) 0x1298 rmon rx packets > max_fl bytes, good crc (rmon_r_oversize) 0x129c rmon rx packets < 64 bytes, bad crc (rmon_r_frag) 0x12a0 rmon rx packets > max_fl bytes, bad crc (rmon_r_jab) 0x12a4 reserved (rmon_r_resvd_0) 0x12a8 rmon rx 64 byte packets (rmon_r_p64) 0x12ac rmon rx 65 to 127 byte packets (rmon_r_p65to127) 0x12b0 rmon rx 128 to 255 byte packets (rmon_r_p128to255) 0x12b4 rmon rx 256 to 511 byte packets (rmon_r_p256to511) 0x12b8 rmon rx 512 to 1023 byte packets (rmon_r_p512to1023) 0x12bc rmon rx 1024 to 2047 byte packets (rmon_r_p1024to2047) 0x12c0 rmon rx packets with > 2048 bytes (rmon_r_p_gte2048) 0x12c4 rmon rx octets (rmon_r_octets) 0x12c8 count of received frames not counted correctly (ieee_r_drop) 0x12cc frames received ok (ieee_r_frame_ok) 0x12d0 frames received with crc error (ieee_r_crc) 0x12d4 frames received with alignment error (ieee_r_align) 0x12d8 receive fifo overflow count (ieee_r_macerr) table 17-4. mib counters memory map (continued) ipsbar offset register mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) freescale semiconductor 17-9 17.4.2 ethernet interrupt event register (eir) when an event occurs that sets a bit in eir, an in terrupt occurs if the corresponding bit in the interrupt mask register (eimr) is also set. writing a 1 to an eir bit clears it; writing 0 has no effect. this register is cleared upon hardware reset. these interrupts can be divided into operational inte rrupts, transceiver/networ k error interrupts, and internal error interrupts. interrupt s which may occur in nor mal operation are gra, txf, txb, rxf, rxb, and mii. interrupts resulting from er rors/problems detected in the ne twork or transceiver are hberr, babr, babt, lc, and rl. interrupts resulting from internal errors are hberr and un. some of the error interrupts are independe ntly counted in the mib block counters: ? hberr - ieee_t_sqe ? babr - rmon_r_oversize (good crc), rmon_r_jab (bad crc) ? babt - rmon_t_oversize (good crc), rmon_t_jab (bad crc) ? late_col - ieee_t_lcol ? col_retry_lim - ieee_t_excol ? xfifo_un - ieee_t_macerr software may choose to mask off these interrupts becaus e these errors are visibl e to network management via the mib counters. 0x12dc flow control pause fr ames received (ieee_r_fdxfc) 0x12e0 octet count for frames rece ived without error (ieee_r_octets_ok) ipsbar offset: 0x1004 access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 rhb err babr babt gra txf txb rxf rxb mii eb err lc rl un 000 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 000000000 0 000000 w reset0000000000000000 figure 17-2. ethernet interrupt event register (eir) table 17-4. mib counters memory map (continued) ipsbar offset register mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) 17-10 freescale semiconductor 17.4.3 interrupt mask register (eimr) the eimr register controls which interrupt events are allowed to generate actual interrupts. all implemented bits in this csr are read/write. a hardwa re reset clears this regist er. if the corresponding bits in the eir and eimr registers are se t, an interrupt is generated. the in terrupt signal remain s asserted until a 1 is written to the eir bit (write 1 to clear) or a 0 is written to the eimr bit. table 17-5. eir field descriptions field description 31 hberr heartbeat error. indicates tcr[hbc] is set and that th e col input was not asserted within the heartbeat window following a transmission. 30 babr babbling receive error. indicates a frame was received with length in excess of rcr[max_fl] bytes. 29 babt babbling transmit error. indicates the transmitted frame le ngth exceeds rcr[max_fl] bytes. usually this condition is caused by a frame that is too long is placed into the transmit data buffer(s). truncation does not occur. 28 gra graceful stop complete. indicates the graceful stop is complete. during graceful stop the transmitter is placed into a pause state after completion of the fr ame currently being transmitted. this bi t is set by one of three conditions: 1) a graceful stop initiated by the sett ing of the tcr[gts] bit is now complete. 2) a graceful stop initiated by the setting of the tcr[tfc_pause] bit is now complete. 3) a graceful stop initiated by the re ception of a valid full duplex flow control pause frame is now complete. refer to section 17.5.11, ?full duplex flow control.? 27 txf transmit frame interrupt. indicates a frame has been trans mitted and the last corresponding buffer descriptor has been updated. 26 txb transmit buffer interrupt. indicates a transmit buffer descriptor has been updated. 25 rxf receive frame interrupt. indicates a frame has been received and the last corresponding buffer descriptor has been updated. 24 rxb receive buffer interrupt. indicates a receive buffer descriptor not the last in the frame has been updated. 23 mii mii interrupt. indicates the mii has completed the data transfer requested. 22 eberr ethernet bus error. indicates a system bus error occurr ed when a dma transaction is underway. when the eberr bit is set, ecr[ether_en] is cleared, halting frame proc essing by the fec. when this occurs, software needs to ensure that the fifo controller and dma also soft reset. 21 lc late collision. indicates a collision occurred beyond the collision window (slot time) in half duplex mode. the frame truncates with a bad crc and the re mainder of the frame is discarded. 20 rl collision retry limit. indicates a collisi on occurred on each of 16 successive attempts to transmit the frame. the frame is discarded without being transmitted and transmission of th e next frame commences. this error can only occur in half duplex mode. 19 un transmit fifo underrun. indicates the transmit fifo bec ame empty before the complete frame was transmitted. a bad crc is appended to the frame fragment and the remainder of the frame is discarded. 18?0 reserved, must be cleared. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) freescale semiconductor 17-11 17.4.4 receive descriptor active register (rdar) rdar is a command register, writte n by the user, indicating the receive descriptor ring is updated (the driver produced empty receive buffers with the empty bit set). when the register is written, the rdar bit is set. th is is independent of the data actually written by the user. when set, the fec polls the receive descript or ring and processes re ceive frames (provided ecr[ether_en] is also set) . after the fec polls a receive descript or whose empty bit is not set, fec clears the rdar bit and ceas es receive descriptor ring polling until the user sets the bit again, signifying that additional descriptor s are placed into the receive descriptor ring. the rdar register is cleared at rese t and when ecr[ether_en] is cleared. ipsbar offset: 0x1008 access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r hb err babr babt gra txf txb rxf rxb mii eb err lc rl un 000 w reset0000000000000000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 000000000 0 000000 w reset0000000000000000 figure 17-3. ethernet interrupt mask register (eimr) table 17-6. eimr field descriptions field description 31?19 see figure 17-3 and ta bl e 1 7 - 5 interrupt mask. each bit corresponds to an interrupt source defined by the eir register. the corresponding eimr bit determines whether an interrupt condition can g enerate an interrupt. at every processor clock, the eir samples the signal generated by the interrupting s ource. the corresponding eir bit reflects the state of the interrupt signal even if the corresponding eimr bit is set. 0 the corresponding interrupt source is masked. 1 the corresponding interrupt source is not masked. 18?0 reserved, must be cleared. ipsbar offset: 0x1010 access: user read/write 31302928272625 24 23222120191817161514131211109876543210 r0000000 rdar 00000 0 0 0000000000 0000000 w reset0000000 0 000000000000000000000000 figure 17-4. receive descriptor active register (rdar) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) 17-12 freescale semiconductor 17.4.5 transmit descriptor active register (tdar) the tdar is a command regi ster which the user writes to indicate the transm it descriptor ring is updated (transmit buffers have been produced by the driver with the ready bi t set in the buffer descriptor). when the register is written, the tdar bit is set. this value is independent of th e data actually written by the user. when set, the fec polls the transmit descri ptor ring and processes tr ansmit frames (provided ecr[ether_en] is also set) . after the fec polls a tran smit descriptor that is a ready bit not set, fec clears the tdar bit and cease s transmit descriptor ri ng polling until the user sets the bit again, signifying additional descriptors are placed in to the transmit descriptor ring. the tdar register is cleared at reset, when ecr[ether_en] is clea red, or when ecr[reset] is set. 17.4.6 ethernet control register (ecr) ecr is a read/write user register, though hardware ma y alter fields in this register as well. the ecr enables/disables the fec. table 17-7. rdar field descriptions field description 31?25 reserved, must be cleared. 24 rdar set to 1 when this register is written, regardless of the value written. cleared by the fec device when no additional empty descriptors remain in the receive ring. also cleared when ecr[ether_en] is cleared. 23?0 reserved, must be cleared. ipsbar offset: 0x1014 access: user read/write 31302928272625 24 23222120191817161514131211109876543210 r0000000 tdar 00000 0 0 0000000000 0000000 w reset0000000 0 000000000000000000000000 figure 17-5. transmit descriptor active register (tdar) table 17-8. tdar field descriptions field description 31?25 reserved, must be cleared. 24 tdar set to 1 when this register is written, regardless of the value written. cleared by the fec device when no additional ready descriptors remain in the transmit ring . also cleared when ecr[ether_en] is cleared. 23?0 reserved, must be cleared. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) freescale semiconductor 17-13 17.4.7 mii management frame register (mmfr) the mmfr is user-accessible and does not reset to a defined value. the mmfr register is used to communicate with the attached mii compatible phy de vice(s), providing read/write access to their mii registers. performing a write to th e mmfr causes a manageme nt frame to be source d unless the mscr is programmed to 0. if mscr is cleared while mmfr is written and then mscr is wr itten with a non-zero value, an mii frame is generated with the data previously written to the mmfr. this allows mmfr and mscr to be programmed in either or der if mscr is currently zero. ipsbar offset: 0x1024 access: user read/write 3130292827262524232221201918171615141312111098765432 1 0 r1111000000000 0 0 0000000000 00000 ether _en reset w reset111100000000000000000000000000 0 0 figure 17-6. ethernet control register (ecr) table 17-9. ecr field descriptions field description 31?2 reserved, must be cleared. 1 ether_en when this bit is set, fec is enabled, and reception an d transmission are possible. when this bit is cleared, reception immediately stops and transmission stops a fter a bad crc is appended to any currently transmitted frame. the buffer descriptor(s) for an aborted transmit frame are not updated after clearing this bit. when ether_en is cleared, the dma, buffer descriptor, and fifo control logic are reset, including the buffer descriptor and fifo pointers. hardware alters the ether_en bit under the following conditions: ? ecr[reset] is set by software, in which case ether_en is cleared ? an error condition causes the eir[eberr] bi t to set, in which case ether_en is cleared 0 reset when this bit is set, the equivalent of a hardware reset is performed but it is local to the fec. ecr[ether_en] is cleared and all other fec registers take their reset val ues. also, any transmission/reception currently in progress is abruptly aborted. this bit is au tomatically cleared by hardware during the reset sequence. the reset sequence takes approximately eight internal bu s clock cycles after this bit is set. ipsbar offset: 0x1040 access: user read/write 313029282726252423222120191817161514131211109876543210 r st op pa ra ta data w reset???????????????????????????????? figure 17-7. mii management frame register (mmfr) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) 17-14 freescale semiconductor to perform a read or write operation on the mii ma nagement interface, writ e the mmfr register. to generate a valid read or write management frame, st field must be written with a 01 pattern, and the ta field must be written with a 10. if ot her patterns are written to these fi elds, a frame is generated, but does not comply with the ieee 802.3 mii definition. to generate an ieee 802.3-complian t mii management interface write fr ame (write to a phy register), the user must write {01 01 phyad re gad 10 data} to the mmfr regist er. writing this pattern causes the control logic to shift out the da ta in the mmfr register following a preamble generated by the control state machine. during this time, contents of the mmfr register are altered as the contents are serially shifted and are unpredictabl e if read by the user. after the write management frame operation completes, the mii interrupt is generated. at this time, contents of the mmfr register match the original value written. to generate an mii management in terface read frame (read a phy register), the user must write {01 10 phyad regad 10 xxxx} to the mmfr re gister (the content of the data field is a don?t care). writing this pattern causes the control logi c to shift out the data in the mm fr register following a preamble generated by the control state machine. during this time, conten ts of the mmfr register are altered as the contents are serially shifted and are unpredictable if read by the user. after th e read management frame operation completes, the mii interrupt is generated. at this time, the cont ents of the mmfr register match the original value written except for the data fiel d whose contents are replaced by the value read from the phy register. if the mmfr register is written wh ile frame generation is in progress, the frame contents are altered. software must use the mii interrupt to avoid writing to the mmfr register whil e frame generation is in progress. table 17-10. mmfr field descriptions field description 31?30 st start of frame delimiter. these bits must be prog rammed to 0b01 for a valid mii management frame. 29?28 op operation code. 00 write frame operation, but not mii compliant. 01 write frame operation for a valid mii management frame. 10 read frame operation for a valid mii management frame. 11 read frame operation, but not mii compliant. 27?23 pa phy address. this field specifies one of up to 32 attached phy devices. 22?18 ra register address. this field specifies one of up to 32 registers within the specified phy device. 17?16 ta turn around. this field must be programmed to 10 to generate a valid mii management frame. 15?0 data management frame data. this is t he field for data to be written to or read from the phy register. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) freescale semiconductor 17-15 17.4.8 mii speed control register (mscr) the mscr provides control of the mii clock (fec_mdc pi n) frequency and allo ws a preamble drop on the mii management frame. the mii_speed field must be programmed with a valu e to provide an fec_mdc frequency of less than or equal to 2.5 mhz to be compli ant with the ieee 802.3 mii specificat ion. the mii_speed must be set to a non-zero value to source a read or write management frame. after the management frame is complete, the mscr register may optionally be set to 0 to turn off the fec_ mdc. the fec_mdc generated has a 50% duty cycle except when mii_speed changes duri ng operation (change takes effect following a rising or falling edge of fec_mdc). if the internal bus clock is 25 mhz, programmi ng this register to 0x0000_0005 results in an fec_mdc as stated the equation below. eqn. 17-1 a table showing optimum values for mii_speed as a fu nction of internal bus cl ock frequency is provided below. ipsbar offset: 0x1044 access: user read/write 3130292827262524232221201918171615141312111098 7 6543210 r0000000000000 0 0 000000000 dis_ pre mii_speed 0 w reset000000000000000000000000 0 0000000 figure 17-8. mii speed control register (mscr) table 17-11. mscr field descriptions field description 31?8 reserved, must be cleared. 7 dis_pre setting this bit causes the preamble (32 ones) not to be prepended to the mii management frame. the mii standard allows the preamble to be dropped if the attached phy device(s) does not require it. 6?1 mii_speed controls the frequency of the mii management interface cl ock (fec_mdc) relative to the internal bus clock. a value of 0 in this field turns off the fec_mdc and leaves it in low voltage state. any non-zero value results in the fec_mdc frequency of 1/(mii_speed 2) of the internal bus frequency. 0 reserved, must be cleared. table 17-12. programming examples for mscr internal fec clock frequency mscr[mii_speed] fec_mdc frequency 25 mhz 0x5 2.50 mhz 33 mhz 0x7 2.36 mhz 40 mhz 0x8 2.50 mhz 25 mhz 1 52 ----------- - 2.5 mhz = mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) 17-16 freescale semiconductor the mibc is a read/write register controlling and observing the state of the mib block. user software accesses this register if there is a need to disable the mib bloc k operation. for example, to clear all mib counters in ram: 1. disable the mib block 2. clear all the mib ram locations 3. enable the mib block the mib_dis bit is reset to 1. see table 17-4 for the locations of the mib counters. 17.4.10 receive control register (rcr) rcr controls the operational mode of the receive block a nd must be written onl y when ecr[ether_en] is cleared (initi alization time). 50 mhz 0xa 2.50 mhz 66 mhz 0xe 2.36 mhz ipsbar offset: 0x1064 access: user read/write 31 30 29282726252423222120191817161514131211109876543210 r mib_ dis mib_ idle 00000000000 0 0 0000000000 0000000 w reset 1 1 000000000000000000000000000000 figure 17-9. mib control register (mibc) table 17-13. mibc field descriptions field description 31 mib_dis a read/write control bit. if set, the mib logic halts and not update any mib counters. 30 mib_idle a read-only status bit. if set the mib bloc k is not currently updating any mib counters. 29?0 reserved. table 17-12. programming examples for mscr (continued) internal fec clock frequency mscr[mii_speed] fec_mdc frequency 17.4.9 mib control register (mibc) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) freescale semiconductor 17-17 17.4.11 transmit control register (tcr) tcr is read/write and configures the transmit block. this register is cleared at sy stem reset. bits 2 and 1 must be modified only when ecr[ether_en] is cleared. ipsbar offset: 0x1084 access: user read/write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 r 00000 max_fl w reset0000010 1 1110 1 1 10 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r 0000000 0 0 0 fce bc_ rej prom mii_ mode drt loop w reset0000000 0 0000 0 0 01 figure 17-10. r eceive control register (rcr) table 17-14. rcr field descriptions field description 31?27 reserved, must be cleared. 26?16 max_fl maximum frame length. resets to decimal 1518. length is measured starting at da and includes the crc at the end of the frame. transmit frames longer than max_fl causes the babt interrupt to occur. receive frames longer than max_fl causes the babr interrupt to occur and sets the lg bit in the end of frame receive buffer descriptor. the recommended default value to be programmed is 1518 or 1522 if vlan tags are supported. 15?6 reserved, must be cleared. 5 fce flow control enable. if asserted, the receiver detects pause frames. upon pause frame detection, the transmitter stops transmitting data frames for a given duration. 4 bc_rej broadcast frame reject. if asserted, frames with da (desti nation address) equal to f fff_ffff_ffff are rejected unless the prom bit is set. if bc_rej and prom are se t, frames with broadcast da are accepted and the m (miss) is set in the receive buffer descriptor. 3 prom promiscuous mode. all frames are accepted regardless of address matching. 2 mii_mode media independent interface mode. selects the external interface mode for transmit and receive blocks. 0 7-wire mode (used only for serial 10 mbps) 1 mii mode 1 drt disable receive on transmit. 0 receive path operates independently of transmit (use for full duplex or to monitor transmit activity in half duplex mode). 1 disable reception of frames while transmitting (normally used for half duplex mode). 0 loop internal loopback. if set, transmitted frames are looped back internal to the device and transmit output signals are not asserted. the internal bus clock substitutes for the fec_txclk when loop is asserted. drt must be set to 0 when setting loop. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) 17-18 freescale semiconductor 17.4.12 physical address lower register (palr) palr contains the lower 32 bits (bytes 0,1,2,3) of the 48-bit address used in the address recognition process to compare with the da (destination address) field of receive frames with an individual da. in addition, this register is used in bytes 0 through 3 of the 6-byte sour ce address field when transmitting pause frames. this register is not reset and you must initialize it. ipsbar offset: 0x10c4 access: user read/write 3130292827262524232221201918171615141312111098765 4 3 2 1 0 r 0000000000000 0 0 0000000000 00 rfc_ pau s e tfc_ pau s e fden hbc gts w reset000000000000000000000000000 0 0 0 0 0 figure 17-11. transmit control register (tcr) table 17-15. tcr field descriptions field description 31?5 reserved, must be cleared. 4 rfc_pause receive frame control pause. this read -only status bit is asserted when a fu ll duplex flow control pause frame is received and the transmitter pauses for the duration defined in this pause frame. this bit automatically clears when the pause duration is complete. 3 tfc_pause transmit frame control pause. transmits a pause frame when asserted. when this bit is set, the mac stops transmission of data frames after the current transmission is complete. at this time, gra interrupt in the eir register is asserted. with transmission of data fram es stopped, mac transmits a mac control pause frame. next, the mac clears the tfc_pause bit and resumes tran smitting data frames. if the transmitter pauses due to user assertion of gts or reception of a pause fr ame, the mac may continue transmitting a mac control pause frame. 2 fden full duplex enable. if set, frames transmit independent of carrier sense and collision inputs. this bit should only be modified when ecr[ether_en] is cleared. 1 hbc heartbeat control. if set, the heartbeat check performs following end of transmission and the hb bit in the status register is set if the collision input does not assert within the heartbeat window. this bit should only be modified when ecr[ether_en] is cleared. 0 gts graceful transmit stop. when this bit is set, mac st ops transmission after any fr ame currently transmitted is complete and gra interrupt in the eir register is assert ed. if frame transmission is not currently underway, the gra interrupt is asserted immediately. after transmission finishes, clear gts to restart. the next frame in the transmit fifo is then transmitted. if an early collision o ccurs during transmission when gts is set, transmission stops after the collision. the frame is transmitted again after gts is cleared. there may be old frames in the transmit fifo that transmit when gt s is reasserted. to avoid this, clear ecr[ether_en] following the gra interrupt. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) freescale semiconductor 17-19 17.4.13 physical address upper register (paur) paur contains the upper 16 bits (bytes 4 and 5) of the 48-bit a ddress used in the address recognition process to compare with the da (destination address) field of receive frames with an individual da. in addition, this register is used in bytes 4 and 5 of the 6- byte source address field when transmitting pause frames. bits 15:0 of paur contain a constant type field (0x8808) for transmission of pause frames. the upper 16 bits of this register are not reset and you must initialize it. 17.4.14 opcode/pause duration register (opd) the opd is read/write accessible. th is register contains the 16-bit opcode and 16-bit pause duration fields used in transmission of a pause frame. the opcode field is a constant value, 0x0001. when another node detects a pause frame, that node pauses transmissi on for the duration specified in the pause duration field. the lower 16 bits of this register are not reset and you must initialize them. ipsbar offset: 0x10e4 access: user read/write 313029282726252423222120191817161514131211109876543210 r paddr1 w reset???????????????????????????????? figure 17-12. physical address lower register (palr) table 17-16. palr field descriptions field description 31?0 paddr1 bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8), and 3 (bit s 7:0) of the 6-byte individual address are used for exact match and the source address field in pause frames. ipsbar offset: 0x10e8 access: user read/write 313029282726252423222120191817161514131211109876543210 r paddr2 type w reset???????????????? 1 0 0 0100000001000 figure 17-13. physical address upper register (paur) table 17-17. paur field descriptions field description 31?16 paddr2 bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match, and the source address field in pause frames. 15?0 type type field in pause frames. these 16 read-only bits are a constant value of 0x8808. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) 17-20 freescale semiconductor 17.4.15 descriptor individual upper address register (iaur) iaur contains the upper 32 bits of the 64-bit indi vidual address hash table. the address recognition process uses this table to check fo r a possible match with the destinat ion address (da) field of receive frames with an individual da. this regist er is not reset and you must initialize it. 17.4.16 descriptor individual lower address register (ialr) ialr contains the lower 32 bits of the 64-bit individual address hash table. the address recognition process uses this table to check fo r a possible match with the da field of receive frames with an individual da. this register is not rese t and you must initialize it. ipsbar offset: 0x10ec access: user read/write 313029282726252423222120191817161514131211109876543210 ro p c o d e pause_dur w reset0000000000000001??? ????????????? figure 17-14. opcode/pause duration register (opd) table 17-18. opd field descriptions field description 31?16 opcode opcode field used in pause frames. these read-only bits are a constant, 0x0001. 15?0 pause_dur pause duration field used in pause frames. ipsbar offset: 0x1118 access: user read/write 313029282726252423222120191817161514131211109876543210 r iaddr1 w reset???????????????????????????????? figure 17-15. descriptor individua l upper address register (iaur) table 17-19. iaur field descriptions field description 31?0 iaddr1 the upper 32 bits of the 64-bit hash table used in the addres s recognition process for receive frames with a unicast address. bit 31 of iaddr1 contains hash index bi t 63. bit 0 of iaddr1 contains hash index bit 32. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) freescale semiconductor 17-21 17.4.17 descriptor group upper address register (gaur) gaur contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address. you must initialize this register. 17.4.18 descriptor group lower address register (galr) galr contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address. you must initialize this register. ipsbar offset: 0x111c access: user read/write 313029282726252423222120191817161514131211109876543210 r iaddr2 w reset???????????????????????????????? figure 17-16. descriptor individual lower address register (ialr) table 17-20. ialr field descriptions field description 31?0 iaddr2 the lower 32 bits of the 64-bit hash table used in the ad dress recognition process for receive frames with a unicast address. bit 31 of iaddr2 contains hash index bi t 31. bit 0 of iaddr2 contains hash index bit 0. ipsbar offset: 0x1120 access: user read/write 313029282726252423222120191817161514131211109876543210 r gaddr1 w reset???????????????????????????????? figure 17-17. descriptor group upper address register (gaur) table 17-21. gaur field descriptions field description 31?0 gaddr1 the gaddr1 register contains the upper 32 bits of the 64 -bit hash table used in the address recognition process for receive frames with a multicast address. bit 31 of gaddr1 contains hash index bit 63. bit 0 of gaddr1 contains hash index bit 32. ipsbar offset: 0x1124 access: user read/write 313029282726252423222120191817161514131211109876543210 r gaddr2 w reset???????????????????????????????? figure 17-18. descriptor group lower address register (galr) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) 17-22 freescale semiconductor 17.4.19 transmit fifo watermark register (tfwr) the tfwr controls the amount of da ta required in the transmit fifo before transmission of a frame can begin. this allows you to minimize transmit latency (tfwr = 00 or 01) or allow for larger bus access latency (tfwr = 11) due to contention for the sy stem bus. setting the watermark to a high value minimizes the risk of transmit fifo underrun due to contention for the system bus. the byte counts associated with the tfwr field may need to be modified to match a gi ven system requirement (worst case bus access latency by the tran smit data dma channel). 17.4.20 fifo receive bound register (frbr) frbr indicates the upper address bound of the fifo ra m. drivers can use this value, along with the frsr, to appropriately divide the available fifo ram between the transmit and receive data paths. table 17-22. galr field descriptions field description 31?0 gaddr2 the gaddr2 register contains the lower 32 bits of the 64- bit hash table used in the address recognition process for receive frames with a multicast address. bit 31 of gaddr2 contains hash index bit 31. bit 0 of gaddr2 contains hash index bit 0. ipsbar offset: 0x1144 access: user read/write 3130292827262524232221201918171615141312111098765432 1 0 r0000000000000 0 0 0000000000 00000 tfwr w reset000000000000000000000000000000 0 0 figure 17-19. transmit fifo watermark register (tfwr) table 17-23. tfwr field descriptions field description 31?2 reserved, must be cleared. 1?0 tfwr number of bytes written to transmit fi fo before transmission of a frame begins 00 64 bytes written 01 64 bytes written 10 128 bytes written 11 192 bytes written ipsbar offset: 0x114c access: user read-only 3130292827262524232221201918171615141312111098765432 1 0 r0000000000000 0 0 0000001 r_bound 0 0 w reset000000000000000000000110000000 0 0 figure 17-20. fifo receiv e bound register (frbr) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) freescale semiconductor 17-23 17.4.21 fifo receive start register (frsr) frsr indicates the starting addre ss of the receive fifo. frsr marks the boundary between the transmit and receive fifos. the tran smit fifo uses addresses from the start of the fifo to the location four bytes before the address programmed into the frsr. the receive fifo uses addresses from frsr to frbr inclusive. hardware initializes the frsr register at reset. frsr only needs to be written to change the default value. 17.4.22 receive descriptor ring start register (erdsr) erdsr points to the start of the ci rcular receive buffer desc riptor queue in external memory. this pointer must be 32-bit aligned; however, it is recommended it be made 128-bi t aligned (evenly divisible by 16). this register is not reset and must be initialized pr ior to operation. table 17-24. frbr field descriptions field description 31?10 reserved, read as 0 (except bit 10, which is read as 1). 9?2 r_bound read-only. highest valid fifo ram address. 1?0 reserved, read as 0. ipsbar offset: 0x1150 access: user read/write 3130292827262524232221201918171615141312111098765432 1 0 r0000000000000 0 0 0000001 r_fstart 00 w reset000000000000000000000101000000 0 0 figure 17-21. fifo receive start register (frsr) table 17-25. frsr field descriptions field description 31?11 reserved, must be cleared. 10 reserved, must be set. 9?2 r_fstart address of first receive fifo location. acts as delim iter between receive and transmit fifos. for proper operation, ensure that r_fstart is set to 0x48 or greater. 1?0 reserved, must be cleared. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) 17-24 freescale semiconductor 17.4.23 transmit buffer descriptor ring start registers (etsdr) etsdr provides a pointer to the start of the circular transmit buffer desc riptor queue in external memory. this pointer must be 32-bit aligned; however, it is recommended it be ma de 128-bit aligned (evenly divisible by 16). you should wr ite zeros to bits 1 and 0. hardware ignores non-zero values in these two bit positions. this register is undefined at reset and must be initialized prior to operation. 17.4.24 receive buffer size register (emrbr) the emrbr is a user-programmable register that dict ates the maximum size of all receive buffers. this value should take into consideration th at the receive crc is al ways written into the last receive buffer. to allow one maximum size frame per buf fer, emrbr must be set to rcr[ max_fl] or larger. to properly align the buffer, emrbr must be evenly divisibl e by 16. to ensure this, bits 3?0 are forced low. ipsbar offset: 0x1180 access: user read/write 3130292827262524232221201918171615141312111098765432 1 0 r r_des_start 00 w reset?????????????????????????????? ? ? figure 17-22. ethernet receive descriptor ring start register (erdsr) table 17-26. erdsr field descriptions field description 31?2 r_des_start pointer to start of receive buffer descriptor queue. 1?0 reserved, must be cleared. ipsbar offset: 0x1184 access: user read/write 3130292827262524232221201918171615141312111098765432 1 0 r x_des_start 00 w reset?????????????????????????????? ? ? figure 17-23. transmit buffer descriptor ring start register (etdsr) table 17-27. etdsr field descriptions field description 31?2 x_des_start pointer to start of transmit buffer descriptor queue. 1?0 reserved, must be cleared. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) freescale semiconductor 17-25 to minimize bus utilization (descripto r fetches), it is recommended that emrbr be greater than or equal to 256 bytes. the emrbr register is undefined at rese t and must be initialized by the user. 17.5 functional description this section describes the operation of the fec, beginning with the buf fer descriptors, the hardware and software initialization sequence, then the software (ethernet driver) interface for transmitting and receiving frames. following the software initializati on and operation sections are secti ons providing a detailed description of the functions of the fec. 17.5.1 buffer descriptors this section provides a description of the operation of the driver/dma via the buf fer descriptors. it is followed by a detailed description of the receive and transmit descriptor fields. 17.5.1.1 driver/dma operation with buffer descriptors the data for the fec frames resides in one or more me mory buffers external to the fec. associated with each buffer is a buffer descriptor (bd), which contains a starting address (32-bit aligned pointer), data length, and status/control informati on (which contains the current st ate for the buffer). to permit maximum user flexibility, the bds are also located in external memory and are read by the fec dma engine. ipsbar offset: 0x1188 access: user read/write 3130292827262524232221201918171615141312111098765432 1 0 r0000000000000 0 0 000000 r_buf_size 00 0 0 w reset?????????????????????????????? ? ? figure 17-24. receive buffer size register (emrbr) table 17-28. emrbr field descriptions field description 31?11 reserved, must be cleared. 10?4 r_buf_size maximum size of receive buffer size in bytes. to minimize bus utilization (descriptor fetches), set this field to 256 bytes (0x10) or larger. 0x10 256 + 15 bytes (minimum size recommended) 0x11 272 + 15 bytes ... 0x7f 2032 + 15 bytes. the fec writes up to 2047 bytes in the receive buffer. if data larger than 2047 is received, the fec truncates it and shows 0x7ff in the receive descriptor 3?0 reserved, must be cleared. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) 17-26 freescale semiconductor software produces buffers by allocati ng/initializing memory and initializi ng buffer descriptors. setting the rxbd[e] or txbd[r] bit produces the buffer. software writing to tdar or rdar tells the fec that a buffer is placed in external memory for the transmit or receive data traffic, respectively. the hardware reads the bds and consumes the buffers after they ha ve been produced. after the data dma is complete and the dma engine writes the buffer descriptor stat us bits, hardware clears rxbd[e] or txbd[r] to signal the buffer has been consumed. software may poll the bds to detect when the buffers are consumed or may rely on the buffer/frame interr upts. the driver may process these buf fers, and they can return to the free list. the ecr[ether_en] bit operates as a reset to the bd/dma logic. when ecr[ether_en] is cleared, the dma engine bd pointers are reset to point to the starting transmit and receive bds. the buffer descriptors are not in itialized by hardware during re set. at least one transmit a nd receive buffer descriptor must be initialized by software before ecr[ether_en] is set. the buffer descriptors operate as tw o separate rings. erdsr defines th e starting address for receive bds and etdsr defines the starting addr ess for transmit bds. the wrap (w) bit defines the last buffer descriptor in each ring. when w is set, the next de scriptor in the ring is at the location pointed to by erdsr and etdsr for the receive and transmit rings, respectively. buffer descriptor rings must start on a 32-bit boundary; however, it is recommended they are made 128-bit aligned. 17.5.1.1.1 driver/dma operation with transmit bds typically, a transmit frame is divided between multiple buffers. an example is to have an application payload in one buffer, tcp header in a second buffer, ip header in a third buffer, and ethernet/ieee 802.3 header in a fouth buffer. the ethe rnet mac does not prepend the ethern et header (destination address, source address, length/t ype field(s)), so the driver must provide this in one of the transmit buffers. the ethernet mac can append the ethernet crc to the fr ame. txbd[tc], which must be set by the driver, determines whether the mac or driver appends the crc. the driver (txbd software producer) should set up tx bds so a complete transmit frame is given to the hardware at once. if a transmit frame consists of th ree buffers, the bds should be initialized with pointer, length, and control (w, l, tc, abc) and then the tx bd[r] bit should be set in reverse order (third, second, then first bd) to ensure th at the complete frame is ready in memory before the dma begins. if the txbds are set up in order, the dma controller could dma the first bd before the second was made available, potentially caus ing a transmit fifo underrun. in the fec, the driver notifies the dma that new transmit frame(s) are av ailable by writing to tdar. when this register is written to (d ata value is not significant) the fec, risc tells the dma to read the next transmit bd in the ring. after star ted, the risc + dma continues to re ad and interpret transmit bds in order and dma the associated buffers until a transmit bd is encountered with the r bit cleared. at this point, the fec polls this bd one more time. if the r b it is cleared the second time , risc stops the transmit descriptor read proce ss until software sets up another transmit frame and writes to tdar. when the dma of each transmit buffer is complete, the dma writes back to the bd to clear the r bit, indicating that the hardware consum er is finished with the buffer. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) freescale semiconductor 17-27 17.5.1.1.2 driver/dma oper ation with receive bds unlike transmit, the length of the receive frame is unknown by the driver ahead of time. therefore, the driver must set a variable to define the length of all r eceive buffers. in the fec, this variable is written to the emrbr register. the driver (rxbd software producer) should set up some number of empt y buffers for the ethernet by initializing the address field and the e and w bits of the associated receive bds. the hardware (receive dma) consumes these buffers by filling them with data as frames are received and clearing the e bit and writing to the l bit (1 indicates last buffer in frame), the frame status b its (if l is set), and the length field. if a receive frame spans multiple rece ive buffers, the l bit is only set for the last buffer in the frame. for non-last buffers, the length field in the receive bd is written by the dma (at the same time the e bit is cleared) with the default receive buf fer length value. for e nd-of-frame buffers, the receive bd is written with l set and information written to the status bits (m, bc, mc, lg, no , cr, ov, tr). some of the status bits are error indicators wh ich, if set, indicate the r eceive frame should be discarded and not given to higher layers. the frame status/length inform ation is written into the receive fi fo following the end of the frame (as a single 32-bit word) by the receive logic. the lengt h field for the end of frame buffer is written with the length of the entire frame, not only the length of the last buffer. for simplicity, the driver may assign a large enough de fault receive buffer length to contain an entire frame, keeping in mind that a malfunction on the netw ork or out-of-spec implementation could result in giant frames. frames of 2k (2048) bytes or larger ar e truncated by the fec at 2047 bytes so software never sees a receive frame larger than 2047 bytes. similar to transmit, the fec polls the receive descriptor ring after the driver sets up receive bds and writes to the rdar register. as fr ames are received, the fec fills receive buffers and updates the associated bds, then reads the next bd in the receive descriptor ri ng. if the fec reads a receive bd and finds the e bit cleared, it polls this bd once more. if rxbd[e] is clear a second time, fec stops reading receive bds until the driver writes to rdar. 17.5.1.2 ethernet receive bu ffer descriptor (rxbd) in the rxbd, the user initializes the e and w bits in the first longword and the pointer in the second longword. when the buffer ha s been dma?d, the ethernet controller modifies the e, l, m, bc, mc, lg, no, cr, ov, and tr bits an d writes the length of the used portion of the buff er in the first longword. the m, bc, mc, lg, no, cr, ov, and tr bits in the first longword of the buffer descriptor are only modified by the ethernet controller when the l bit is set. 1514131211109876543210 offset + 0 e ro1 w ro2 l ? ? m bc mc lg no ? cr ov tr offset + 2 data length offset + 4 rx data buffer pointer - a[31:16] offset + 6 rx data buffer pointer - a[15:0] figure 17-25. receive buffer descriptor (rxbd) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) 17-28 freescale semiconductor table 17-29. receive buffer descriptor field definitions word field description offset + 0 15 e empty. written by the fec (=0) and user (=1). 0 the data buffer associated with this bd is fille d with received data, or data reception has aborted due to an error condition. the status and lengt h fields have been updated as required. 1 the data buffer associated with this bd is empty, or reception is currently in progress. offset + 0 14 ro1 receive software ownership. this field is reserved for use by software. this read/write bit is not modified by hardware, nor does its value affect hardware. offset + 0 13 w wrap. written by user. 0 the next buffer descriptor is found in the consecutive location 1 the next buffer descriptor is found at the location defined in erdsr. offset + 0 12 ro2 receive software ownership. this field is reserved for use by software. this read/write bit is not modified by hardware, nor does its value affect hardware. offset + 0 11 l last in frame. written by the fec. 0 the buffer is not the last in a frame. 1 the buffer is the last in a frame. offset + 0 10?9 reserved, must be cleared. offset + 0 8 m miss. written by the fec. this bit is set by th e fec for frames accepted in promiscuous mode, but flagged as a miss by the internal address recogniti on. therefore, while in promiscuous mode, you can use the m-bit to quickly determine whether the frame was destined to this station. this bit is valid only if the l-bit is set and the prom bit is set. 0 the frame was received because of an address recognition hit. 1 the frame was received because of promiscuous mode. offset + 0 7 bc set if the da is broadcast (ffff_ffff_ffff). offset + 0 6 mc set if the da is multicast and not bc. offset + 0 5 lg rx frame length violation. written by the fec. a frame length greater than rcr[max_fl] was recognized. this bit is valid only if the l-bit is set. the receive data is not altered in any way unless the length exceeds 2047 bytes. offset + 0 4 no receive non-octet aligned frame. written by the fe c. a frame that contained a number of bits not divisible by 8 was received, and the crc check that occurred at the preceding byte boundary generated an error. this bit is valid only if the l-bit is set. if this bit is set, the cr bit is not set. offset + 0 3 reserved, must be cleared. offset + 0 2 cr receive crc error. written by the fec. this frame contains a crc error and is an integral number of octets in length. this bit is valid only if the l-bit is set. offset + 0 1 ov overrun. written by the fec. a receive fifo overr un occurred during frame reception. if this bit is set, the other status bits, m, lg, no, cr, and cl lose their normal meaning and are zero. this bit is valid only if the l-bit is set. offset + 0 0 tr set if the receive frame is truncated (frame length > 2047 bytes). if the tr bit is set, the frame must be discarded and the other error bits must be ignored as they may be incorrect. offset + 2 15?0 data length data length. written by the fec. data length is th e number of octets written by the fec into this bd?s data buffer if l equals 0 (the value is equal to emrbr), or the length of the frame including crc if l is set. it is written by the fec once as the bd is closed. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) freescale semiconductor 17-29 note when the software driver sets an e bit in one or more receive descriptors, the driver should follow with a write to rdar. 17.5.1.3 ethernet transmit buffer descriptor (txbd) data is presented to the fec for transmission by arrangi ng it in buffers referenced by the channel?s txbds. the ethernet controller confirms transmission by clearing the ready bit (txbd[r]) when dma of the buffer is complete. in the txbd, the user initializes th e r, w, l, and tc bits and the length (in bytes) in the first longword and the buffe r pointer in the second longword. the fec clears the r bit when the buff er is transferred. status bits for the buffer/frame are not included in the transmit buffer descriptors. tran smit frame status is indicated vi a individual interrupt bits (error conditions) and in st atistic counters in the mib block. see section 17.4.1, ?mib bloc k counters memory map,? for more details. 0ffset + 4 15?0 a[31:16] rx data buffer pointer, bits [31:16] 1 offset + 6 15?0 a[15:0] rx data buffer pointer, bits [15:0] 1 the receive buffer pointer, containing the address of the a ssociated data buffer, must always be evenly divisible by 16. the buffer must reside in memory external to the fec. the ethernet controller never modifies this value. 1514131211109876543210 offset+0rto1wto2ltcabc????????? offset + 2 data length offset + 4 tx data buffer pointer - a[31:16] offset + 6 tx data buffer pointer - a[15:0] figure 17-26. transmit buffer descriptor (txbd) table 17-30. transmit buffer descriptor field definitions word field description offset + 0 15 r ready. written by the fec and you. 0 the data buffer associated with this bd is not ready for transmission. you are free to manipulate this bd or its associated data buffer. the fec clears this bit after the buffer has been transmitted or after an error condition is encountered. 1 the data buffer, prepared for transmission by you, has not been transmitted or currently transmits. you may write no fields of this bd after this bit is set. offset + 0 14 to1 transmit software ownership. this field is reserved for software use. this read/write bit is not modified by hardware nor does its value affect hardware. table 17-29. receive buffer descriptor field definitions (continued) word field description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) 17-30 freescale semiconductor note after the software driver has set up th e buffers for a fram e, it should set up the corresponding bds. the last step in setting up the bds for a transmit frame is setting the r bit in the first bd for the frame. the driver must follow that with a write to tdar that triggers the fec to poll the next bd in the ring. 17.5.2 initialization sequence this section describes which regist ers are reset due to hardware rese t, which are reset by the fec risc, and what locations you must ini tialize prior to enabling the fec. 17.5.2.1 hardware controlled initialization in the fec, hardware resets regist ers and control logic that generate interrupts. a hardware reset negates output signals and resets ge neral configuration bits. offset + 0 13 w wrap. written by user. 0 the next buffer descriptor is found in the consecutive location 1 the next buffer descriptor is found at the location defined in etdsr. offset + 0 12 to2 transmit software ownership. this field is reserved for use by software. this read/write bit is not modified by hardware nor does its value affect hardware. offset + 0 11 l last in frame. written by user. 0 the buffer is not the last in the transmit frame 1 the buffer is the last in the transmit frame offset + 0 10 tc transmit crc. written by user (only valid if l is set). 0 end transmission immediately after the last data byte 1 transmit the crc sequence after the last data byte offset + 0 9 abc append bad crc. written by user (only valid if l is set). 0 no effect 1 transmit the crc sequence inverted after the last data byte (regardless of tc value) offset + 0 8?0 reserved, must be cleared. offset + 2 15?0 data length data length, written by user. data length is the number of octets the fec shoul d transmit from this bd?s data buffer. it is never modified by the fec. offset + 4 15?0 a[31:16] tx data buffer pointer, bits [31:16] 1 offset + 6 15?0 a[15:0] tx data buffer pointer, bits [15:0] 1 the transmit buffer pointer, containing the address of the associat ed data buffer, must always be evenly divisible by 4. the buffer must reside in memory extern al to the fec. this value is neve r modified by the ethernet controller. table 17-30. transmit buffer descri ptor field definitions (continued) word field description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) freescale semiconductor 17-31 other registers reset when the ecr[ ether_en] bit is cleared (which is accomplished by a hard reset or software to halt operation). by cl earing ecr[ether_en], configurati on control registers such as the tcr and rcr are not reset, but the entire data path is reset. 17.5.3 user initialization (pri or to setting ecr[ether_en]) you need to initialize portions th e fec prior to setting the ecr[ether _en] bit. the ex act values depend on the particular application. the sequence is not important. table 17-32 defines ethernet mac registers requiring initialization. table 17-33 defines fec fifo/dma register s that require initialization. table 17-31. ecr[ether_en] de-assertion effect on fec register/machine reset value xmit block transmission is aborted (bad crc appended) recv block receive activity is aborted dma block all dma activity is terminated rdar cleared tdar cleared descriptor controller block halt operation table 17-32. user initialization (before ecr[ether_en]) description initialize eimr clear eir (write 0xffff_ffff) tfwr (optional) ialr / iaur gaur / galr palr / paur (only needed for full duplex flow control) opd (only needed for full duplex flow control) rcr tcr mscr (optional) clear mib_ram table 17-33. fec user initialization (before ecr[ether_en]) description initialize frsr (optional) initialize emrbr initialize erdsr initialize etdsr mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) 17-32 freescale semiconductor 17.5.4 microcontroller initialization in the fec, the descriptor control risc initializes some registers after ec r[ether_en] is asserted. after the microcontroller initia lization sequence is complete, ha rdware is ready for operation. table 17-34 shows microcontroller initialization operations. 17.5.5 user initialization (a fter setting ecr[ether_en]) after setting ecr[ether_en], you can set up the buf fer/frame descriptors and write to tdar and rdar. refer to section 17.5.1, ?buffer descriptors,? for more details. 17.5.6 network interface options the fec supports an mii interface for 10/100 mbps ethe rnet and a 7-wire serial interface for 10 mbps ethernet. the rcr[mii_mode] bit select the inte rface mode. in mii mode (rcr[mii_mode] set), there are 18 signals defined by the ieee 802.3 standard and supported by the emac. table 17-35 shows these signals. initialize (empty) transmit descriptor ring initialize (empty) receive descriptor ring table 17-34. microcontroller initialization description initialize backoff random number seed activate receiver activate transmitter clear transmit fifo clear receive fifo initialize transmit ring pointer initialize receive ring pointer initialize fifo count registers table 17-35. mii mode signal description emac pin transmit clock fec_txclk transmit enable fec_txen transmit data fec_txd[3:0] transmit error fec_txer table 17-33. fec user initialization (before ecr[ether_en]) (continued) description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) freescale semiconductor 17-33 the 7-wire serial mode interface (rcr[mii_mode] cleared) is ge nerally referred to as amd mode. table 17-36 shows the 7-wire mode connecti ons to the external transceiver. 17.5.7 fec frame transmission the ethernet transmitter is designed to work with almost no intervention from software. after ecr[ether_en] is set and data appe ars in the transmit fifo, the et hernet mac can transmit onto the network. the ethernet controller transmit s bytes least significant bit (lsb) first. when the transmit fifo fills to the watermark (defined by tfwr), mac transmit logic asserts fec_txen and starts transmitting th e preamble (pa) sequence, the star t frame delimiter (sfd), and then the frame information from the fifo. however, the c ontroller defers the transmission if the network is busy (fec_crs is asserted). before transmitting, the controller waits for carrier sense to become inactive, then determines if carrier sense st ays inactive for 60 bit tim es. if so, transmission begins after waiting an additional 36 bit times ( 96 bit times after carri er sense originally became inactive). see section 17.5.15.1, ?transmission errors,? for more details. collision fec_col carrier sense fec_crs receive clock fec_rxclk receive data valid fec_rxdv receive data fec_rxd[3:0] receive error fec_rxer management data clock fec_mdc management data input/output fec_mdio table 17-36. 7-wire mode configuration signal description emac pin transmit clock fec_ txclk transmit enable fec_ txen transmit data fec_ txd[0] collision fec_ col receive clock fec_ rxclk receive data valid fec_ rxdv receive data fec_ rxd[0] table 17-35. mii mode (continued) signal description emac pin mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) 17-34 freescale semiconductor if a collision occurs duri ng transmission of the frame (half duplex mode), the ethernet controller follows the specified backoff procedures and attempts to retransmit the frame unt il the retry limit is reached. the transmit fifo stores at least the first 64 bytes of the transmit frame, so they do not have to be retrieved from system memory in case of a collision. this im proves bus utilization and latency in case immediate retransmission is necessary. when all the frame data is transmitted, fcs (frame check sequence) or 32-bit cyclic redundancy check (crc) bytes are appended if the tc bit is set in the tr ansmit frame control word. if the abc bit is set in the transmit frame control word, a bad crc is appended to the frame data regardless of the tc bit value. following the transmission of the cr c, the ethernet controller writes the frame status information to the mib block. transmit logic au tomatically pads short frames (if the tc bit in the transmit buffer descriptor for the end of frame buffer is set). settings in the eimr determin e interrupts generated to the buffer (txb) and frame (tfint). the transmit error interrupts are hberr, babt , late_col, col_retry_lim, and xfifo_un. if the transmit frame length exceeds m ax_fl bytes, babt interrupt is asse rted. however, the entire frame is transmitted (no truncation). to pause transmission, set tcr[gts] (graceful transm it stop). the fec transmi tter stops immediately if transmission is not in progress; ot herwise, it continues transmission unt il the current frame finishes or terminates with a collision. after the transmitter has stopped, the gra (graceful stop complete) interrupt is asserted. if tcr[gts] is cleared, the fe c resumes transmission with the next frame. 17.5.7.1 duplicate frame transmission the fec fetches transmit buffer descriptors (txbds ) and the corresponding transmit data continuously until the transmit fifo is full. it does not determine whether the txbd to be fetched is already being processed internally (as a result of a wrap). as the fec nears the end of the transmission of one frame, it begins to dma the data for the next frame. to remain one bd ahead of the dma, it also fetches the txbd for the next frame. it is possible th at the fec fetches from memory a bd that has already been processed but not yet written back (it is read a second time with the r bit remains set) . in this case, the data is fetched and transmitted again. using at least three txbds fixes this problem for large frames, but not fo r small frames. to ensure correct operation for large or small frames, one of the following must be true: ? the fec software driver ensures that there is always at least one txbd with the ready bit cleared. ? every frame uses more than one txbd and every txbd but the la st is written back immediately after the data is fetched. ? the fec software driver ensures a minimum frame size, n . the minimum number of txbds is then (tx fifo size ( n + 4)) rounded up to the nearest integer (though the result cannot be less than three). the default tx fifo size is 192 bytes; this size is programmable. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) freescale semiconductor 17-35 17.5.8 fec frame reception the fec receiver works with almost no interventi on from the host and can pe rform address recognition, crc checking, short frame checking, and maximum frame length checking. th e ethernet controller receives serial data lsb first. when the driver enables the fec receiver by setti ng ecr[ether_en], it immediately starts processing receive frames. when fec_rxdv is as serted, the receiver first checks for a valid pa/sfd header. if the pa/sfd is valid, it is stripped and the receiver processes the frame. if a valid pa/sfd is not found, the frame is ignored. in serial mode, the first 16 bit times of rx_d0 following asserti on of fec_rxdv are ignored. following the first 16 bit times, the data sequence is checked for alternating 1/0s . if a 11 or 00 data sequence is detected during bit times 17 to 21, the remainder of the frame is ignored. after bit time 21, the data sequence is monitored for a va lid sfd (11). if a 00 is de tected, the frame is rejecte d. when a 11 is detected, the pa/sfd sequence is complete. in mii mode, the receiver checks fo r at least one byte matching the sfd. ze ro or more pa bytes may occur, but if a 00 bit sequence is detected prio r to the sfd byte, the frame is ignored. after the first 6 bytes of the frame are receive d, the fec performs address recognition on the frame. after a collision window (64 bytes) of data is received and if addre ss recognition has not rejected the frame, the receive fifo signals the frame is accepted and may be passed on to the dma. if the frame is a runt (due to collision) or is rejected by address rec ognition, the receive fifo is not ified to reject the frame. therefore, no collision fragments ar e presented to you except late collisions, which indicate serious lan problems. during reception, the ethernet controller checks for vari ous error conditions and af ter the entire frame is written into the fifo, a 32-bit frame status word is wr itten into the fifo. this status word contains the m, bc, mc, lg, no, cr, ov, and tr st atus bits, and th e frame length. see section 17.5.15.2, ?reception errors,? for more details. receive buffer (rxb) and frame inte rrupts (rfint) may be generated if enabled by the eimr register. a receive error interrupt is a babbling receiver error (bab r). receive frames are not truncated if they exceed the max frame length (max_fl); however , the babr interrupt occurs and the lg bit in the receive buffer descriptor (rxbd) is set. see section 17.5.1.2, ?ethernet receive buffer descriptor (rxbd),? for more details. when the receive frame is complete, the fec sets the l-bit in the rxbd, writes the other fr ame status bits into the rxbd, and clears the e-bit. the ethernet controller next gene rates a maskable interrupt (rfint bit in eir, maskable by rfien bit in eimr), indica ting that a frame is received and is in memory. the ethernet controller then waits for a new frame. 17.5.9 ethernet address recognition the fec filters the received frames based on destination a ddress (da) type ? indi vidual (unicast), group (multicast), or broadcast (all-one s group address). the difference betw een an individual address and a mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) 17-36 freescale semiconductor group address is determined by the i/g bit in the destination address field. a flowchart for address recognition on received frames a ppears in the figures below. address recognition is accomplished through the use of the receive block a nd microcode running on the microcontroller. the flowchart shown in figure 17-27 illustrates the address recognition decisions made by the receive block, while figure 17-28 illustrates the decisions made by the microcontroller. if the da is a broadcast address and broadcast re ject (rcr[bc_rej]) is cl eared, then the frame is accepted unconditionally, as shown in figure 17-27 . otherwise, if the da is not a broadcast address, then the microcontroller runs the address recognition subroutine, as shown in figure 17-28 . if the da is a group (multica st) address and flow contro l is disabled, then the mi crocontroller performs a group hash table lookup using the 64-entry hash table programmed in gaur and galr. if a hash match occurs, the receiver accepts the frame. if flow control is enabled, the microcontroller does an exact address match ch eck between the da and the designated pause da (01:80:c2:00:00: 01). if the receive block determin es the received frame is a valid pause frame, the frame is rejected. the receiver de tects a pause frame with the da field set to the designated pause da or th e unicast physical address. if the da is the individual (unicas t) address, the microc ontroller performs an individual exact match comparison between the da and 48-bit physical address that you pr ogram in the palr and paur registers. if an exact match occurs , the frame is accepted; otherwise, th e microcontroller does an individual hash table lookup using the 64- entry hash table programmed in register s, iaur and ialr. in the case of an individual hash match, the frame is accepted. again, the r eceiver accepts or rej ects the frame based on pause frame detection, shown in figure 17-27 . if neither a hash match (group or individual) nor an exact match (gr oup or individual) occur, and if promiscuous mode is enabled (rcr[prom] set), the frame is accepted and the miss bit in the receive buffer descriptor is set; othe rwise, the frame is rejected. similarly, if the da is a broadcast address, broadc ast reject (rcr[bc_rej]) is asserted, and promiscuous mode is enabled, the frame is accepted and the miss bit in the receive buffer descri ptor is set; otherwise, the frame is rejected. in general, when a frame is reject ed, it is flushed from the fifo. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) freescale semiconductor 17-37 figure 17-27. ethernet address recognition?receive block decisions accept/reject broadcast addr ? ? prom = 1 ? receive address tr u e false tr u e false bc_rej = 1 ? frame hash match ? exact match ? pause frame false false false false tr u e tr u e tr u e tr u e receive frame receive frame receive frame receive frame reject frame reject frame set bc bit in rcv bd set mc bit in rcv bd if multicast set m (miss) bit in rcv bd set mc bit in rcv bd if multicast set bc bit in rcv bd if broadcast flush from fifo flush from fifo recognition notes: bc_rej - field in rcr register (broadcast reject) prom - field in rcr register (promiscous mode) pause frame - valid pause frame received mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) 17-38 freescale semiconductor figure 17-28. ethernet address recognition?microcode decisions 17.5.10 hash algorithm the hash table algorithm used in th e group and individual hash filteri ng operates as follows. the 48-bit destination address is mapped into one of 64 bits, represented by 64 bits stored in gaur, galr (group address hash match), or iaur, ia lr (individual address hash match). this mapping is performed by passing the 48-bit address through the on-chip 32-bit crc generator and selecting the six most significant bits of the crc-encoded result to generate a number between 0 and 63. th e msb of the crc result selects gaur (msb = 1) or galr (msb = 0). the five least signifi cant bits of the hash resu lt select the bit within the selected register. if the crc ge nerator selects a bit set in the ha sh table, the frame is accepted; otherwise, it is rejected. for example, if eight group addresses are stored in the hash table and random group addres ses are received, the hash table prevents roughly 56/ 64 (87.5%) of the group address frames from reaching memory. those that do reach memory must be further filtered by the processor to determine if they truly c ontain one of the eight desired addresses. the effectiveness of the hash table declin es as the number of addresses increases. receive address i/g address ? exact match ? hash search group table match ? hash search individual table false match ? false false tr u e tr u e tr u e individual group tr u e false tr u e false ? pause address fce ? recognition reject frame flush from fifo reject frame flush from fifo receive frame receive frame receive frame receive frame notes: fce - field in rcr register (flow control enable) i/g - individual/group bit in dest ination address (lsb in first byte received in mac frame) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) freescale semiconductor 17-39 the user must initialize the hash table registers. use this crc32 polynomial to compute the hash: eqn. 17-2 table 17-37 contains example destination addr esses and corresponding hash values. table 17-37. destination address to 6-bit hash 48-bit da 6-bit hash (in hex) hash decimal value 65ff_ffff_ffff 0x0 0 55ff_ffff_ffff 0x1 1 15ff_ffff_ffff 0x2 2 35ff_ffff_ffff 0x3 3 b5ff_ffff_ffff 0x4 4 95ff_ffff_ffff 0x5 5 d5ff_ffff_ffff 0x6 6 f5ff_ffff_ffff 0x7 7 dbff_ffff_ffff 0x8 8 fbff_ffff_ffff 0x9 9 bbff_ffff_ffff 0xa 10 8bff_ffff_ffff 0xb 11 0bff_ffff_ffff 0xc 12 3bff_ffff_ffff 0xd 13 7bff_ffff_ffff 0xe 14 5bff_ffff_ffff 0xf 15 27ff_ffff_ffff 0x10 16 07ff_ffff_ffff 0x11 17 57ff_ffff_ffff 0x12 18 77ff_ffff_ffff 0x13 19 f7ff_ffff_ffff 0x14 20 c7ff_ffff_ffff 0x15 21 97ff_ffff_ffff 0x16 22 a7ff_ffff_ffff 0x17 23 99ff_ffff_ffff 0x18 24 b9ff_ffff_ffff 0x19 25 f9ff_ffff_ffff 0x1a 26 c9ff_ffff_ffff 0x1b 27 x 32 x 26 x 23 x 22 x 16 x 12 x 11 x 10 x 8 x 7 x 5 x 4 x 2 x1 + + + + + + + +++++++ mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) 17-40 freescale semiconductor 59ff_ffff_ffff 0x1c 28 79ff_ffff_ffff 0x1d 29 29ff_ffff_ffff 0x1e 30 19ff_ffff_ffff 0x1f 31 d1ff_ffff_ffff 0x20 32 f1ff_ffff_ffff 0x21 33 b1ff_ffff_ffff 0x22 34 91ff_ffff_ffff 0x23 35 11ff_ffff_ffff 0x24 36 31ff_ffff_ffff 0x25 37 71ff_ffff_ffff 0x26 38 51ff_ffff_ffff 0x27 39 7fff_ffff_ffff 0x28 40 4fff_ffff_ffff 0x29 41 1fff_ffff_ffff 0x2a 42 3fff_ffff_ffff 0x2b 43 bfff_ffff_ffff 0x2c 44 9fff_ffff_ffff 0x2d 45 dfff_ffff_ffff 0x2e 46 efff_ffff_ffff 0x2f 47 93ff_ffff_ffff 0x30 48 b3ff_ffff_ffff 0x31 49 f3ff_ffff_ffff 0x32 50 d3ff_ffff_ffff 0x33 51 53ff_ffff_ffff 0x34 52 73ff_ffff_ffff 0x35 53 23ff_ffff_ffff 0x36 54 13ff_ffff_ffff 0x37 55 3dff_ffff_ffff 0x38 56 0dff_ffff_ffff 0x39 57 5dff_ffff_ffff 0x3a 58 7dff_ffff_ffff 0x3b 59 table 17-37. destination address to 6-bit hash (continued) 48-bit da 6-bit hash (in hex) hash decimal value mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) freescale semiconductor 17-41 17.5.11 full duplex flow control full-duplex flow control allows you to transmit pause frames and to detect received pause frames. upon detection of a pause frame, mac data frame transmission st ops for a given pause duration. to enable pause frame detection, the fec must operate in full-duplex mode (tcr [fden] set) with flow control (rcr[fce] set). the fec dete cts a pause frame when the fields of the incoming frame match the pause frame specificat ions, as shown in table 17-38 . in addition, the receive status associated with the frame should indicate that the frame is valid. the receiver and microcontroller m odules perform pause fr ame detection. the micr ocontroller runs an address recognition subroutine to det ect the specified pause frame destin ation address, while the receiver detects the type and opcode pause frame fields. on de tection of a pause frame, tcr[gts] is set by the fec internally. when transmission has paused, the ei r[gra] interrupt is asse rted and the pause timer begins to increment. the pause timer uses the transmit backoff timer ha rdware for tracking the appropriate collision backoff time in half-duplex mode. the pa use timer increments once every slot time, until opd[pause_dur] slot times have expired. on opd[ pause_dur] expiration, tcr[gts] is cleared allowing mac data frame transmission to resume . the receive flow control pause status bit (tcr[rfc_pause]) is set while the transmitte r pauses due to recept ion of a pause frame. to transmit a pause frame, the fec must operate in full-duplex mode a nd you must set flow control pause (tcr[tfc_pause]). after tcr[tfc_pause] is set, the transmitter sets tcr[gts] internally. when the transmission of data frames stops, the eir[gra] (graceful stop complete) interrupt asserts and the pause frame is transmitted. tcr[tfc_paus e,gts] are then cleared internally. you must specify the desired paus e duration in the opd register. fdff_ffff_ffff 0x3c 60 ddff_ffff_ffff 0x3d 61 9dff_ffff_ffff 0x3e 62 bdff_ffff_ffff 0x3f 63 table 17-38. pause frame field specification 48-bit destination address 0x0180_c200_0001 or physical address 48-bit source address any 16-bit type 0x8808 16-bit opcode 0x0001 16-bit pause duration 0x0000 ? 0xffff table 17-37. destination address to 6-bit hash (continued) 48-bit da 6-bit hash (in hex) hash decimal value mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) 17-42 freescale semiconductor when the transmitter pauses due to receiver/micro controller pause frame de tection, tcr[tfc_pause] may remain set and cause the transm ission of a single pause frame. in this case, the eir[gra] interrupt is not asserted. 17.5.12 inter-packet gap (ipg) time the minimum inter-packet gap time for back-to-back transmission is 96 bit times. after completing a transmission or after the ba ckoff algorithm completes, the transmitte r waits for carrier sense to be negated before starting its 96 bit time ipg counter. frame transmission may begi n 96 bit times after carrier sense is negated if it stays negated for at least 60 bit times. if carrier sense asserts during the last 36 bit times, it is ignored and a collision occurs. the receiver accepts back-to-back frames with a minimum spacing of at least 28 bit times. if an inter-packet gap between receive frames is less th an 28 bit times, the receiver may discard the following frame. 17.5.13 collision managing if a collision occurs during frame tr ansmission, the ethernet controller continues the transmission for at least 32 bit times, transmitting a jam pattern consisting of 32 ones. if the collision occurs during the preamble sequence, a jam pattern is sent after the end of the preamble sequence. if a collision occurs within 512 bit t imes (one slot time), the retry proces s is initiated. the transmitter waits a random number of slot times. if a collision occurs after 512 bit times, then no retransmission is performed and the end of frame buffer is closed with a late collision (lc) error indication. 17.5.14 mii internal and external loopback internal and external loopback are supported by the et hernet controller. in l oopback mode, both of the fifos are used and the fec actually operates in a full-duplex fashi on. internal and external loopback are configured using combinations of the rcr[loop, drt] and tcr[fden] bits. set fden for internal and external loopback. for internal loopback, set rcr[loop] and clear rcr[drt]. fec_txen and fec_txer do not assert during internal loopback. during intern al loopback, the transmit/receive data rate is higher than in normal operation because the transmit and rece ive blocks use the internal bus clock instead of the clocks from the external transceiver. this causes an increase in th e required system bus bandwid th for transmit and receive data being dma?d to/from external memory. it may be necessary to pace the frames on the transmit side and/or limit the size of the fram es to prevent transmit fifo unde rruns and receive fifo overflows. for external loopback, clear rcr[loop] and rcr[dr t], and configure the external transceiver for loopback. 17.5.15 ethernet error-managing procedure the ethernet controller reports frame reception and transmission er ror conditions using the mib block counters, the fec rxbds, and the eir register. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) freescale semiconductor 17-43 17.5.15.1 transmission errors 17.5.15.1.1 transmitter underrun if this error occurs, the fec sends 32 bits that en sure a crc error and stops transmitting. all remaining buffers for that frame are then flus hed and closed, and eir[un] is set. the fec then continues to the next transmit buffer descriptor and begin transmitting the next frame. the un interrupt is asserted if enabled in the eimr register. 17.5.15.1.2 retransmission attempts limit expired when this error occurs, the fec te rminates transmission. all remaining buffers for that frame are flushed and closed, and eir[rl] is set. the fec then continues to the next tran smit buffer descri ptor and begins transmitting the next frame. the rl interrupt is asserted if enabled in the eimr register. 17.5.15.1.3 late collision when a collision occurs after the slot time (512 bi ts starting at the preamble), the fec terminates transmission. all remaining buffers for that frame ar e flushed and closed, and eir[lc] is set. the fec then continues to the next transm it buffer descriptor and begin tran smitting the next frame. the lc interrupt is asserted if en abled in the eimr register. 17.5.15.1.4 heartbeat some transceivers have a self-test feature called heartbeat or signal quality error. to signify a good self-test, the transceiver indicates a collision to the fec within four microseconds after completion of a frame transmitted by the ethernet controller. this indi cation of a collision does not imply a real collision error on the network, but is rather an indication that the transceiver cont inues to function properly. this is the heartbeat condition. if tcr[hbc] is set and the heartb eat condition is not detected by th e fec after a frame transmission, a heartbeat error occurs. when this error occurs, the fe c closes the buffer, sets eir[hb], and generates the hberr interrupt if it is enabled. 17.5.15.2 reception errors 17.5.15.2.1 overrun error if the receive block has data to put into the receive fifo and the receiv e fifo is full, fec sets rxbd[ov]. all subsequent data in the frame is discarded and subsequent frames may also be discarded until the receive fifo is serviced by the dma and space is made available. at this point the receive frame/status word is written into the fifo with the ov bit set. the driver mu st discard this frame. 17.5.15.2.2 non-octet er ror (dribbling bits) the ethernet controller manages up to seven dribbli ng bits when the receive frame terminates past an non-octet aligned boundary. dribbling bits are not used in the crc calculat ion. if there is a crc error, the frame non-octet aligned (no) error is reported in the rxbd. if ther e is no crc error, no error is reported. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 fast ethernet controller (fec) 17-44 freescale semiconductor 17.5.15.2.3 crc error when a crc error occurs with no dribble bits, fec closes the buffer and sets rxbd[cr]. crc checking cannot be disabled, but the crc error can be ignored if checking is not required. 17.5.15.2.4 frame length violation when the receive frame length exceeds max_fl bytes the babr interrupt is generated, and rxbd[lg] is set. the frame is not truncated unless the frame length exceeds 2047 bytes. 17.5.15.2.5 truncation when the receive frame length exceeds 2047 bytes, frame is truncated and rxbd[tr] is set. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor 18-1 chapter 18 watchdog timer module 18.1 introduction the watchdog timer is a 16-bit timer used to help software recover from runaway code. the watchdog timer has a free-running down-counter (watchdog counter) that generates a reset on underflow. to prevent a reset, software must periodically restart the countdown by servicing the watchdog. 18.2 low-power mode operation this subsection describes the opera tion of the watchdog module in low- power modes and halted mode of operation. low-power mode s are described in chapter 7, ?power management .? table 3-1 shows the watchdog module operation in the low-power modes, and shows how this module ma y facilitate exit from each mode. in wait mode with the watchdog control register?s wait bit (wcr[wait]) set, watchdog timer operation stops. in wait mode with the wcr[wait] bit clea red, the watchdog timer conti nues to operate normally. in doze mode with the wcr[doze] bit set, the watchdog timer modu le operation stops. in doze mode with the wcr[doze] bit cleared, the watchdog timer continues to operate normally. watchdog timer operation stops in stop mode. when stop mode is exited, the watchdog ti mer continues to operate in its pre-stop mode state. in halted mode with the wcr[hal ted] bit set, watchdog timer modul e operation stops. in halted mode with the wcr[halted] bit cleare d, the watchdog timer continues to operate normally. when halted mode is exited, watchdog timer operati on continues from the st ate it was in before entering halted mode, but any updates made in halted mode remain. table 18-1. watchdog module operation in low-power modes low-power mode watchdog operation mode exit wait normal if wcr[wait] cleared, stopped otherwise upon watchdog reset doze normal if wcr[doze] cleared, stopped otherwise upon watchdog reset stop stopped no halted normal if wcr[halted] cleared, stopped otherwise upon watchdog reset mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 watchdog timer module 18-2 freescale semiconductor 18.3 block diagram figure 18-1. watchdog timer block diagram 18.4 signals the watchdog timer module has no off-chip signals. 18.5 memory map and registers this subsection describes the memo ry map and registers for the watc hdog timer. the wa tchdog timer has a ipsbar offset for base address of 0x0014_0000. 18.5.1 memory map refer to table 18-2 for an overview of the watchdog memory map. 16-bit wmr 16-bit watchdog counter count = 0 system divide by reset clock ipbus 8192 16-bit wcntr 16-bit wsr ipbus load counter en wait doze halted mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 watchdog timer module freescale semiconductor 18-3 18.5.2 registers the watchdog timer programming model consists of th ese registers: ? watchdog control register (wcr), wh ich configures watchdog timer operation ? watchdog modulus register (wmr), which determines the timer modulus reload value ? watchdog count register (wcntr), which provi des visibility to th e watchdog counter value ? watchdog service register (wsr), which requires a service sequence to prevent reset 18.5.2.1 watchdog control register (wcr) the 16-bit wcr configures watchdog timer operation. table 18-2. watchdog timer module memory map ipsbar offset bits 15?8 bits 7?0 access 1 1 s = cpu supervisor mode access only. s/u = cpu supervisor or user mode access. user mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error. 0x0014_0000 watchdog control register (wcr) s 0x0014_0002 watchdog modulus register (wmr) s 0x0014_0004 watchdog count register (wcntr) s/u 0x0014_0006 watchdog service register (wsr) s/u 15 14 13 12 11 10 9 8 field ? reset 0000_0000 r/w r 765 4 3210 field ? wait doze halted en reset 0000_1111 r/w r r/w address ipsbar + 0x0014_0000, 0x0014_0001 figure 18-2. watchdog control register (wcr) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 watchdog timer module 18-4 freescale semiconductor 18.5.2.2 watchdog modulus register (wmr) table 18-3. wcr field descriptions bit(s) name description 15?4 ? reserved, should be cleared. 3 wait wait mode bit. controls the function of the watchdog timer in wait mode. once written, the wait bit is not affected by further writes except in halted mode. reset sets wait. 1 watchdog timer stopped in wait mode 0 watchdog timer not affected in wait mode 2 doze doze mode bit. controls the function of the watchdog timer in doze mode. once written, the doze bit is not affected by further writes except in halted mode. reset sets doze. 1 watchdog timer stopped in doze mode 0 watchdog timer not affected in doze mode 1 halted halted mode bit. controls the function of the watchdog timer in halted mode. once written, the halted bit is not affected by further writes except in halted mode. during halted mode, watchdog timer registers can be written and read normally. when halted mode is exited, timer operation continues from the state it was in before entering halted mode, but any updates made in halted mode remain. if a write-once register is written for the first time in halte d mode, the register is still writable when halted mode is exited. 1 watchdog timer stopped in halted mode 0 watchdog timer not affected in halted mode note: changing the halted bit from 1 to 0 during halted mode starts the watchdog timer. changing the halted bit from 0 to 1 during halted mode stops the watchdog timer. 0 en watchdog enable bit. enables the watchdog timer. once written, the en bit is not affected by further writes except in halt ed mode. when the watchdog timer is disabled, the watchdog counter and prescaler counter are held in a stopped state. 1 watchdog timer enabled 0 watchdog timer disabled 15 14 13 12 11 10 9 8 field wm15 wm14 wm13 wm12 wm11 wm10 wm9 wm8 reset 1111_1111 r/w r/w 765 4 3210 field wm7 wm6 wm5 wm4 wm3 wm2 wm1 wm0 reset 1111_1111 r/w r/w address ipsbar + 0x0014_0002, 0x0014_0003 figure 18-3. watchdog modulus register (wmr) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 watchdog timer module freescale semiconductor 18-5 18.5.2.3 watchdog count register (wcntr) 18.5.2.4 watchdog serv ice register (wsr) when the watchdog time r is enabled, writing 0x5555 and then 0xaaaa to wsr before the watchdog counter times out prevents a reset. if wsr is not servi ced before the timeout, the watchdog timer sends a signal to the reset controller module that sets the rsr[wdr] bit and asserts a system reset. both writes must occur in the or der listed before the timeout, but any number of instructions can be executed between the two writes. however, writing any value othe r than 0x5555 or 0xaaaa to wsr resets the servicing sequence, requi ring both values to be written to keep the watchdog timer from causing a reset. table 18-4. wmr field descriptions bit(s) name description 15?0 wm watchdog modulus. contains the modulus that is reloaded into the watchdog counter by a service sequence. once written, the wm[15:0] field is not affected by further writes except in halted mode. writing to wmr immediately loads the new modulus value into the watchdog counter. the new va lue is also used at the next and all subsequent reloads. reading wmr returns the value in the modulus register. reset initializes the wm[ 15:0] field to 0xffff. note: the prescaler counter is reset anytime a new value is loaded into the watchdog counter and also during reset. 15 14 13 12 11 10 9 8 field wc15 wc14 wc13 wc12 wc11 wc10 wc9 wc8 reset 1111_1111 r/w r 765 4 3210 field wc7 wc6 wc5 wc4 wc3 wc2 wc1 wc0 reset 1111_1111 r/w r address ipsbar + x0014_0004, 0x0014_0005 figure 18-4. watchdog count register (wcntr) table 18-5. wcntr field descriptions bit(s) name description 15?0 wc watchdog count field. reflects the current value in the watchdog counter. reading the 16-bit wcntr with two 8-bit reads is not guaranteed to return a coherent value. writing to wcntr has no effect, and write cycles are terminated normally. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 watchdog timer module 18-6 freescale semiconductor 15 14 13 12 11 10 9 8 field ws15 ws14 ws13 ws12 ws11 ws10 ws9 ws8 reset 0000_0000 r/w r/w 765 4 3210 field ws7 ws6 ws5 ws4 ws3 ws2 ws1 ws0 reset 0000_0000 r/w r/w address ipsbar + 0x0014_0006, 0x0014_0007 figure 18-5. watchdog service register (wsr) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor 19-1 chapter 19 programmable interrupt timers (pit0?pit3) 19.1 introduction this chapter describes the opera tion of the four programmable in terrupt timer modules: pit0?pit3. 19.1.1 overview each pit is a 16-bit timer that pr ovides precise interrupts at regular intervals with minimal processor intervention. the timer can count down from the value written in the modulus register or it can be a free-running down-counter. 19.1.2 block diagram figure 19-1. pit block diagram 19.1.3 low-power mode operation this subsection describes the operation of the pi t modules in low-power modes and debug mode of operation. low-power modes are describe d in the power management module, chapter 7, ?power management.? table 19-1 shows the pit module operation in low-pow er modes and how it can exit from each mode. internal bus clock (f sys ) 16-bit pmr n 16-bit pit counter count = 0 internal bus 16-bit pcntr n internal bus en ovw doze dbg prescaler pre[3:0] rld pif pie load counter to interrupt controller mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 programmable interrupt timers (pit0?pit3) 19-2 freescale semiconductor note the low-power interrupt control regist er (lpicr) in the system control module specifies the interrupt level at or above which the device can be brought out of a low-power mode. in wait mode, the pit module continues to operate as in run mode and can be configured to exit the low-power mode by generati ng an interrupt request. in doze mode with the pcsr n [doze] bit set, pit module operation stops. in doze mode with the pcsr n [doze] bit cleared, doze mode does not affect pit operation. when doze mode is exited, pit continues operating in the state it was in prior to doze mode. in stop mode, the internal bus clock is absent and pit module operation stops. in debug mode with the pcsr n[dbg] bit set, pit module operation stops. in debug mode with the pcsr n[dbg] bit cleared, debug mode does not affect pit operation. when debug mode is exited, the pit continues to operate in its pr e-debug mode state, but any update s made in debug mode remain. 19.2 memory map/register definition this section contains a memory map (see table 19-2 ) and describes the register structure for pit0?pit3. table 19-1. pit module operation in low-power modes low-power mode pit operation mode exit wait normal n/a doze normal if pcsr n [doze] cleared, stopped otherwise any interrupt at or above level in lpicr, exit doze mode if pcsr n [doze] is set. otherwise interrupt assertion has no effect. stop stopped no debug normal if pcsr n [dbg] cleared, stopped otherwise no. any interrupt is serviced upon normal exit from debug mode table 19-2. programmable interrupt timer modules memory map ipsbar offset register width (bits) access 1 reset value section/page pit 0 pit 1 pit 2 pit 3 supervisor access only registers 2 0x15_0000 0x16_0000 0x17_0000 0x18_0000 pit control and status register (pcsr n ) 16 r/w 0x0000 19.2.1/19-3 0x15_0002 0x16_0002 0x17_0002 0x18_0002 pit modulus register (pmr n ) 16 r/w 0xffff 19.2.2/19-5 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 programmable interrupt timers (pit0?pit3) freescale semiconductor 19-3 19.2.1 pit control and st atus register (pcsr n ) the pcsr n registers configure the corresponding timer?s operation. user/supervisor access registers 0x15_0004 0x16_0004 0x17_0004 0x18_0004 pit count register (pcntr n ) 16 r 0xffff 19.2.3/19-5 1 accesses to reserved address locati ons have no effect and result in a cycle termination transfer error. 2 user mode accesses to supervisor only addresses have no ef fect and result in a cycle termination transfer error. ipsbar offset: 0x15_0000 (pcsr0) 0x16_0000 (pcsr 1 ) 0x17_0000 (pcsr 2 ) 0x18_0000 (pcsr 3 ) access: supervisor read/write 1514131211109876543210 r0000 pre 0 doze dbg ovw pie pif rld en w w1c reset000000000 0000000 figure 19-2. pcsr n register table 19-2. programmable interrupt timer modules memory map (continued) ipsbar offset register width (bits) access 1 reset value section/page pit 0 pit 1 pit 2 pit 3 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 programmable interrupt timers (pit0?pit3) 19-4 freescale semiconductor table 19-3. pcsr n field descriptions field description 15?12 reserved, must be cleared. 11?8 pre prescaler. the read/write prescaler bits select the internal bus cl ock divisor to generate the pit clock. to accurately predict the timing of the next count, ch ange the pre[3:0] bits only when the enable bit (en) is clear. changing pre[3:0] resets the prescaler counter. system reset and th e loading of a new value into the counter also reset the prescaler counter. setting the en bit and writing to pre[3: 0] can be done in this same write cycle. clearing the en bit stops the prescaler counter. 7 reserved, must be cleared. 6 doze doze mode bit. the read/write doze bit controls the f unction of the pit in doze mode. reset clears doze. 0 pit function not affected in doze mode 1 pit function stopped in doze mode. when doze mode is ex ited, timer operation continues from the state it was in before entering doze mode. 5 dbg debug mode bit. controls the function of pit in halted/ debug mode. reset clears dbg. during debug mode, register read and write accesses function normally. when debug mode is exited, timer operation co ntinues from the state it was in before entering debug mode, but any updates made in debug mode remain. 0 pit function not affected in debug mode 1 pit function stopped in debug mode note: changing the dbg bit from 1 to 0 during debug mode starts the pit timer. likewise, changing the dbg bit from 0 to 1 during debug mode stops the pit timer. 4 ovw overwrite. enables writing to pmr n to immediately overwrite the value in the pit counter. 0 value in pmr n replaces value in pit counter when count reaches 0x0000. 1 writing pmr n immediately replaces value in pit counter. 3 pie pit interrupt enable. this read/write bit enab les pif flag to generate interrupt requests. 0 pif interrupt requests disabled 1 pif interrupt requests enabled 2 pif pit interrupt flag. this read/w rite bit is set when pit counter reaches 0x0000. clear pif by writing a 1 to it or by writing to pmr. writing 0 has no effect. reset clears pif. 0 pit count has not reached 0x0000. 1 pit count has reached 0x0000. pre internal bus clock divisor decimal equivalent 0000 2 0 1 0001 2 1 2 0010 2 2 4 ... ... ... 1101 2 13 8192 1110 2 14 16384 1111 2 15 32768 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 programmable interrupt timers (pit0?pit3) freescale semiconductor 19-5 19.2.2 pit modulus register (pmr n ) the 16-bit read/write pmr n contains the timer modulus value loaded into the pit counter when the count reaches 0x0000 and the pcsr n [rld] bit is set. when the pcsr n[ovw] bit is set, pmr n is transparent, and the value written to pmr n is immediately loaded into the pit counter. the prescaler counter is reset (0xffff) anytime a new value is loaded into the pit counter and also during reset. reading the pmr n returns the value written in the modulus latch. reset initializes pmr n to 0xffff. 19.2.3 pit count register (pcntr n ) the 16-bit, read-only pcntr n contains the counter value. reading the 16-bit counter wi th two 8-bit reads is not guaranteed coherent. writing to pcntr n has no effect, and write cycl es are terminated normally. 1 rld reload bit. the read/write reload bit enables loading the value of pmr n into pit counter when the count reaches 0x0000. 0 counter rolls over to 0xffff on count of 0x0000 1 counter reloaded from pmr n on count of 0x0000 0 en pit enable bit. enables pit operation. when pit is disabled, counter and prescaler are held in a stopped state. this bit is read anytime, write anytime. 0 pit disabled 1 pit enabled ipsbar offset: 0x15_0002 (pmr0) 0x16_0002 (pmr 1 ) 0x17_0002 (pmr 2 ) 0x18_0002 (pmr 3 ) access: supervisor read/write 1514131211109876543210 r pm w reset111111111 1111111 figure 19-3. pit modulus register (pmr n) table 19-4. pmr n field descriptions field description 15?0 pm timer modulus. the value of this register is loaded in to the pit counter when the count reaches zero and the pcsr n [rld] bit is set. however, if pcsr n [ovw] is set, the value written to this field is immediately loaded into the counter. reading this field returns the value written. table 19-3. pcsr n field descriptions (continued) field description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 programmable interrupt timers (pit0?pit3) 19-6 freescale semiconductor 19.3 functional description this section describes th e pit functional operation. 19.3.1 set-and-forget timer operation this mode of operation is selected when the rld bit in the pcsr register is set. when pit counter reaches a count of 0x0000, pif flag is set in pcsr n. the value in the modulus register loads into the counter, and the counter be gins decrementing to ward 0x0000. if the pcsrn [pie] bit is set, the pif flag issues an interrupt request to the cpu. when the pcsr n [ovw] bit is set, the counter can be directly initialized by writing to pmr n without having to wait for the count to reach 0x0000. figure 19-5. counter reloading from the modulus latch 19.3.2 free-running timer operation this mode of operation is selected when the pcsr n [rld] bit is clear. in this mode, the counter rolls over from 0x0000 to 0xffff without reloading from th e modulus latch and c ontinues to decrement. when the counter reaches a count of 0x0000, pcsr n [pif] flag is set. if the pcsr n[pie] bit is set, pif flag issues an interrupt request to the cpu. ipsbar offset: 0x15_0004 (pcntr0) 0x16_0004 (pcntr 1 ) 0x17_0004 (pcntr 2 ) 0x18_0004 (pcntr 3 ) access: user read only 1514131211109876543210 rp c w reset111111111 1111111 figure 19-4. pit count register (pcntr n ) table 19-5. pcntr n field descriptions field description 15?0 pc counter value. reading this field with two 8-bit reads is not guaranteed coherent. writing to pcntr n has no effect, and write cycles are te rminated normally. 0x0002 0x0001 0x0000 0x0005 0x0005 pit clock counter modulus pif mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 programmable interrupt timers (pit0?pit3) freescale semiconductor 19-7 when the pcsr n[ovw] bit is set, counter can be directly init ialized by writing to pmr n without having to wait for the co unt to reach 0x0000. figure 19-6. counter in free-running mode 19.3.3 timeout specifications the 16-bit pit counter and pr escaler supports different timeout periods . the prescaler divides the internal bus clock period as selected by the pcsr n [pre] bits. the pmrn [pm] bits select the timeout period. eqn. 19-1 19.3.4 interrupt operation table 19-6 shows the interrupt request generated by the pit. the pif flag is set when the pit counter reaches 0x0000. the pie bit enables the pif flag to generate interrupt requests. clear pif by writing a 1 to it or by writing to the pmr. table 19-6. pit interrupt requests interrupt request flag enable bit timeout pif pie 0x0002 0x0001 0x0000 0xffff 0x0005 pit clock counter modulus pif timeout period 2 pcsrn[pre] (pmrn[pm] 1) + f sys ----------------------------------------------------------------------- - = mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 programmable interrupt timers (pit0?pit3) 19-8 freescale semiconductor mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor 20-1 chapter 20 general purpose timer modules (gpta and gptb) the processor has two 4-channel ge neral purpose timer modules (gpta a nd gptb). each consists of a 16-bit counter driven by a 7-stage programmable prescaler. a timer overflow function allows so ftware to extend the timing capability of the system beyond the 16-bit range of the counter. each of the four timer channels can be configured for input capture, which can capture the time of a selected tran sition edge, or for output compare, which can generate output waveforms and timer software delays. these functions allow simultaneous input waveform measurements and output waveform generation. additionally, one of the channels, ch annel 3, can be configur ed as a 16-bit pulse accumulator that can operate as a simple event counter or as a gated time accumulator. th e pulse accumulator uses the gpt channel 3 input/output pin in either event mode or gated time accumulation mode. 20.1 features features of the genera l-purpose timer include: ? four 16-bit input captur e/output compare channels ? 16-bit architecture ? programmable prescaler ? pulse widths variable fr om microseconds to seconds ? single 16-bit pulse accumulator ? toggle-on-overflow feature for pulse-width modulator (pwm) generation ? external timer cloc k input (synca/syncb) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose timer modules (gpta and gptb) 20-2 freescale semiconductor 20.2 block diagram figure 20-1. gpt block diagram prescaler channel 0 pt0 16-bit counter system logic pr[2:0] divide-by-64 gptc0h:gptc0l edge detect gptpacnth:gptpacntl paov f pedge paov i pa m o d pa e 16-bit comparator gptcnth:gptcntl 16-bit latch channel 1 gptc1h:gptc1l 16-bit comparator 16-bit latch 16-bit counter interrupt logic tof toi c0f c1f edge detect pt1 logic edge detect cxf channel 2 channel3 gptc3h:gptc3l 16-bit comparator 16-bit latch c3f pt3 logic edge detect ios0 ios1 ios3 om:ol0 tov0 om:ol1 tov1 om:ol3 tov3 edg1a edg1b edg3a edg3b edg0a edg0b tcre channel 3 output compare pa i f clear counter pa i f pa i interrupt logic cxi interrupt request interrupt request paov f ch. 3 compare ch.3 capture ch. 1 capture mux clk[1:0] pac l k paclk/256 paclk/65536 pac l k paclk/256 paclk/65536 te clock ch. 1 compare ch. 0 compare ch. 0 capture pa input mux gptx0 pin gptx1 pin gptx3 pin x syncx pin divide by 2 divide by 2 system clock mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose timer modules (gpta and gptb) freescale semiconductor 20-3 20.3 low-power mode operation this subsection describes the ope ration of the general purpose time module in low-power modes and halted mode of operation. low-power modes are described in the power management module. table 3-1 shows the general purpose timer modul e operation in the low-power m odes, and shows how this module may facilitate exit from each mode. general purpose timer operation stops in stop mode. wh en stop mode is exited, the general purpose timer continues to operate in its pre-stop mode state. 20.4 signal description table 20-2 provides an overview of the signal properties. note throughout this section, an ? n ? in the pin name, as in ?gpt n0,? designates gpta or gptb. 20.4.1 gpt n [2:0] the gpt n[2:0] pins are for channel 2?0 input capture and output compare functions. these pins are available for general-purpose input/output (i/o) when not conf igured for timer functions. 20.4.2 gpt n 3 the gpt n3 pin is for channel 3 input cap ture and output compare functions or for the pulse accumulator input. this pin is available fo r general-purpose i/o when not c onfigured for timer functions. table 20-1. watchdog module operation in low-power modes low-power mode watchdog operation mode exit wait normal no doze normal no stop stopped no halted normal no table 20-2. signal properties pin name gptport register bit function reset state pull-up gpt n 0portt n 0gpt n channel 0 ic/oc pin input active gpt n 1portt n 1gpt n channel 1 ic/oc pin input active gpt n 2portt n 2gpt n channel 2 ic/oc pin input active gpt n 3portt n 3gpt n channel 3 ic/oc or pa pin input active sync n porte[3:0] 1 1 synca is available on either porte3 or porte1 ; syncb is available on either porte2 or porte0. gpt n counter synchronization input active mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose timer modules (gpta and gptb) 20-4 freescale semiconductor 20.4.3 sync n the sync n pin is for synchronization of the timer counter. it can be used to synchronize the counter with externally-timed or clocked events. a hi gh signal on this pin clears the counter. 20.5 memory map and registers see table 20-3 for a memory map of the two gpt modules. gpta has a base address of ipsbar + 0x1a_0000. gptb has a base addr ess of ipsbar + 0x1b_0000. note reading reserved or unimplemented locations returns zeroes. writing to reserved or unimplemented locations has no effect. table 20-3. gpt modules memory map ipsbar offset bits 7?0 access 1 gpta gptb 0x1a_0000 0x1b_0000 gpt ic/oc se lect register (gptios) s 0x1a_0001 0x1b_0001 gpt compare force register (gptcforc) s 0x1a_0002 0x1b_0002 gpt output compare 3 mask register (gptoc3m) s 0x1a_0003 0x1b_0003 gpt output compare 3 data register (gptoc3d) s 0x1a_0004 0x1b_0004 gpt counter register (gptcnt) s 0x1a_0006 0x1b_0006 gpt system control register 1 (gptscr1) s 0x1a_0007 0x1b_0007 reserved 2 ? 0x1a_0008 0x1b_0008 gpt toggle-on-overflow register (gpttov) s 0x1a_0009 0x1b_0009 gpt control register 1 (gptctl1) s 0x1a_000a 0x1b_000a reserved (2) ? 0x1a_000b 0x1b_000b gpt control register 2 (gptctl2) s 0x1a_000c 0x1b_000c gpt interrupt enable register (gptie) s 0x1a_000d 0x1b_000d gpt system control register 2 (gptscr2) s 0x1a_000e 0x1b_000e gpt flag register 1 (gptflg1) s 0x1a_000f 0x1b_000f gpt flag register 2 (gptflg2) s 0x1a_0010 0x1b_0010 gpt channel 0 register high (gptc0h) s 0x1a_0011 0x1bb_0011 gpt channel 0 register low (gptc0l) s 0x1a_0012 0x1b_0012 gpt channel 1 register high (gptc1h) s 0x1a_0013 0x1b_0013 gpt channel 1 register low (gptc1l) s 0x1a_0014 0x1b_0014 gpt channel 2 register high (gptc2h) s 0x1a_0015 0x1b_0015 gpt channel 2 register low (gptc2l) s 0x1a_0016 0x1b_0016 gpt channel 3 register high (gptc3h) s mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose timer modules (gpta and gptb) freescale semiconductor 20-5 20.5.1 gpt input capture/output co mpare select register (gptios) 0x1a_0017 0x1b_0017 gpt channel 3 register low (gptc3l) s 0x1a_0018 0x1b_0018 pulse accumulator control register (gptpactl) s 0x1a_0019 0x1b_0019 pulse accumulator flag register (gptpaflg) s 0x1a_001a 0x1b_001a pulse accumulator counter register high (gptpacnth) s 0x1a_001b 0x1b_001b pulse accumulator counter register low (gptpacntl) s 0x1a_001c 0x1b_001c reserved (2) ? 0x1a_001d 0x1b_001d gpt port data register (gptport) s 0x1a_001e 0x1b_001e gpt port data direction register (gptddr) s 0x1a_001f 0x1b_001f gpt test register (gpttst) s 1 s = cpu supervisor mode access only. 2 writes have no effect, reads return 0s, and the access terminates without a transfer error exception. 74 3 0 field ? ios reset 0000_0000 r/w r/w address ipsbar + 0x401a_0000, 0x401b_0000 figure 20-2. gpt input capture/output compare select register (gptios) table 20-4. gptios field descriptions bit(s) name description 7?4 ? reserved, should be cleared. 3?0 ios i/o select. the ios[3:0] bits enable input capture or output compare operation for the corresponding timer channels. these bits are read anytime (always read 0x00), write anytime. 1 output compare enabled 0 input capture enabled table 20-3. gpt modules memory map (continued) ipsbar offset bits 7?0 access 1 gpta gptb mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose timer modules (gpta and gptb) 20-6 freescale semiconductor 20.5.2 gpt compare force register (gpcforc) note a successful channel 3 output compar e overrides any co mpare on channels 2:0. for each oc3m bit that is set, the output compare action reflects the corresponding oc3d bit. 20.5.3 gpt output compare 3 mask register (gptoc3m) 74 3 0 field ? foc reset 0000_0000 r/w r/w address ipsbar + 0x1a _00001, 0x1b_0001 figure 20-3. gpt input compare force register (gpcforc) table 20-5. gptcforc field descriptions bit(s) name description 7?4 ? reserved, should be cleared. 3?0 foc force output compare.setting an foc bit causes an immediate output compare on the corresponding channel. forcing an ou tput compare does not set the output compare flag. these bits are read anytime, write anytime. 1 force output compare 0 no effect 74 3 0 field ? oc3m reset 0000_0000 r/w r/w address ipsbar + 0x1a_0002, 0x1b_0002 figure 20-4. gpt output compare 3 mask register (gptoc3m) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose timer modules (gpta and gptb) freescale semiconductor 20-7 20.5.4 gpt output compare 3 data register (gptoc3d) note a successful channel 3 output compar e overrides any channel 2:0 compares. for each oc3m bit that is set, th e output compare action reflects the corresponding oc3d bit. 20.5.5 gpt counter register (gptcnt) table 20-6. gptoc3m field descriptions bit(s) name description 7?4 ? reserved, should be cleared. 3?0 oc3m output compare 3 mask. setting an oc 3m bit configures the corresponding portt n pin to be an output. oc3m n makes the gpt port pin an output regardless of the data direction bit when the pin is configured for output compare (iosx = 1). the oc3m n bits do not change the state of the portt n ddr bits. these bits are read anytime, write anytime. 1 corresponding portt n pin configured as output 0 no effect 74 3 0 field ? oc3d reset 0000_0000 r/w r/w address ipsbar + 0x1a_0003, 0x1b_0003 figure 20-5. gpt output compare 3 data register (gptoc3d) table 20-7. gptoc3d field descriptions bit(s) name description 7?4 ? reserved, should be cleared. 3?0 oc3d output compare 3 data. when a successful channel 3 output compare occurs, these bits transfer to the portt n data register if the corresponding oc3m n bits are set. these bits are read an ytime, write anytime. 15 0 field cntr reset 0000_0000_0000_0000 r/w read only address ipsbar + 0x1a_0004, 0x1b_0004 figure 20-6. gpt counter register (gptcnt) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose timer modules (gpta and gptb) 20-8 freescale semiconductor 20.5.6 gpt system control register 1 (gptscr1) table 20-8. gptcnt field descriptions bit(s) name description 15?0 cntr read-only field that provides the cu rrent count of the timer counter. to ensure coherent reading of the timer counter, su ch that a timer rollover does not occur between two back-to-back 8-bit reads, it is recommended that only word (16-bit) accesses be used. a write to gptcnt may have an extra cycle on the first count because the write is not synchronized with the prescale r clock. the write occurs at least one cycle before the synchronization of the prescaler clock. these bits are read anytime. they should be written to only in test (special) mode; writing to them has no effect in normal modes. 7 6543 0 field gpten ? tffca ? reset 0000_0000 r/w r/w address ipsbar + 0x1a_0006, 0x1b_0006 figure 20-7. gpt system control register 1 (gptscr1) table 20-9. gptscr1 field descriptions bit(s) name description 7 gpten enables the general purpose timer. when the timer is disabled, only the registers are accessible. clearing gpten reduces power consumption. these bits are read anytime, write anytime. 1 gpt enabled 0 gpt and gpt counter disabled 6?5 ? reserved, should be cleared. 4 tffca timer fast flag clear all. en ables fast clearing of the main timer interrupt flag registers (gptflg1 and gptflg2) and the pa flag register (gptpaflg). tffca eliminates the software overhead of a separate clear sequence. see figure 20-8 . when tffca is set: ? an input capture read or a write to an output compare channel clears the corresponding channel flag, cxf. ? any access of the gpt count regist ers (gptcnth/l) clears the tof flag. ? any access of the pa counter register s (gptpacnt) clears both the paovf and paif flags in gptpaflg. writing logic 1s to the flags clea rs them only when tffca is clear. 1 fast flag clearing 0 normal flag clearing 3?0 ? reserved, should be cleared. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose timer modules (gpta and gptb) freescale semiconductor 20-9 figure 20-8. fast clear flag logic 20.5.7 gpt toggle-on-overflow register (gpttov) 20.5.8 gpt control register 1 (gptctl1) 7 6543 0 field ? tov reset 0000_0000 r/w r/w address ipsbar + 0x1a_0008, 0x1b_0008 figure 20-9. gpt toggle-on-overflow register (gpttov) table 20-10. gpttov field descriptions bit(s) name description 7?4 ? reserved, should be cleared. 3?0 tov toggles the output compare pin on overflow for each channel. this feature only takes effect when in output compare mode. when set, it takes precedence over forced output compare but not channel 3 override ev ents. these bits are read anytime, write anytime. 1 toggle output compare pin on overflow feature enabled 0 toggle output compare pin on overflow feature disabled 7 654321 0 field om3 ol3 om2 ol2 om1 ol1 om0 ol0 reset 0000_0000 r/w r/w address ipsbar + 0x1a_0009, 0x1b_0009 figure 20-10. gpt control register 1 (gptctl1) clear write gptc n registers read gptc n registers tffca data bit n write gptflg1 register c n f c n f flag mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose timer modules (gpta and gptb) 20-10 freescale semiconductor 20.5.9 gpt control register 2 (gptctl2) 20.5.10 gpt interrupt enable register (gptie) table 20-11. gptcl1 field descriptions bit(s) name description 7?0 omx/olx output mode/output leve l. selects the output action to be taken as a result of a successful output compare on each channel. when either om n or ol n is set and the ios n bit is set, the pin is an output regardle ss of the state of the corresponding ddr bit. these bits are read anytime, write anytime. 00 gpt disconnected from output pin logic 01 toggle oc n output line 10 clear oc n output line 11 set oc n line note: channel 3 shares a pin with the pulse accumulator input pin. to use the pai input, clear both the om3 and ol3 bits and clear the oc3m3 bit in the output compare 3 mask register. 7 654321 0 field edg3b edg3a edg2b edg2a edg1b edg1a edg0b edg0a reset 0000_0000 r/w r/w address ipsbar + 0x1a_000b, 0x1b_000b figure 20-11. gpt control register 2 (gptctl2) table 20-12. gptlctl2 field descriptions bit(s) name description 7?0 edg n [b:a] input capture edge control. configures the input captur e edge detector circuits for each channel. these bits are read anytime, write anytime. 00 input capture disabled 01 input capture on rising edges only 10 input capture on falling edges only 11 input capture on any edge (rising or falling) 7 6543 0 field ? ci reset 0000_0000 r/w r/w address ipsbar + 0x1a_000c, 0x1b_000c figure 20-12. gpt interrupt enable register (gptie) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose timer modules (gpta and gptb) freescale semiconductor 20-11 20.5.11 gpt system control register 2 (gptscr2) table 20-13. gptie field descriptions bit(s) name description 7?4 ? reserved, should be cleared. 3?0 c n i channel interrupt enable. enables the c[3:0]f flags in gpt flag register 1 to generate interrupt requests for each channel. these bits are read anytime, write anytime. 1 corresponding channel interrupt requests enabled 0 corresponding channel interrupt requests disabled 7 65432 0 field toi ? pupt rdpt tcre pr reset 0000_0000 r/w r/w address ipsbar + 0x1a_000d, 0x1b_000d figure 20-13. gpt system control register 2 (gptscr2) table 20-14. gptscr2 field descriptions bit(s) name description 7 toi enables timer overflow interrupt requests. 1 overflow interrupt requests enabled 0 overflow interrupt requests disabled 6 ? reserved, should be cleared. 5 pupt enables pull-up resistors on the gpt po rts when the ports are configured as inputs. 1 pull-up resistors enabled 0 pull-up resistors disabled 4 rdpt gpt drive reduction. reduces the output driver size. 1 output drive reduction enabled 0 output drive reduction disabled 3 tcre enables a counter reset after a channel 3 compare. 1 counter reset enabled 0 counter reset disabled note: when the gpt channel 3 registers contain 0x0000 and tcre is set, the gpt counter registers remain at 0x0000 all the time. when the gpt channel 3 registers contain 0xffff and tcre is set, tof does not get set even though the gpt counter registers go from 0xffff to 0x0000. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose timer modules (gpta and gptb) 20-12 freescale semiconductor 20.5.12 gpt flag register 1 (gptflg1) 20.5.13 gpt flag register 2 (gptflg2) 2?0 pr n prescaler bits. select the prescaler divisor for the gpt counter. 000 prescaler divisor 1 001 prescaler divisor 2 010 prescaler divisor 4 011 prescaler divisor 8 100 prescaler divisor 16 101 prescaler divisor 32 110 prescaler divisor 64 111 prescaler divisor 128 note: the newly selected prescaled clock doe s not take effect until the next synchronized edge of the prescaled clock w hen the clock count transitions to 0x0000.) 7 6543 0 field ? cf reset 0000_0000 r/w r/w address ipsbar + 0x1a_000e, 0x1b_000e figure 20-14. gpt flag register 1 (gptflg1) table 20-15. gptflg1 field descriptions bit(s) name description 7?4 ? reserved, should be cleared. 3?0 c n f channel flags. a channel flag is set when an input capture or output compare event occurs. these bits are read anytime, write an ytime (writing 1 clears the flag, writing 0 has no effect). note: when the fast flag clear all bit, gptscr1 [tffca], is set, an input capture read or an output compare write clears the corresponding channel flag. when a channel flag is set, it does not inhibit subsequent output compares or input captures. 76543 0 field tof ? reset 0000_0000 r/w r/w address ipsbar + 0x1a_000f, 0x1b_000f figure 20-15. gpt flag register 2 (gptflg2) table 20-14. gptscr2 field descriptions (continued) bit(s) name description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose timer modules (gpta and gptb) freescale semiconductor 20-13 note: when the fast flag clear all bit, gptscr1[tffca], is set, any access to the gpt counter regi sters clears gpt flag register 2. 20.5.14 gpt channel registers (gptc n ) table 20-16. gptflg2 field descriptions bit(s) name description 7 tof timer overflow flag. set when the gpt coun ter rolls over from 0x ffff to 0x0000. if the toi bit in gptscr2 is also set, tof ge nerates an interrupt request. this bit is read anytime, write anytime (writing 1 clears the flag, and writing 0 has no effect). 1 timer overflow 0 no timer overflow note: when the gpt channel 3 registers contai n 0xffff and tcre is set, tof does not get set even though the gpt counter r egisters go from 0xffff to 0x0000. when tof is set, it does not inhibit subsequent overflow events. 6?0 ? reserved, should be cleared. 15 0 field ccnt reset 0000_0000_0000_0000 r/w r/w address ipsbar + 0x1a_0010, 0x1a _0012, 0x1a_0014, 0x1a_0016, 0x1b_0010, 0x1b_0012, 0x1b_0014, 0x1b_0016 figure 20-16. gpt channel[0:3] register (gptc n ) table 20-17. gptc n field descriptions bit(s) name description 15?0 ccnt when a channel is configured for input capture (ios n = 0), the gpt channel registers latch the value of the free-running counter when a defined transition occurs on the corresponding input capture pin. when a channel is configured for output compare (ios n = 1), the gpt channel registers contain the output compare value. to ensure coherent reading of the gpt counte r, such that a timer rollover does not occur between back-to-back 8-bit reads, it is recommended that only word (16-bit) accesses be used. these bits are read anytim e, write anytime (for the output compare channel); writing to the input capture channel has no effect. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose timer modules (gpta and gptb) 20-14 freescale semiconductor 20.5.15 pulse accumulator co ntrol register (gptpactl) 7 6543 0 field ? pae pamod pedge clk paovi pai reset 0000_0000 r/w r/w address ipsbar + 0x1a_0018, 0x1b_0018 figure 20-17. pulse accumulator control register (gptpactl) table 20-18. gptpactl field descriptions bit(s) name description 7 ? reserved, should be cleared. 6 pae enables the pulse accumulator. 1 pulse accumulator enabled 0 pulse accumulator disabled note: the pulse accumulator can operate in event mode even when the gpt enable bit, gpten, is clear. 5 pamod pulse accumulator mode. selects event counter mode or gated time accumulation mode. 1 gated time accumulation mode 0 event counter mode 4 pedge pulse accumulator edge. selects falling or rising edges on the pai pin to increment the counter. in event counter mode (pamod = 0): 1 rising pai edge increments counter 0 falling pai edge increments counter in gated time accumulati on mode (pamod = 1): 1 low pai input enables divide-by-64 clock to pulse accumulator and trailing rising edge on pai sets paif flag. 0 high pai input enables divide-by-64 clock to pulse accumulator and trailing falling edge on pai sets paif flag. note: the timer prescaler generates the divide-by-64 clock. if the timer is not active, there is no divide-by-64 clock. to operate in gated time accumulation mode: 1. apply logic 0 to rsti pin. 2. initialize registers for pulse accumulator mode test. 3. apply appropriate level to pai pin. 4. enable gpt. 3?2 clk select the gpt counter input clock. changing the clk bits causes an immediate change in the gpt counter clock input. 00 gpt prescaler clock (when pae = 0, the gpt prescaler clock is always the gpt counter clock.) 01 paclk 10 paclk/256 11 paclk/65536 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose timer modules (gpta and gptb) freescale semiconductor 20-15 20.5.16 pulse accumulator flag register (gptpaflg) note when the fast flag clear all enable bi t, gptscr1[tffca], is set, any access to the pulse accumulator counter regist ers clears all the flags in gptpaflg. 1 paovi pulse accumulator overflow interrupt enable. enables the paovf flag to generate interrupt requests. 1 paovf interrupt requests enabled 0 paovf interrupt requests disabled 0 pai pulse accumulator input interrupt enable. enables the paif flag to generate interrupt requests. 1 paif interrupt requests enabled 0 paif interrupt requests disabled 72 1 0 field ? paovf paif reset 0000_0000 r/w r/w address ipsbar + 0x1a_0019, 0x1b_0019 figure 20-18. pulse accumulator flag register (gptpaflg) table 20-19. gptpaflg field descriptions bit(s) name description 7?2 ? reserved, should be cleared. 1 paovf pulse accumulator overflow flag. set when the 16-bit pulse accumulator rolls over from 0xffff to 0x0000. if the gptpactl[paovi] bit is also set, paovf generates an interrupt request. clear paovf by writing a 1 to it. this bit is read anytime, write anytime. (writing 1 clears t he flag; writing 0 has no effect.) 1 pulse accumulator overflow 0 no pulse accumulator overflow 0 paif pulse accumulator input flag. set when the selected edge is detec ted at the pai pin. in event counter mode, the event edge sets paif. in gated time accumulation mode, the trailing edge of the gate signal at the pai pin sets paif. if the pai bit in gptpactl is also set, paif generates an interrupt request. clear paif by writing a 1 to it. 1 active pai input 0 no active pai input table 20-18. gptpactl field descriptions (continued) bit(s) name description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose timer modules (gpta and gptb) 20-16 freescale semiconductor 20.5.17 pulse accumulator counter register (gptpacnt) 20.5.18 gpt port data register (gptport) 15 0 field pacnt reset 0000_0000_0000_0000 r/w r/w address ipsbar + 0x1a_001a, 0x1b_001b figure 20-19. pulse accumulator counter register (gptpacnt) table 20-20. gptpacr field descriptions bit(s) name description 15?0 pacnt contains the number of active input edges on the pai pin since the last reset. note: reading the pulse accumulator counter registers immediately after an active edge on the pai pin may miss the last count since the input first has to be synchronized with the bus clock. to ensure coherent reading of the pa c ounter, such that the counter does not increment between back-to-back 8-bit reads, it is recommended that only word (16-bit) accesses be used. these bits ar e read anytime, write anytime. 7 6543 0 field ? portt reset 0000_0000 r/w r/w address ipsbar + 0x1a_001d, 0x1b_001d figure 20-20. gpt port data register (gptport) table 20-21. gptport field descriptions bit(s) name description 7?4 ? reserved, should be cleared. 3?0 portt gpt port input capture/output compare data. data written to gptport is buffered and drives the pins only when they are configured as general-purpose outputs. reading an input (ddr bit = 0) reads the pin state; reading an output (ddr bit = 1) reads the latched value. writing to a pin configured as a gpt output does not change the pin state. these bits are read anytime (read pin state when corresponding portt n bit is 0, read pin driver state when corresponding gptddr bit is 1), write anytime. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose timer modules (gpta and gptb) freescale semiconductor 20-17 20.5.19 gpt port data di rection register (gptddr) 20.6 functional description the general purpose timer (gpt) module is a 16-bit, 4-channel ti mer with input capture and output compare functions and a pulse accumulator. 20.6.1 prescaler the prescaler divides the module clock by 1, 2, 4, 8, 16, 32, 64, or 128. th e gptscr2[pr] bits select the prescaler divisor. 20.6.2 input capture clearing an i/o select bit, ios n, configures channel n as an input capture channel. the input capture function captures the time at which an external event occurs. when an active edge occurs on the pin of an input capture channel, the timer tr ansfers the value in the gpt counter into the gpt channel registers, gptc n. the minimum pulse width for the input captur e input is greater th an two module clocks. the input capture function does not fo rce data direction. the gpt port data direction register controls the data direction of an input capture pin. pin conditions such as risi ng or falling edges can trigger an input capture only on a pin configured as an input. an input capture on channel n sets the c nf flag. the c n i bit enables the c nf flag to generate interrupt requests. 7 6543 0 field ? ddrt gpt function ? ic/oc pulse accumulator function ? pai ? reset 0000_0000 r/w r/w address ipsbar + 0x1a_001e, 0x1b_001e figure 20-21. gpt port data direction register (gptddr) table 20-22. gptddr field descriptions bit(s) name description 7?4 ? reserved, should be cleared. 3?0 ddrt control the port logic of portt n . reset clears the portt n data direction register, configuring all gpt port pins as inputs. thes e bits are read anytime, write anytime. 1 corresponding pin configured as output 0 corresponding pin configured as input mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose timer modules (gpta and gptb) 20-18 freescale semiconductor 20.6.3 output compare setting an i/o se lect bit, ios n, configures channel n as an output compare channel. the output compare function can generate a periodic pul se with a programmable polarity, duration, and frequency. when the gpt counter reaches the value in the channel register s of an output compare channel, the timer can set, clear, or toggle the channel pin. an output compare on channel n sets the c n f flag. the c ni bit enables the c nf flag to generate interrupt requests. the output mode and level bits, om n and oln , select, set, clear, or toggl e on output compare. clearing both om n and oln disconnects the pin from the output logic. setting a force output compare bit, foc n, causes an output compare on channel n. a forced output compare does not set the channel flag. a successful output compare on channel 3 overrid es output compares on all other output compare channels. a channel 3 output compare can cause bits in the output compar e 3 data register to transfer to the gpt port data register, dependi ng on the output compar e 3 mask register. th e output compare 3 mask register masks the bits in the out put compare 3 data register. the gp t counter reset enable bit, tcre, enables channel 3 output compares to reset the gp t counter. a channel 3 output compare can reset the gpt counter even if the oc3/pai pin is being used as the pulse accumulator input. an output compare overrides the data direction bit of the output compar e pin but does not change the state of the data direction bit. writing to the portt n bit of an output compare pin does not affect the pin state. the value written is stored in an internal latch. when the pin becomes availa ble for general-purpose ou tput, the last value written to the bit appears at the pin. 20.6.4 pulse accumulator the pulse accumulator (pa) is a 16-bit counter that can operate in two modes: 1. event counter mode: counts edge s of selected polarity on the pulse accumulator input pin, pai 2. gated time accumulation mode: count s pulses from a divide-by-64 clock the pa mode bit, pamod, selects the mode of operation. the minimum pulse width for the pai input is greater than two module clocks. 20.6.5 event counter mode clearing the pamod bit configures the pa for even t counter operation. an active edge on the pai pin increments the pa. the pa edge b it, pedge, selects falli ng edges or rising edges to increment the pa. an active edge on the pai pin sets th e pa input flag, paif. the pa input interrupt enable bit, pai, enables the paif flag to generate interrupt requests. note the pai input and gpt channel 3 use th e same pin. to use the pai input, disconnect it from the output logic by clearing th e channel 3 output mode and output level bits, om3 and ol 3. also clear the channel 3 output compare 3 mask bit, oc3m3. the pa counter register, gptpacnt , reflects the number of active i nput edges on the pai pin since the last reset. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose timer modules (gpta and gptb) freescale semiconductor 20-19 the pa overflow flag, paovf, is set when the pa rolls over from 0xffff to 0x0000. the pa overflow interrupt enable bit, paovi, enables the paovf flag to generate interrupt requests. note the pa can operate in event counter mode even when the gpt enable bit, gpten, is clear. 20.6.6 gated time accumulation mode setting the pamod bit configures the pa for gated time accumulation operation. an active level on the pai pin enables a divide-by-64 clock to drive the pa. the pa edge bit, pedge, selects low levels or high levels to enable the divide-by-64 clock. the trailing edge of the active level at the pai pin sets the pa input flag, pa if. the pa input interrupt enable bit, pai, enables the paif flag to generate interrupt requests. note the pai input and gpt channel 3 use th e same pin. to use the pai input, disconnect it from the output logic by clearing th e channel 3 output mode and output level bits, om3 and ol 3. also clear the channel 3 output compare mask bit, oc3m3. the pa counter register, gptpacnt, reflects the numb er of pulses from the di vide-by-64 clock since the last reset. note the gpt prescaler generates the divi de-by-64 clock. if the timer is not active, there is no divide-by-64 clock. figure 20-22. channel 3 output compare/pulse accumulator logic 20.6.7 general-purpose i/o ports an i/o pin used by the timer defaul ts to general-purpose i/o unless an internal function which uses that pin is enabled. the portt n pins can be configured for either an input capture functi on or an output compare function. the ios n bits in the gpt ic/oc select register configure the portt n pins as either input capture or output compare pins. pa d om3 ol3 channel 3 output compare pulse accumulator oc3m3 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose timer modules (gpta and gptb) 20-20 freescale semiconductor the portt n data direction register controls the data direction of an input capture pin. external pin conditions trigger input captures on input capture pins conf igured as inputs. to configure a pin for input capture: 1. clear the pin?s ios bit in gptios. 2. clear the pin?s ddr bit in portt nddr. 3. write to gptctl2 to select the input edge to detect. portt n ddr does not affect the data direction of an output compare pin. the output compare function overrides the data direction regist er but does not affect the state of the data direction register. to configure a pin for output compare: 1. set the pin?s ios bit in gptios. 2. write the output compare value to gptc n. 3. clear the pin?s ddr bit in portt nddr. 4. write to the om n /oln bits in gptctl1 to select the output action. table 20-23 shows how various timer setti ngs affect pin functionality. table 20-23. gpt settings and pin functions gpte n ddr 1 gptios edgx [b:a] omx/ olx 2 oc3mx 3 pin data dir. pin driven by pin function comments 00x 4 x x x in ext. digital input gpt disabled by gpten = 0 0 1 x x x x out data reg. digital output gpt disabled by gpten = 0 1 0 0 (ic) 0 (ic disable d) x 0 in ext. digital input input capture disabled by edg n setting 1 1 0 0 x 0 out data reg. digital output input capture disabled by edg n setting 1 0 0 <> 0 x 0 in ext. ic and digital input normal settings for input capture 1 1 0 <> 0 x 0 out data reg. digital output in put capture of data driven to output pin by cpu 1 0 0 <> 0 x 1 in ext. ic and digital input oc3m setting has no effect because ios = 0 1 1 0 <> 0 x 1 out data reg. digital output oc3m setting has no effect because ios = 0; input capture of data driven to output pin by cpu 101 (oc)x (3) 0 5 0 in ext. digital input output compare takes place but does not affect the pin because of the om n /ol n setting 1 1 1 x 0 0 out data reg. digital output output compare takes place but does not affect the pin because of the om n /ol n setting 1 0 1 x <> 0 0 out oc action output compare pin readable only if ddr = 0 (5) 1 1 1 x <> 0 0 out oc action output compare pin driven by oc action (5) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose timer modules (gpta and gptb) freescale semiconductor 20-21 20.7 reset reset initializes the gpt registers to a known start up state as described in section 20.5, ?memory map and registers .? 20.8 interrupts table 20-24 lists the interrupt reque sts generated by the timer. 20.8.1 gpt channel interrupts (c n f) a channel flag is set when an input capture or output compare event occu rs. clear a channe l flag by writing a 1 to it. 10 1 x x 1outoc action/ oc3d n output compare (ch 3) pin readable only if ddr = 0 6 11 1 x x 1outoc action/ oc3d n output compare/ oc3d n (ch 3) pin driven by channel oc action and oc3d n via channel 3 oc (6) 1 when ddr set the pin as input (0), reading the data register will return the state of the pin. wh en ddr set the pin as output ( 1), reading the data register will return the cont ent of the data latch. pin conditions such as rising or falling edges can trigger an input capture on a pin configured as an input. 2 om n /ol n bit pairs select the output action to be taken as a result of a successful output compare. when either om n or ol n is set and the ios n bit is set, the pin is an output regardless of the state of the corresponding ddr bit. 3 setting an oc3m bit configures the corresponding portt n pin to be output. oc3m n makes the portt n pin an output regardless of the data direction bit when the pin is configured for output compare (ios n = 1). the oc3m n bits do not change the state of the portt n ddr bits. 4 x = don?t care 5 an output compare overrides the data directi on bit of the output compare pin but does not change the state of the data directio n bit. enabling output compare disables data register drive of the pin. 6 a successful output compare on channel 3 c auses an output value determined by oc3d n value to temporarily override the output compare pin state of any other output compare channel.the next oc action for the specific channel will still be output to the p in. a channel 3 output compare can cause bits in the output compare 3 data register to transfer to the gpt port data register, depending on the output compare 3 mask register. table 20-24. gpt interrupt requests interrupt request flag enable bit channel 3 ic/oc c3f c3i channel 2 ic/oc c2f c2i channel 1 ic/oc c1f c1i channel 0 ic/oc c0f c0i pa overflow paovf paovi pa input paif pai timer overflow tof toi table 20-23. gpt settings and pin functions (continued) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose timer modules (gpta and gptb) 20-22 freescale semiconductor note when the fast flag clear all bit, gpts cr1[tffca], is set, an input capture read or an output compare write cl ears the corresponding channel flag. when a channel flag is set, it does not inhibit subsequent output compares or input captures 20.8.2 pulse accumulator overflow (paovf) paovf is set when the 16-bit pulse accumulator rolls over from 0xffff to 0x0000. if the paovi bit in gptpactl is also set, paovf generates an interrupt request. clear paovf by writing a 1 to this flag. note when the fast flag clear all enable bi t, gptscr1[tffca], is set, any access to the pulse accumulator counter regist ers clears all the flags in gptpaflg. 20.8.3 pulse accumulator input (paif) paif is set when the selected edge is detected at the pai pin. in ev ent counter mode, the event edge sets paif. in gated time accumulation mode , the trailing edge of th e gate signal at the pai pin sets paif. if the pai bit in gptpactl is also set, paif generates an interrupt request. clear pa if by writing a 1 to this flag. note when the fast flag clear all enable bi t, gptscr1[tffca], is set, any access to the pulse accumulator counter regist ers clears all the flags in gptpaflg. 20.8.4 timer overflow (tof) tof is set when the gpt counter rolls over from 0xffff to 0x0000. if th e gptscr2[toi] bit is also set, tof generates an interrupt request. cl ear tof by writing a 1 to this flag. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose timer modules (gpta and gptb) freescale semiconductor 20-23 note when the gpt channel 3 registers c ontain 0xffff and tcre is set, tof does not get set even though the gpt counter registers go from 0xffff to 0x0000. when the fast flag clear all bit, gp tscr1[tffca], is set, any access to the gpt counter registers clear s gpt flag register 2. when tof is set, it does not i nhibit future overflow events. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose timer modules (gpta and gptb) 20-24 freescale semiconductor mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor 21-1 chapter 21 dma timers (dtim0?dtim3) 21.1 introduction this chapter describes the configuration and operation of the four direct memory access (dma) timer modules (dtim0, dtim1, dtim2, and dtim3). these 32-bit timers provide input capture and reference compare capabilities with optional signaling of events using interrupt s or dma triggers. additionally, programming examples are included. note the designation n appears throughout this section to refer to registers or signals associated with one of the four identical time r modules: dtim0, dtim1, dtim2, or dtim3. 21.1.1 overview each dma timer module has a separate register set for configuration and control. the timers can be configured to operate from the inte rnal bus clock or from an extern al clocking source using the dtin n signal. if the internal bus clock is selected, it can be divided by 16 or 1. the selected clock source is routed to an 8-bit programmable prescal er that clocks the actual dma timer counter register (dtcn n). using the dtmr n, dtxmr n, dtcr n, and dtrr n registers, the dma timer may be configured to assert an output signal, generate an interrupt, or request a dma transfer on a particular event. note the gpio module must be configured to enable the peripheral function of the appropriate pins (refer to chapter 26, ?general purpose i/o module? ) prior to configuring the dma timers. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 dma timers (dtim0?dtim3) 21-2 freescale semiconductor figure 21-1 is a block diagram of one of the four identical timer modules. figure 21-1. dma timer block diagram 21.1.2 features each dma timer module has: ? maximum timeout period of 219,902 seconds at 80 mhz (~61 hours) ? 12.5-ns resolution at 80 mhz ? programmable sources for the cloc k input, including external clock ? programmable prescaler ? input-capture capability with progr ammable trigger edge on input pin ? programmable mode for the output pin on reference compare ? free run and restart modes ? programmable interrupt or dma request on input capture or reference-compare dma timer divider dma timer mode register (dtmr n ) prescaler mode bits dma timer counter register (dtcn n ) 31 0 dma timer reference register (dtrr n ) 31 0 dma timer capture register (dtcr n ) 31 0 dma timer event register (dter n ) capture detection clock (contains incrementing value) (reference value for comparison with dtcn) (indicates capture or when dtcn = dtrr n ) interrupt request clock generator dma timer extended mode register (dtxmr n ) dma request 0 0 15 7 7 0 internal bus clock (1 or 16 ) dma timer internal bus to/from dma timer registers (latches dtcn value when triggered by dtin n) dtout n dtin n mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 dma timers (dtim0?dtim3) freescale semiconductor 21-3 21.2 memory map/register definition the timer module registers, shown in table 21-1 , can be modified at any time. 21.2.1 dma timer mode registers (dtmr n ) the dtmr n registers program the prescaler and various timer modes. table 21-1. dma timer module memory map ipsbar offset register width (bits) access reset value section/page dma timer 0 dma timer 1 dma timer 2 dma timer 3 0x00_0400 0x00_0440 0x00_0480 0x00_04c0 dma timer n mode register (dtmr n ) 16 r/w 0x0000 21.2.1/21-3 0x00_0402 0x00_0442 0x00_0482 0x00_04c2 dma timer n extended mode register (dtxmr n ) 8 r/w 0x00 21.2.2/21-5 0x00_0403 0x00_0443 0x00_0483 0x00_04c3 dma timer n event register (dter n )8 r / w 0 x 0 0 21.2.3/21-5 0x00_0404 0x00_0444 0x00_0484 0x00_04c4 dma timer n reference register (dtrr n ) 32 r/w 0xffff_ffff 21.2.4/21-7 0x00_0408 0x00_0448 0x00_0488 0x00_04c8 dma timer n capture register (dtcr n ) 32 r/w 0x0000_0000 21.2.5/21-7 0x00_040c 0x00_044c 0x00_048c 0x00_04cc dma timer n counter register (dtcn n ) 32 r 0x0000_0000 21.2.6/21-8 ipsbar offset: 0x00_0400 (dtmr0) 0x00_0440 (dtmr1) 0x00_0480 (dtmr2) 0x00_04c0 (dtmr3) access: user read/write 1514131211109876543210 r ps ce om orri frr clk rst w reset000000000 0000000 figure 21-2. dtmr n registers mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 dma timers (dtim0?dtim3) 21-4 freescale semiconductor table 21-2. dtmr n field descriptions field description 15?8 ps prescaler value. divides the clock input (internal bus clock/(16 or 1) or clock on dtin n ) 0x00 1 ... 0xff 256 7?6 ce capture edge. 00 disable capture event output. timer in reference mode. 01 capture on rising edge only 10 capture on falling edge only 11 capture on any edge 5 om output mode. 0 active-low pulse for one internal bus clock cycle (12.5-ns resolution at 80 mhz) 1 toggle output. 4 orri output reference request, interrupt enable. if orri is set when dter n [ref] is set, a dma request or an interrupt occurs, depending on the value of dtxmr n [dmaen] (dma request if set, interrupt if cleared). 0 disable dma request or interrupt for reference reached (does not affect dma request or interrupt on capture function). 1 enable dma request or interrupt upon reaching the reference value. 3 frr free run/restart 0 free run. timer count continues increm enting after reaching the reference value. 1 restart. timer count is reset immediately after reaching the reference value. 2?1 clk input clock source for the timer. avoid setting clk when rst is already set. doing so causes clk to zero (stop counting). 00 stop count 01 internal bus clock divided by 1 10 internal bus clock divided by 16. this clock source is not synchronized with the timer; therefore, successive time-outs may vary slightly. 11 dtin n pin (falling edge) 0 rst reset timer. performs a software timer reset similar to an external reset, although other r egister values can be written while rst is cleared. a transition of rst from 1 to 0 resets register values. the timer counter is not clocked unless the timer is enabled. 0 reset timer (software reset) 1 enable timer mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 dma timers (dtim0?dtim3) freescale semiconductor 21-5 21.2.2 dma timer extended mode registers (dtxmr n ) the dtxmr n registers program dma request a nd increment modes for the timers. 21.2.3 dma timer event registers (dter n ) dter n, shown in figure 21-4 , reports capture or reference events by setting dter n[cap] or dter n[ref]. this reporting happens regardless of th e corresponding dma request or interrupt enable values, dtxmr n[dmaen] and dtmr n [orri,ce]. writing a 1 to dter n [ref] or dter n[cap] clears it (writing a 0 does not affect bit value); both bits can be cleared at the same time. if conf igured to generate an interrupt requ est, clear ref and cap early in the interrupt service routine so the timer module can nega te the interrupt request signal to the interrupt controller. if configured to gene rate a dma request, processing of the dma data transfer automatically clears the ref and cap flags via the internal dma ack signal. ipsbar offset: 0x00_0402 (dtxmr0) 0x00_0442 (dtxmr1) 0x00_0482 (dtxmr2) 0x00_04c2 (dtxmr3) access: user read/write 76543210 r dmaen 000000 mode16 w r e s e t :00000000 figure 21-3. dtxmr n registers table 21-3. dtxmr n field descriptions field description 7 dmaen dma request. enables dma request output on counter reference match or capture edge event. 0 dma request disabled 1 dma request enabled 6?1 reserved, must be cleared. 0 mode16 selects the increment mode for the timer. setting mode16 is intended to exercise the upper bits of the 32-bit timer in diagnostic software without requiring the timer to count through its entire dynamic range. when set, the counter?s upper 16 bits mirror its lower 16 bits. all 32 bits of the counter remain compared to the reference value. 0 increment timer by 1 1 increment timer by 65,537 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 dma timers (dtim0?dtim3) 21-6 freescale semiconductor ipsbar offset: 0x 00_04 03 (dter0) 0x 00_044 3 (dter1) 0x 00_048 3 (dter2) 0x 00_04c 3 (dter3) access: user read/write 76543210 r000000r e fc a p w w1c w1c r e s e t :00000000 figure 21-4. dter n registers table 21-4. dter n field descriptions field description 7?2 reserved, must be cleared. 1 ref output reference event. the counter value (dtcn n ) equals dtrr n . writing a 1 to ref clears the event condition. writing a 0 has no effect. 0 cap capture event. the counter value has been latched into dtcr n . writing a 1 to cap clears the event condition. writing a 0 has no effect. ref dtmr n [orri] dtxmr n [dmaen] 0x x no event 1 0 0 no request asserted 1 0 1 no request asserted 1 1 0 interrupt request asserted 1 1 1 dma request asserted cap dtmr n [ce] dtxmr n [dmaen] 0xx x no event 1 00 0 disable capture event output 1 00 1 disable capture event output 1 01 0 capture on rising edge and trigger interrupt 1 01 1 capture on rising edge and trigger dma 1 10 0 capture on falling edge and trigger interrupt 1 10 1 capture on falling edge and trigger dma 1 11 0 capture on any edge and trigger interrupt 1 11 1 capture on any edge and trigger dma mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 dma timers (dtim0?dtim3) freescale semiconductor 21-7 21.2.4 dma timer reference registers (dtrr n ) as part of the output-compare function, each dtrr n contains the reference value compared with the respective free-running timer counter (dtcnn). the reference value is matched when dtcn n equals dtrr n. the prescaler indicates that dtcn n should be incremented again. therefore, the re ference register is matched after dtrr n + 1 time intervals. 21.2.5 dma timer capture registers (dtcr n ) each dtcr n latches the corresponding dtcn n value during a capture operation when an edge occurs on dtin n, as programmed in dtmr n. the internal bus clock is assu med to be the clock source. dtin n cannot simultaneously func tion as a clocking source and as an input capture pin. indeterminate operation results if dtin n is set as the clock source when the input capture mode is used. ipsbar offset: 0x00_0404 (dtrr0) 0x00_0444 (dtrr1) 0x00_0484 (dtrr2) 0x00_04c4 (dtrr3) access: user read/write 313029282726252423222120191817161514131211109876543210 r ref (32-bit reference value) w reset11111111111111111111111111111111 figure 21-5. dtrr n registers table 21-5. dtrr n field descriptions field description 31?0 ref reference value compared with the respective free-running timer counter (dtcn n ) as part of the output-compare function. ipsbar offset: 0x00_0408 ( dtcr0 ) 0x00_0448 ( dtcr1 ) 0x00_0488 ( dtcr2 ) 0x00_04c8 ( dtcr3 ) access: user read-only 313029282726252423222120191817161514131211109876543210 r cap (32-bit capture counter value) w reset00000000000000000000000000000000 figure 21-6. dtcr n registers table 21-6. dtcr n field descriptions field description 31?0 cap captures the corresponding dtcn n value during a capture operation when an edge occurs on dtin n , as programmed in dtmr n . mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 dma timers (dtim0?dtim3) 21-8 freescale semiconductor 21.2.6 dma timer counters (dtcn n ) the current value of the 32-bit timer counter can be read at anytime wi thout affecting counting. writes to dtcn n clear the timer counter. the timer counter incremen ts on the clock source ri sing edge (internal bus clock divided by 1, internal bus clock divided by 16, or dtin n). 21.3 functional description 21.3.1 prescaler the prescaler clock input is selected from the internal bus clock (f sys divided by 1 or 16) or from the corresponding timer input, dtin n. dtin n is synchronized to the internal bus clock, and the synchronization delay is between two and thre e internal bus clocks. the corresponding dtmr n [clk] selects the clock input source. a pr ogrammable prescaler divi des the clock input by va lues from 1 to 256. the prescaler output is an input to the 32-bit counter, dtcn n. 21.3.2 capture mode each dma timer has a 32-bit ti mer capture register (dtcr n) that latches the counter value when the corresponding input capture edge detector senses a defined dtin n transition. the capture edge bits (dtmr n[ce]) select the type of transition that triggers the capture and sets the timer event register capture event bit, dter n [cap]. if dter n[cap] and dtxmr n [dmaen] are set, a dma re quest is asserted. if dter n [cap] is set and dtxmr n[dmaen] is cleared, an interrupt is asserted. 21.3.3 reference compare each dma timer can be configured to count up to a reference value. if the reference value is met, dter n [ref] is set. ?if dtmr n[orri] is set and dtxmr n[dmaen] is cleared, an interrupt is asserted. ?if dtmr n[orri] and dtxmr n [dmaen] are set, a dma request is asserted. ipsbar offset: 0x00_040c ( dtcn0 ) 0x00_044c ( dtcn1 ) 0x00_048c ( dtcn2 ) 0x00_04cc ( dtcn3 ) access: user read/write 313029282726252423222120191817161514131211109876543210 r cnt (32-bit timer counter value count) w reset00000000000000000000000000000000 figure 21-7. dma timer counters (dtcn n ) table 21-7. dtcn n field descriptions field description 31?0 cnt timer counter. can be read at anytime without affe cting counting and any write to this field clears it. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 dma timers (dtim0?dtim3) freescale semiconductor 21-9 if the free run/restart bit (dtmr n[frr]) is set, a new count starts. if it is clear, the timer keeps running. 21.3.4 output mode when a timer reaches the reference value selected by dtrr, it can send an output signal on dtout n. dtoutn can be an active-low pulse or a toggle of the current output, as selected by the dtmr n [om] bit. 21.4 initialization/application information the general-purpose timer modules typically, but not necessarily , follow this program order: ? the dtmr n and dtxmr n registers are configured for th e desired function and behavior. ? count and compare to a reference value stored in the dtrr n register ? capture the timer value on an edge detected on dtin n ? configure dtout n output mode ? increment counter by 1 or by 65,537 (16-bit mode) ? enable/disable interrupt or dma request on counter reference ma tch or capture edge ? the dtmr n [clk] register is configured to select the clock source to be routed to the prescaler. ? internal bus clock (can be divided by 1 or 16) ?dtin n, the maximum value of dtin n is 1/5 of the internal bus clock, as described in the device?s electrical characteristics note dtin n may not be configured as a cloc k source when the timer capture mode is selected or inde terminate operation results. ? the 8-bit dtmr n[ps] prescaler value is set. ? using dtmr n[rst], counter is cleared and started. ? timer events are managed with an interrupt se rvice routine, a dma request, or by a software polling mechanism. 21.4.1 code example the following code provides an exam ple of how to initialize and use dma timer0 for co unting time-out periods. dtmr0 equ ipsbarx+0x400 ;timer0 mode register dtmr1 equ ipsbarx+0x440 ;timer1 mode register dtrr0 equ ipsbarx+0x404 ;timer0 reference register dtrr1 equ ipsbarx+0x444 ;timer1 reference register dtcr0 equ ipsbarx+0x408 ;timer0 capture register dtcr1 equ ipsbarx+0x448 ;timer1 capture register dtcn0 equ ipsbarx+0x40c ;timer0 counter register dtcn1 equ ipsbarx+0x44c ;timer1 counter register dter0 equ ipsbarx+0x403 ;timer0 event register dter1 equ ipsbarx+0x443 ;timer1 event register * tmr0 is defined as: * *[ps] = 0xff, divide clock by 256 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 dma timers (dtim0?dtim3) 21-10 freescale semiconductor *[ce] = 00 disable capture event output *[om] = 0 output=active-low pulse *[orri] = 0, disable ref. match output *[frr] = 1, restart mode enabled *[clk] = 10, internal bus clock/16 *[rst] = 0, timer0 disabled move.w #0xff0c,d0 move.w d0,tmr0 move.l #0x0000,d0;writing to the timer counter with any move.l do,tcn0 ;value resets it to zero move.l #0xafaf,do ;set the timer0 reference to be move.l #d0,trr0 ;defined as 0xafaf the simple example below uses timer0 to count time-out loops. a time-out occurs when the reference value, 0xafaf, is reached. timer0_ex clr.l do clr.l d1 clr.l d2 move.l #0x0000,d0 move.l d0,tcn0 ;reset the counter to 0x0000 move.b #0x03,d0 ;writing ones to ter0[ref,cap] move.b d0,ter0 ;clears the event flags move.w tmr0,d0 ;save the contents of tmr0 while setting bset #0,d0 ;the 0 bit. this enables timer 0 and starts counting move.w d0,tmr0 ;load the value back into the register, setting tmr0[rst] t0_loop move.b ter0,d1 ;load ter0 and see if btst #1,d1 ;ter0[ref] has been set beq t0_loop addi.l #1,d2 ;increment d2 cmp.l #5,d2 ;did d2 reach 5? (i.e. timer ref has timed) beq t0_finish ;if so, end timer0 example. otherwise jump back. move.b #0x02,d0 ;writing one to ter0[ref] clears the event flag move.b d0,ter0 jmp t0_loop t0_finish halt ;end processing. example is finished 21.4.2 calculating time-out values equation 21-1 determines time-out periods for various reference values: eqn. 21-1 when calculating time-out periods, add one to the prescaler to simplify calculating, because dtmr n [ps] equal to 0x00 yields a pr escaler of one, and dtmr n [ps] equal to 0xff yields a prescaler of 256. timeout period 1 clock frequency ? () 1 or 16 () dtmr n [ps] 1 + () dtrr n [ref] 1+ () = mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 dma timers (dtim0?dtim3) freescale semiconductor 21-11 for example, if a 80-mhz time r clock is divided by 16, dtmr n [ps] equals 0x7f, and the timer is referenced at 0x1312c (78,124 decima l), the time-out period is: eqn. 21-2 timeout period 1 80 10 6 -------------------- 16 127 1+ () 78124 1+ () 2.00 seconds == mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 dma timers (dtim0?dtim3) 21-12 freescale semiconductor mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor 22-1 chapter 22 queued serial peripheral interface (qspi) 22.1 introduction this chapter describes the queued seri al peripheral inte rface (qspi) module. 22.1.1 block diagram figure 22-1 illustrates the qspi module. figure 22-1. qspi block diagram queue control block queue pointer 4 done comparator end queue pointer status regs delay counter control logic control regs 80-byte qspi ram chip selects command divide by 2 baud rate generator msb lsb logic array qspi_clk qspi_din 8 /16 bit shift reg . rx/tx data reg. qspi_dout 4 4 internal bus qspi address register qspi data register internal bus clock (f sys ) qspi_cs[3:0] mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued serial peripheral interface (qspi) 22-2 freescale semiconductor 22.1.2 overview the queued serial peripheral interface module provides a serial periphe ral interface with queued transfer capability. it allows users to queue up to 16 tran sfers at once, eliminating cpu intervention between transfers. transfer ram in the qspi is indirectly accessible us ing address and data registers. note the gpio module must be configured to enable the peripheral function of the appropriate pins (refer to chapter 26, ?general purpose i/o module? ) prior to configuring the qspi module. 22.1.3 features features include: ? programmable queue to support up to 16 transfers without user intervention ? 80 bytes of data storage provided ? supports transfer sizes of 8 to 16 bits in 1-bit increments ? four peripheral chip-select lines for control of up to 15 devices (all ch ip selects may not be available on all devices. see chapter 14, ?signal descriptions,? for details on which chip-selects are pinned-out.) ? baud rates from 156.9 kbps to 20 mbps at 80 mhz internal bus frequency ? programmable delays before and after transfers ? programmable qspi clock phase and polarity ? supports wraparound mode for continuous transfers 22.1.4 modes of operation because the qspi module only operates in master m ode, the master bit in the qspi mode register (qmr[mstr]) must be set for the qspi to function properly. if the master bit is not set, qspi activity is indeterminate. the qspi can initiate serial transfers but ca nnot respond to transfers initiated by other qspi masters. 22.2 external signal description the module provides access to as many as 15 devi ces with a total of seven signals: qspi_dout, qspi_din, qspi_clk, qspi_cs[3:0]. peripheral chip-selec t signals, qspi_cs n , are used to select an external device as th e source or destination for serial data transfer. signals are asserted when a command in the queue is executed. more than one chip-select signal can be asserted simultaneously. although qspi_csn signals function as si mple chip selects in most appl ications, up to 15 devices can be selected by decoding them with an external 4-to-16 decoder. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued serial peripheral interface (qspi) freescale semiconductor 22-3 22.3 memory map/register definition table 22-2 is the qspi register memory map. reading reserved locations returns zeros. 22.3.1 qspi mode register (qmr) the qmr, shown in figure 22-2 , determines the basic operating modes of the q spi module. parameters such as qspi_clk polarity and phase, baud rate , master mode operation, and transfer size are determined by this register. note because the qspi doe s not operate in slave mode , the master mode enable bit (qmr[mstr]) must be set for th e qspi module to operate correctly. table 22-1. qspi input and output signals and functions signal name hi-z or actively driven function data output (qspi_dout) configurable serial data output from qspi data input (qspi_din) n/a serial data input to qspi serial clock (qspi_clk) actively driven clock output from qspi peripheral chip selects (qspi_cs n ) actively driven peripheral selects from qspi table 22-2. qspi memory map ipsbar offset 1 1 addresses not assigned to a register and undefined register bits are reserved for expansion. register width (bits) access reset value section/page 0x00_0340 qspi mode register (qmr) 16 r/w 0x0104 22.3.1/22-3 0x00_0344 qspi delay register (qdlyr) 16 r/w 0x0404 22.3.2/22-5 0x00_0348 qspi wrap register (qwr) 16 r/w 2 2 see the register description for special case s. some bits may be read- or write-only. 0x0000 22.3.3/22-6 0x00_034c qspi interrupt register (qir) 16 r/w 2 0x0000 22.3.4/22-6 0x00_0350 qspi address register (qar) 16 r/w 2 0x0000 22.3.5/22-7 0x00_0354 qspi data register (qdr) 16 r/w 0x0000 22.3.6/22-8 ipsbar offset: 0x00_0340 (qmr) access: user read/write 1514131211109 876543210 r mstr 0 bits cpol cpha baud w reset0 0 0000010 0000100 figure 22-2. qspi mode register (qmr) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued serial peripheral interface (qspi) 22-4 freescale semiconductor table 22-3. qmr field descriptions field description 15 mstr master mode enable. 0 reserved, do not use. 1 the qspi is in master mode. must be se t for the qspi module to operate correctly. 14 reserved, must be cleared. 13?10 bits transfer size. determines the number of bits to be transferred for each entry in the queue. 9 cpol clock polarity. defines the clock polarity of qspi_clk. 0 the inactive state value of qspi_clk is logic level 0. 1 the inactive state value of qspi_clk is logic level 1. 8 cpha clock phase. defines the qspi_clk clock-phase. 0 data captured on the leading edge of qspi_clk and changed on the following edge of qspi_clk. 1 data changed on the leading edge of qspi_clk a nd captured on the follo wing edge of qspi_clk. 7?0 baud baud rate divider. the baud rate is selected by writing a va lue in the range 2?255. a value of zero disables the qspi. a value of 1 is an invalid setting. the desired qspi_clk baud rate is related to the internal bus clock and qmr[baud] by the following expression: qmr[baud] = f sys/ /(2 [desired qspi_clk baud rate]) bits bits per transfer 0000 16 0001?0111 reserved 1000 8 1001 9 1010 10 1011 11 1100 12 1101 13 1110 14 1111 15 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued serial peripheral interface (qspi) freescale semiconductor 22-5 figure 22-3 shows an example of a qspi clocking and data transfer. figure 22-3. qspi clocking and data transfer example 22.3.2 qspi delay register (qdlyr) the qdlyr is used to initiate master mode transfers and to set va rious delay parameters. ipsbar offset: 0x00_0344 (qdlyr) access: user read/write 1514131211109 876543210 r spe qcd dtl w reset0 0 0001000 0000100 figure 22-4. qspi delay register (qdlyr) table 22-4. qdlyr field descriptions field description 15 spe qspi enable. when set, the qspi initiates transfers in master mode by executing co mmands in the command ram. the qspi clears this bit automatically when a transfer comp letes. the user can also clear this bit to abort transfer unless qir[abrtl] is set. the recommended method for aborting transfers is to set qwr[halt]. 14?8 qcd qspi_clk delay. when the dsck bit in the command ram is set this field determines the length of the delay from assertion of the chip selects to valid qspi_clk transition. see section 22.4.3, ?transfer delays? for information on setting this bit field. 7?0 dtl delay after transfer. when the dt bit in the command ram is set this field determines t he length of delay after the serial transfer. qspi_clk qspi_dout qspi_din qspi_cs a b qmr[cpol] = 0 qmr[cpha] = 1 qcr[cont] = 0 chip selects are active low a=qdlyr[qcd] b=qdlyr[dtl] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 msb mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued serial peripheral interface (qspi) 22-6 freescale semiconductor 22.3.3 qspi wrap register (qwr) the qspi wrap register provides halt transfer control, wraparound settings, and queue pointer locations. 22.3.4 qspi interrupt register (qir) the qir contains qspi interr upt enables and status flags. ipsbar offset: 0x00_0348 (qwr) access: user read/write 1514131211109 876543210 r halt wren wrto csiv endqp cptqp newqp w reset0 0 0 00000 00000000 figure 22-5. qspi wrap register (qwr) table 22-5. qwr field descriptions field description 15 halt halt transfers. assertion of this bit causes the qspi to stop execution of commands afte r it has completed execution of the current command. 14 wren wraparound enable. enables wraparound mode. 0 execution stops after executing the command pointed to by qwr[endqp]. 1 after executing command pointed to by qwr[endqp], wrap back to entry zero, or the entry pointed to by qwr[newqp] and continue execution. 13 wrto wraparound location. determines where the qspi wraps to in wraparound mode. 0 wrap to ram entry zero. 1 wrap to ram entry pointed to by qwr[newqp]. 12 csiv qspi_cs inactive level. 0 qspi chip select outputs return to zero when not driv en from the value in the current command ram entry during a transfer (that is, inactive state is 0, chip selects are active high). 1 qspi chip select outputs return to one when not driven from the value in the current command ram entry during a transfer (that is, inactive state is 1, chip selects are active low). 11?8 endqp end of queue pointer. points to the ram entry that co ntains the last transfer description in the queue. 7?4 cptqp completed queue entry pointer. points to the ram entry t hat contains the last comma nd to have been completed. this field is read only. 3?0 newqp start of queue pointer. this 4-bit field points to the firs t entry in the ram to be executed on initiating a transfer. ipsbar offset: 0x00_034c (qir) access: user read/write 15 141312 11 109876543 210 r wcefb abrtb 0 abrtl wcefe abrte 0 spife 0 0 0 0 wcef abrt 0 spif w w1c w1c w1c reset0 000 0 00000000000 figure 22-6. qspi interrupt register (qir) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued serial peripheral interface (qspi) freescale semiconductor 22-7 22.3.5 qspi address register (qar) the qar is used to specify the location in the qspi ram that read and write ope rations affect. as shown in section 22.4.1, ?qspi ram? , the transmit ram is located at addresses 0x0 to 0xf, the receive ram is located at 0x10 to 0x1f, and th e command ram is located at 0x20 to 0x2f. (these addresses refer to the qspi ram space, not the device memory map.) note a read or write to the qspi ram causes qar to increment. however, the qar does not wrap after the last queue entry within each section of the ram. the application software must manage address range errors. table 22-6. qir field descriptions field description 15 wcefb write collision access error enable. a write collision occu rs during a data transfer when the ram entry containing the current command is written to by the cpu with the qdr. when this bit is asserted, the write access to qdr results in an access error. 14 abrtb abort access error enable. an abort occurs when qdlyr[spe] is cleared during a transfer. when set, an attempt to clear qdlyr[spe] during a transfer results in an access error. 13 reserved, must be cleared. 12 abrtl abort lock-out. when set, qdlyr[spe] ca nnot be cleared by writ ing to the qdlyr. qdlyr[ spe] is only cleared by the qspi when a transfer completes. 11 wcefe write collision (wcef) interrupt enable. 0 write collision interrupt disabled 1 write collision interrupt enabled 10 abrte abort (abrt) interrupt enable. 0 abort interrupt disabled 1 abort interrupt enabled 9 reserved, must be cleared. 8 spife qspi finished (spif) interrupt enable. 0 spif interrupt disabled 1 spif interrupt enabled 7?4 reserved, must be cleared. 3 wcef write collision error flag. indicates that an attempt has been made to write to the ram entry that is currently being executed. writing a 1 to this bit (w1c ) clears it and writing 0 has no effect. 2 abrt abort flag. indicates that qdlyr[spe] ha s been cleared by the user writing to the qdlyr rather than by completion of the command queue by the qspi. writing a 1 to this bit (w1c) clears it and writing 0 has no effect. 1 reserved, must be cleared. 0 spif qspi finished flag. asserted when the qspi has complet ed all the commands in the queue. set on completion of the command pointed to by qwr[endqp], and on comp letion of the current command after assertion of qwr[halt]. in wraparound mode, this bit is set every time the command pointed to by qwr[endqp] is completed. writing a 1 to this bit (w1c) clears it and writing 0 has no effect. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued serial peripheral interface (qspi) 22-8 freescale semiconductor 22.3.6 qspi data register (qdr) the qdr is used to access qspi ram indirectly. the cpu read s and writes all data from and to the qspi ram through this register. a write to qdr causes data to be written to the ram entry specified by qar[addr]. this also causes the value in qar to increment. corr espondingly, a read at qdr returns th e data in the ram at the address specified by qar[addr]. this also causes qar to increment. a read access requires a si ngle wait state. 22.3.7 command ram re gisters (qcr0?qcr15) the command ram is accesse d using the upper byte of the qdr; the qspi cannot modify information in command ram. there are 16 byt es in the command ram. each byte is divided into two fields. the chip select field enables external peripherals for tran sfer. the command field pr ovides transfer operations. ipsbar offset: 0x00_0350 (qar) access: user read/write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r0000000000 addr w reset0000000000000000 figure 22-7. qspi address register (qar) table 22-7. qar field descriptions field description 15?6 reserved, must be cleared. 5?0 addr address used to read/write the qspi ram. ranges are as follows: 0x00?0x0f transmit ram 0x10?0x1f receive ram 0x20?0x2f command ram 0x30?0x3f reserved ipsbar offset: 0x00_0354 (qdr) access: user read/write 1514131211109876543210 r data w reset0000000000000000 figure 22-8. qspi data register (qdr) table 22-8. qdr field descriptions field description 15?0 data a write to this field causes data to be written to the q spi ram entry specified by qar[ addr]. similarly, a read of this field returns the data in the qspi ram at t he address specified by qar[addr]. during command ram accesses (qar[addr] = 0x20?0x2f), only the most significant byte of this field is used. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued serial peripheral interface (qspi) freescale semiconductor 22-9 note the command ram is accessed only us ing the most significant byte of qdr and indirect addre ssing based on qar[addr]. 22.4 functional description the qspi uses a dedicated 80-byte block of static ram accessible to the module and cpu to perform queued operations. the ram is di vided into three segments: ? 16 command control bytes (command ram) ? 32 transmit data bytes (transmit data ram) address: qar[addr] access: cpu write-only 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r wcontbitsedtdsck qspi_cs 00000000 reset???????????????? figure 22-9. command ram registers (qcr0?qcr15) table 22-9. qcr0?qcr15 field descriptions field description 15 cont continuous. 0 chip selects return to inactive level defined by qwr[csiv] when a single word transfer is complete. 1 chip selects return to inactive level defined by qwr[csiv] only after the transfer of the queue entries (max of 16 words). note: to keep the chip selects asserted for transfers beyond 16 words, the qwr[csiv] bit must be set to control the level that the chip selects return to after the first transfer. 14 bitse bits per transfer enable. 0 eight bits 1 number of bits set in qmr[bits] 13 dt delay after transfer enable. 0 default reset value. 1 the qspi provides a variable delay at the end of serial transfer to facilitate interfacing with peripherals that have a latency requirement. the delay between transfers is determined by qdlyr[dtl]. 12 dsck chip select to qspi_clk delay enable. 0 chip select valid to qspi_clk transition is one-half qspi_clk period. 1 qdlyr[qcd] specifies the delay fr om qspi_cs valid to qspi_clk. 11?8 qspi_cs peripheral chip selects. used to select an external device for serial data transfer. more than one chip select may be active at once, and more than one device can be connect ed to each chip select. bits 11-8 map directly to the corresponding qspi_cs n pins. if more than four chip selects are needed, then an external demultiplexor can be used with the qspi_cs n pins. 0 enable chip select. 1 mask chip select. note: not all chip selects may be available on all device packages. see chapter 14, ?signal descriptions,? for details on which chip selects are pinned-out. 7?0 reserved, must be cleared. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued serial peripheral interface (qspi) 22-10 freescale semiconductor ? 32 receive data bytes (receive data ram) the ram is organized so that 1 byte of command cont rol data, 1 word of transmit data, and 1 word of receive data comprise 1 of the 16 queue entries (0x0?0xf). note throughout coldfire documentation, the te rm word is used to designate a 16-bit data unit. the only exceptions to th is appear in discussions of serial communication modules such as qspi that support variable-length data units. to simplify these discussions, the functional unit is referred to as a word regardless of length. the user initiates qspi operation by loading a queue of commands in command ram, writing transmit data into transmit ram, and then enabling the q spi data transfer. the qspi executes the queued commands and sets the completion flag in the qspi interrupt register (qir[spif]) to signal their completion. as another option, qir[spife] can be enabled to generate an interrupt. the qspi uses four queue pointers. th e user can access three of them thr ough fields in qspi wrap register (qwr): ? new queue pointer (qwr[newqp])?points to the first command in the queue ? internal queue pointer?points to th e command currently being executed ? completed queue pointer (qwr[cptqp]) ?points to the last command executed ? end queue pointer (qwr[endqp]) ?points to the final command in the queue the internal pointer is initialized to the same value as qwr[newqp]. during normal operation, the following sequence repeats: 1. the command pointed to by the internal pointer is executed. 2. the value in the internal point er is copied into qwr[cptqp]. 3. the internal pointer is incremented. execution continues at the internal pointer address unless the qwr[newqp] value is changed. after each command is executed, qwr[endqp] and qwr[cptqp] are compar ed. when a match occurs, qir[spif] is set and the qspi stops unless wrap around mode is enabled. setting qwr[wren] enables wraparound mode. qwr[newqp] is cleared at reset. when the qspi is enabled, execution begins at address 0x0 unless another value has been written into qwr[newqp]. qwr[endqp] is clea red at reset but is changed to show the last queue entry before the qspi is enabled. qwr[newqp] and qwr[endqp] can be written at any time. when the qwr[newqp] value changes, the internal pointer value also changes unless a transfer is in progress, in which case the tran sfer completes normally. leaving qwr[newqp] and qwr[endqp] set to 0x0 causes a single transf er to occur when the qspi is enabled. data is transferred relative to q spi_clk, which can be generated in any one of four combinations of phase and polarity using qmr[cpha,cpol]. data is transferred with the most significant bit (msb) first. the number of bits transferred defaults to 8, but can be set to any value between 8 and 16 by writing a value into the bitse field of the command ram (qcr[bitse]). mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued serial peripheral interface (qspi) freescale semiconductor 22-11 22.4.1 qspi ram the qspi contains an 80-byte block of static ram that can be accesse d by the user and the qspi. this ram does not appear in the device memory map, becau se it can only be accessed by the user indirectly through the qspi address register (qar) and the qspi data register (qdr). the ram is divided into three segments with 16 addresses each: ? receive data ram?the initial destination for all incoming data ? transmit data ram?a buffer for all out-bound data ? command ram?where commands are loaded the transmit data and command ram are user wr ite-only. the receive ram is user read-only. figure 22-10 shows the ram configuration. the ram conten ts are undefined immediately after a reset. the command and data ram in the qspi are indirectly accessible wi th qdr and qar as 48 separate locations that comprise 16 words of transmit data, 16 words of receive data, and 16 bytes of commands. a write to qdr causes data to be written to th e ram entry specified by qar[addr] and causes the value in qar to increment. corres pondingly, a read from qdr returns th e data in the ram at the address specified by qar[addr]. this also causes qar to increment. a read access requires a si ngle wait state. 22.4.1.1 receive ram data received by the qspi is stored in the receive ram segment locate d at 0x10 to 0x1f in the qspi ram space. read this segment to retrieve data from the qspi. data words with less than 16 bits are stored in relative address register function 0x00 qtr0 transmit ram 0x01 qtr1 ... ... 16 bits wide 0x0f qtr15 0x10 qrr0 receive ram 0x11 qrr1 ... ... 16 bits wide 0x1f qrr15 0x20 qcr0 command ram 0x21 qcr1 ... ... 8 bits wide 0x2f qcr15 figure 22-10. qspi ram model mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued serial peripheral interface (qspi) 22-12 freescale semiconductor the least significant bits of the ram. unused bits in a receive queue entry are set to zero upon completion of the individual queue entry. receive ram is not writeable. qwr[cptqp] shows which queue entrie s have been executed. the user can query this field to determine which locations in receiv e ram contain valid data. 22.4.1.2 transmit ram data to be transmitted by the qspi is stored in the transmit ram segm ent located at addresses 0x0 to 0xf. the user normally writes 1 word in to this segment for each queue co mmand to be executed. the user cannot read data in the transmit ram. outbound data must be written to transmit ram in a right-justified fo rmat. the unused bits are ignored. the qspi copies the data to its data serializer (shift register) for transmission. the data is transmitted most significant bit first and remains in transmit ram until overw ritten by the user. 22.4.1.3 command ram the cpu writes one byte of control information to this segment for ea ch qspi command to be executed. command ram, referred to as qcr0?15, is wr ite-only memory from a user?s perspective. command ram consists of 16 bytes, each divided into tw o fields. the peripheral chip select field controls the qspi_cs signal levels for the transfer. the command control field pr ovides transfer options. a maximum of 16 commands can be in the queue. queue execution proceeds from the address in qwr[newqp] through the address in qwr[endqp]. the qspi executes a queue of commands defined by th e control bits in each command ram entry that sequence the following actions: ? chip-select pins are activated. ? data is transmitted from the transmit ram and received into the receive ram. ? the synchronous transfer cl ock qspi_clk is generated. before any data transfers begin, control data must be written to the command ram, and any out-bound data must be written to the transmit ram. also, the queue pointers must be initialized to the first and last entries in the command queue. data transfer is synchronized with the internally generated qspi_clk, whos e phase and polarity are controlled by qmr[cpha] and qmr[cpol]. these c ontrol bits determine wh ich qspi_clk edge is used to drive outgoing data and to latch incoming data. 22.4.2 baud rate selection the maximum qspi clock frequency is one-fourth the clock frequency of the internal bus clock (f sys ). baud rate is selected by writing a value from 2?255 into qmr[baud]. the qspi uses a prescaler to derive the qspi_clk rate from the internal bus clock divided by two. table 22-10 shows the qspi_clk frequency as a function of inte rnal bus clock and baud rate. a baud rate value of zero turns off the qspi_clk. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued serial peripheral interface (qspi) freescale semiconductor 22-13 the desired qspi_clk baud rate is related to the internal bus clock and qmr[baud] by the following expression: eqn. 22-1 22.4.3 transfer delays the qspi supports programmable delays for the qspi_c s signals before and after a transfer. the time between qspi_cs assertion and the l eading qspi_clk edge, and the time between the end of one transfer and the beginning of the next, are both independently programmable. the chip select to clock delay enable bit in th e command ram, qcr[dsck], enables the programmable delay period from qspi_cs assertion until the leading edge of qspi_c lk. qdlyr[qcd] determines the period of delay before the leading edge of qspi_clk. the following expression determines the actual delay before the qspi_clk leading edge: eqn. 22-2 qdlyr[qcd] has a range of 1?127. when qdlyr[qcd] or qcr[dsck] e quals zero, the standard delay of one-half the qspi_clk period is used. the command ram delay after transmit enable bit, qcr[dt], enables the programmable delay period from the negation of the qspi_cs signa ls until the start of the next tran sfer. the delay after transfer can be used to provide a peripheral deselect interval. a delay can also be inserted between consecutive transfers to allow serial a/d conve rters to complete conversion. there are two transfer delay options: the user can choose to delay a standard period after serial transfer is complete or can specify a delay period. writing a value to qdlyr[dtl] specifies a delay period. qcr[dt] determines whether the standard delay period (dt = 0) or the specified delay period (dt = 1) is used. the following expression is used to calculate the delay when dt equals 1: eqn. 22-3 table 22-10. qspi_clk frequency as function of internal bus clock and baud rate internal bus clock = 80 mhz qmr [baud] qspi_clk 22 0 m h z 41 0 m h z 85 m h z 16 2.5 mhz 32 1.25 hz 255 156.9 khz qmr[baud] f sys 2 [desired qspi_clk baud rate] ----------------------------------------------------------------------------------- = qspi_cs-to-qspi_clk delay qdlyr[qcd] f sys ------------------------------------ - = delay after transfer 32 qdlyr[dtl] f sys ------------------------------------------------ (dt = 1) = mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued serial peripheral interface (qspi) 22-14 freescale semiconductor where qdlyr[dtl] has a range of 1?255. a zero value for dtl causes a delay-af ter-transfer value of 8192/f sys . standard delay period (dt = 0) is calculated by the following: eqn. 22-4 adequate delay between transfers must be specified for long data streams because the qspi module requires time to load a transmit ram entry for transfer. receiving devices need at least the standard delay between successive transfers. if the internal bus cl ock is operating at a slower rate, the delay between transfers must be in creased proportionately. 22.4.4 transfer length there are two transfer length options. the user can choos e a default value of 8 bits or a programmed value of 8 to 16 bits. the progr ammed value must be written into qm r[bits]. the comm and ram bits per transfer enable field, qcr[bitse], determines whethe r the default value (bitse = 0) or the bits[3?0] value (bitse = 1) is used. qmr[bi ts] indicates the required number of bits to be transferred, with the default value of 16 bits. 22.4.5 data transfer the transfer operation is initiated by setting qdlyr[spe]. shortly afte r qdlyr[spe] is set, the qspi executes the command at the command ram address poi nted to by qwr[newqp] . data at the pointer address in transmit ram is loaded into the data seri alizer and transmitted. data that is simultaneously received is stored at the poi nter address in receive ram. when the proper number of bits has been transferred, the qspi stores the working queue pointer value in qwr[cptqp], increments the worki ng queue pointer, and loads the next data for transfer from the transmit ram. the command pointed to by the incremented working queue pointer is executed next unless a new value has been written to qwr[newqp]. if a new queue pointer value is written while a transfer is in progress, the curr ent transfer is completed normally. when the cont bit in the command ram is set, the qspi_cs n signals are asserted between transfers. when cont is cleared, qspi_cs n are negated between transfers. the qspi_cs n signals are not high impedance. when the qspi reaches the end of th e queue, it asserts the sp if flag, qir[spif]. if qi r[spife] is set, an interrupt request is generated when qir[spif] is asserte d. then the qspi clears qdlyr[spe] and stops, unless wraparound mode is enabled. wraparound mode is enabled by setting qwr[wren]. th e queue can wrap to pointer address 0x0, or to the address specified by qwr[newqp], depending on the state of qwr[wrto]. in wraparound mode, the qspi cycles through the que ue continuously, even while requesting interrupt service. qdlyr[spe] is not cleared when the last command in the queue is executed. new receive data overwrites previously received data in the receive ram. each time the end of the queue is reached, standard delay after transfer 17 f sys ------- (dt = 0) = mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued serial peripheral interface (qspi) freescale semiconductor 22-15 qir[spife] is set. qir[spif] is not automatically rese t. if interrupt driven qspi service is used, the service routine must clear qir[spif] to abort the current reques t. additional interr upt requests during servicing can be prevente d by clearing qir[spife]. there are two recommended methods of exiting wraparound mode: clearing qwr[wren] or setting qwr[halt]. exiting wraparound mode by clearing qdlyr[spe] is not recommended because this may abort a serial transfer in progress. the qspi sets spif, clears qdlyr[spe], a nd stops the first time it reaches the end of the queue after qwr[wren] is cleared. after qwr[ha lt] is set, the qspi finishes the current transfer, then stops executing commands. after the qspi stops, qdlyr[spe] can be cleared. 22.5 initialization/application information the following steps are necessary to set up the qspi 12-bit data transf ers and a qspi_clk of 5 mhz. the qspi ram is set up for a queue of 16 transfers. al l four qspi_cs signals ar e used in this example. 1. write the qmr with 0xb308 to set up 12-bit data words with the data shifted on the falling clock edge, and a qspi_clk frequency of 5 mhz (assuming a 80-mhz internal bus clock). 2. write qdlyr with the desired delays. 3. write qir with 0xd00f to enable write collisi on, abort bus errors, a nd clear any interrupts. 4. write qar with 0x0020 to select the first command ram entry. 5. write qdr with 0x7e00, 0x7e00, 0x7e 00, 0x7e00, 0x7d00, 0x7d00, 0x7d00, 0x7d00, 0x7b00, 0x7b00, 0x7b00, 0x7b00, 0x7700, 0x7700, 0x7700, and 0x7700 to set up four transfers for each chip select. the chip selects are active low in this example. 6. write qar with 0x0000 to select the first transmit ram entry. 7. write qdr with sixteen 12-bit words of data. 8. write qwr with 0x0f00 to set up a queue beginning at entry 0 and ending at entry 15. 9. set qdlyr[spe] to enable the transfers. 10. wait until the transfers are complete. qir[spif] is set when the transfers are complete. 11. write qar with 0x0010 to select the first receive ram entry. 12. read qdr to get the received data for each transfer. 13. repeat steps 5 through 13 to do another transfer. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued serial peripheral interface (qspi) 22-16 freescale semiconductor mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor 23-1 chapter 23 uart modules 23.1 introduction this chapter describes the use of the three univers al asynchronous receiver/t ransmitters (uarts) and includes programming examples. note the designation n appears throughout this section to refer to registers or signals associated with one of the three identical uart modules: uart0, uart1, or uart2. 23.1.1 overview the internal bus clock can clock each of the three independent uarts, eliminating the need for an external uart clock. as figure 23-1 shows, each uart module interfaces directly to the cp u and consists of: ? serial communication channel ? programmable clock generation ? interrupt control logic and dma request logic ? internal channel control logic figure 23-1. uart block diagram serial interrupt control logic internal channel control logic programmable clock communications channel generation uart internal bus clock (f sys ) or external clock (dtin n ) dma request logic transmit dma request receive dma request interrupt request (to interrupt controller) (to dma controller) external signals uart registers ucts n urts n urxd n utxd n internal bus mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 uart modules 23-2 freescale semiconductor note the dtin n pin can clock uart n . however, if the timers are operating and the uart uses dtin n as a clock source, input ca pture mode is not available for that timer. the serial communication channel provides a full-duplex asynchronous/synchronous receiver and transmitter deriving an operating frequency from the internal bus cl ock or an external clock using the timer pin. the transmitter converts parallel data from the cpu to a serial bit stream, inserting appropriate start, stop, and parity bits. it outputs th e resulting stream on the transmit ter serial data output (utxd n ). see section 23.4.2.1, ?transmitter .? the receiver converts serial data from the receiver serial data input (urxd n) to parallel format, checks for a start, stop, and parity bits, or break conditions, and transfers th e assembled character onto the bus during read operations. the receiver ma y be polled, interrupt driven, or use dma requests for servicing. see section 23.4.2.2, ?receiver .? note the gpio module must be configured to enable the peripheral function of the appropriate pins (refer to chapter 26, ?general purpose i/o module? ) prior to configuring the uart module. 23.1.2 features the device contains three i ndependent uart modules with: ? each clocked by external clock or internal bus cl ock (eliminates need for an external uart clock) ? full-duplex asynchronous/synchronous receiver/transmitter ? quadruple-buffered receiver ? double-buffered transmitter ? independently programmable receiver and transmitter clock sources ? programmable data format: ? 5?8 data bits plus parity ? odd, even, no parity, or force parity ? one, one-and-a-half, or two stop bits ? each serial channel programmable to normal (full-duplex), automatic echo, local loopback, or remote loopback mode ? automatic wake-up mode for multidrop applications ? four maskable interrupt conditions ? all three uarts have dma request capability ? parity, framing, and overrun error detection ? false-start bit detection ? line-break detection and generation ? detection of breaks originating in the middle of a character mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 uart modules freescale semiconductor 23-3 ? start/end break interrupt/status 23.2 external signal description table 23-1 briefly describes th e uart module signals. figure 23-2 shows a signal configuration for a uart/rs-232 interface. figure 23-2. uart/rs-232 interface 23.3 memory map/register definition this section contains a detailed de scription of each register and its specific f unction. flowcharts in section 23.5, ?initialization/ application information ,? describe basic uart module programming. writing control bytes into the appropriate regi sters controls the operation of the uart module. note uart registers are accessible only as bytes. note interrupt can mean an interrupt request asserted to the cpu or a dma request. table 23-1. uart module external signals signal description utxd n transmitter serial data output. utxd n is held high (mark condition) when the transmitter is disabled, idle, or operating in the local loopback mode. data is shifted out on utxd n on the falling edge of the clock source, with the least significant bit (lsb) sent first. urxd n receiver serial data input. data received on urxd n is sampled on the rising edge of the clock source, with the lsb received first. ucts n clear-to- send. this input can generate an interrupt on a change of state. urts n request-to-send. this output can be programmed to be negat ed or asserted automatically by the receiver or the transmitter. when connected to a transmitter?s ucts n , urts n can control serial data flow. do2 di1 di2 do1 rs-232 transceiver uart urxdn utxd n ucts n urts n mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 uart modules 23-4 freescale semiconductor table 23-2. uart module memory map register width (bit) access reset value section/page uart0 uart1 uart2 0x00 0x0 0x0 uart mode registers 1 (umr1 n ), (umr2 n ) 1 umr1n , umr2 n , and ucsr n must be changed only after the receiver/transmitter is issued a software reset command. if operation is not disabled, undesirable results may occur. 8 r/w 0x00 23.3.1/23-5 23.3.2/23-6 0x04 0x4 0x4 uart status register (usr n )8 r 0 x 0 0 23.3.3/23-8 uart clock select register 1 (ucsr n ) 8 w see section 23.3.4/23-9 0x08 0x8 0x8 uart command registers (ucr n )8 w 0 x 0 0 23.3.5/23-9 0x0c 0xc 0xc uart receive buffers (urb n ) 8 r 0xff 23.3.6/23-11 uart transmit buffers (utb n )8 w 0 x 0 0 23.3.7/23-12 0x10 0x0 0x0 uart input port change register (uipcr n ) 8 r see section 23.3.8/23-12 uart auxiliary control register (uacr n )8 w 0 x 0 0 23.3.9/23-13 0x14 0x4 0x4 uart interrupt status register (uisr n )8 r 0 x 0 0 23.3.10/23-13 uart interrupt mask register (uimr n )8 w 0 x 0 0 0x18 0x8 0x8 uart baud rate generator register (ubg1 n )8 w 2 2 reading this register results in undesired effects and possible incorrect transmission or reception of characters. register contents may also be changed. 0x00 23.3.11/23-15 0x1c 0xc 0xc uart baud rate generator register (ubg2 n )8 w 2 0x00 23.3.11/23-15 0x34 0x4 0x4 uart input port register (uip n ) 8 r 0xff 23.3.12/23-15 0x38 0x8 0x8 uart output port bit set command register (uop1 n )8w 2 0x00 23.3.13/23-16 0x3c 0xc 0xc uart output port bit rese t command register (uop0 n )8w 2 0x00 23.3.13/23-16 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 uart modules freescale semiconductor 23-5 23.3.1 uart mode registers 1 (umr1 n ) the umr1n registers control uart module configuration. umr1 n can be read or written when the mode register pointer points to it, at reset or after a reset mode register pointer command using ucr n [misc]. after umr1 n is read or written, the pointer points to umr2 n. ipsbar offset: 0x00_0200 (umr10) 0x00_0240 (umr11) 0x00_0280 (umr12) access: user read/write 1 76543210 r rxrts rxirq/ ffull err pm pt b/c w reset:00000000 1 after umr1 n is read or written, the pointer points to umr2 n figure 23-3. uart mode registers 1 (umr1 n ) table 23-3. umr1 n field descriptions field description 7 rxrts receiver request-to-send. allows the urts n output to control the ucts n input of the transmitting device to prevent receiver overrun. if the receiver and tr ansmitter are incorrectly programmed for urts n control, urts n control is disabled for both. transmitter rts control is configured in umr2 n [txrts]. 0 the receiver has no effect on urts n . 1 when a valid start bit is received, urts n is negated if the uart's fifo is full. urts n is reasserted when the fifo has an empty position available. 6 rxirq/ ffull receiver interrupt select. 0 rxrdy is the source generati ng interrupt or dma requests. 1 ffull is the source generating interrupt or dma requests. 5 err error mode. configures t he fifo status bits, usr n [rb,fe,pe]. 0 character mode. the usr n values reflect the status of the character at the top of the fifo. err must be 0 for correct a/d flag information when in multidrop mode. 1 block mode. the usr n values are the logical or of the status for a ll characters reaching the top of the fifo since the last reset error status command for the uart was issued. see section 23.3.5, ?uart command registers (ucrn) .? 4?3 pm parity mode. selects the parity or multidrop mode for the uart. the parity bit is added to the transmitted character, and the receiver performs a parity check on incoming dat a. the value of pm affects pt, as shown below. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 uart modules 23-6 freescale semiconductor 23.3.2 uart mode register 2 (umr2 n ) the umr2n registers control uart module configuration. umr2 n can be read or written when the mode register pointer points to it, wh ich occurs after any access to umr1 n. umr2 n accesses do not update the pointer. 2 pt parity type. pm and pt together select parity type (pm = 0x) or determine whether a data or address character is transmitted (pm = 11). 1?0 b/c bits per character. selects the number of data bits per c haracter to be sent. the values shown do not include start, parity, or stop bits. 00 5 bits 01 6 bits 10 7 bits 11 8 bits ipsbar offset: 0x00_0200 (umr20) 0x00_0240 (umr21) 0x00_0280 (umr22) access: user read/write 1 76543210 r cm txrts txcts sb w reset:00000000 1 after umr1 n is read or written, the pointer points to umr2 n figure 23-4. uart mode registers 2 (umr2 n ) table 23-3. umr1 n field descriptions (continued) field description pm parity mode parity type (pt= 0) parity type (pt= 1) 00 with parity even parity odd parity 01 force parity low parity high parity 10 no parity n/a 11 multidrop mode data character address character mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 uart modules freescale semiconductor 23-7 table 23-4. umr2 n field descriptions field description 7?6 cm channel mode. selects a channel mode. section 23.4.3, ?looping modes ,? describes individual modes. 00 normal 01 automatic echo 10 local loopback 11 remote loopback 5 txrts transmitter ready-to-send. controls negation of urts n to automatically terminate a message transmission. attempting to program a receiver and transmitter in the same uart for urts n control is not permitted and disables urts n control for both. 0 the transmitter has no effect on urts n . 1 in applications where the transmitter is disabled after tran smission completes, setting this bit automatically clears uop[rts] one bit time after any charac ters in the transmitter shift and hol ding registers are completely sent, including the programmed number of stop bits. 4 txcts transmitter clear-to-send. if txcts and txrts are set, txcts controls the operation of the transmitter. 0 ucts n has no effect on the transmitter. 1 enables clear-to-send operation. th e transmitter checks the state of ucts n each time it is ready to send a character. if ucts n is asserted, the character is sent; if it is deasserted, the signal utxd n remains in the high state and transmission is delayed until ucts n is asserted. changes in ucts n as a character is being sent do not affect its transmission. 3?0 sb stop-bit length control. selects length of stop bit appended to the transmitted character. stop-bit lengths of 9/16 to 2 bits are programmable for 6?8 bit characters. lengths of 1- 1/16 to 2 bits are programmable for 5-bit characters. in all cases, the receiver checks only for a high condition at the center of the first stop-bit position, one bit time after the last data bit or after the parity bit, if parity is enabled. if an external 1x clock is used for the transmitter, clearing bit 3 selects one stop bit and setting bit 3 selects two stop bits for transmission. sb 5 bits 6?8 bits sb 5?8 bits 0000 1.063 0.563 1000 1.563 0001 1.125 0.625 1001 1.625 0010 1.188 0.688 1010 1.688 0011 1.250 0.750 1011 1.750 0100 1.313 0.813 1100 1.813 0101 1.375 0.875 1101 1.875 0110 1.438 0.938 1110 1.938 0111 1.500 1.000 1111 2.000 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 uart modules 23-8 freescale semiconductor 23.3.3 uart status registers (usr n ) the usr n registers show the status of the tran smitter, the receiver, and the fifo. ipsbar offset: 0x00_0204 (usr0) 0x00_0244 (usr1) 0x00_0284 (usr2) access: user read-only 76543210 r rb fe pe oe txemp txrdy ffull rxrdy w r e s e t :00000000 figure 23-5. uart status registers (usr n ) table 23-5. usr n field descriptions field description 7 rb received break. the received break circuit detects breaks originating in the middle of a received character. however, a break in the middle of a character must persist until the end of the next detected character time. 0 no break was received. 1 an all-zero character of the programmed length was received without a stop bit. only a single fifo position is occupied when a break is received. further entries to the fifo are inhibited until urxd n returns to the high state for at least one-half bit time, which equals two successive edges of the uart clock. rb is valid only when rxrdy is set. 6 fe framing error. 0 no framing error occurred. 1 no stop bit was detected when the corresponding data c haracter in the fifo was re ceived. the stop-bit check occurs in the middle of the first stop-bit pos ition. fe is valid only when rxrdy is set. 5 pe parity error. valid only if rxrdy is set. 0 no parity error occurred. 1 if umr1 n [pm] equals 0 x (with parity or force parity), the corresponding character in the fifo was received with incorrect parity. if umr1 n [pm] equals 11 (multidrop), pe stores the rece ived address or data (a/d) bit. pe is valid only when rxrdy is set. 4 oe overrun error. indicates whether an overrun occurs. 0 no overrun occurred. 1 one or more characters in the received data stream have been lost. oe is set upon receipt of a new character when the fifo is full and a character is already in the sh ift register waiting for an empty fifo position. when this occurs, the character in the receiver shift register and its break detect, framing error status, and parity error, if any, are lost. the reset error status command in ucr n clears oe. 3 temp transmitter empty. 0 the transmit buffer is not empty. a character is shifte d out, or the transmitter is disabled. the transmitter is enabled/disabled by programming ucr n [tc]. 1 the transmitter has underrun (the transmitter holding regi ster and transmitter shift registers are empty). this bit is set after transmission of the last stop bit of a charac ter if there are no characters in the transmitter holding register awaiting transmission. 2 txrdy transmitter ready. 0 the cpu loaded the transmitter holding register, or the transmitter is disabled. 1 the transmitter holding register is em pty and ready for a character. txrdy is set when a character is sent to the transmitter shift register or when the transmitter is firs t enabled. if the transmitter is disabled, characters loaded into the transmitter holding register are not sent. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 uart modules freescale semiconductor 23-9 23.3.4 uart clock select registers (ucsr n ) the ucsrs select an external clock on the dtin input (divided by 1 or 16) or a prescaled internal bus clock as the clocking source for th e transmitter and receiver. see section 23.4.1, ?transmitter/receiver clock source .? the transmitter and receiver can use different clock sources. to use the internal bus clock for both, set ucsr n to 0xdd. 23.3.5 uart command registers (ucr n ) the ucrs supply commands to the uart. only multiple commands that do not c onflict can be specified in a single write to a ucr n. for example, reset transmitter and enable transmitter cannot be specified in one command. 1 ffull fifo full. 0 the fifo is not full but may hold up to two unread characters. 1 a character was received and the receiver fifo is now full . any characters received when the fifo is full are lost. 0 rxrdy receiver ready. 0 the cpu has read the receive buffer and no characters remain in the fifo after this read. 1 one or more characters were received and are waiting in the receive buffer fifo. ipsbar offset: 0x00_0204 (ucsr0) 0x00_0244 (ucsr1) 0x00_0284 (ucsr2) access: user write-only 76543210 r w rcs tcs reset: see note see note note: the rcs and tcs reset values are set so the receiver and transmiter use the prescaled internal bus clock as their clock source. figure 23-6. uart clock select registers (ucsr n ) table 23-6. ucsr n field descriptions field description 7?4 rcs receiver clock select. selects t he clock source for the receiver. 1101 prescaled internal bus clock (f sys ) 1110 dtin n divided by 16 1111 dtin n 3?0 tcs transmitter clock select. selects the clock source for the transmitter. 1101 prescaled internal bus clock (f sys ) 1110 dtin n divided by 16 1111 dtin n table 23-5. usr n field descriptions (continued) field description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 uart modules 23-10 freescale semiconductor table 23-7 describes ucr n fields and commands. examples in section 23.4.2, ?transmitter and receiver operating modes ,? show how these commands are used. ipsbar offset: 0x00_0208 (ucr0) 0x00_0248 (ucr1) 0x00_0288 (ucr2) access: user write-only 76543210 r w 0 misc tc rc r e s e t :00000000 figure 23-7. uart command registers (ucr n ) table 23-7. ucr n field descriptions field description 7 reserved, must be cleared. 6?4 misc misc field (this field selects a single command) command description 000 no command ? 001 reset mode register pointer causes the mode register pointer to point to umr1 n . 010 reset receiver immediately disables the receiver, clears usr n [ffull,rxrdy], and reinitializes the receiver fifo pointer. no other registers are altered. because it places the receiver in a known state, use this command instead of receiver disable when reconfiguring the receiver. 011 reset transmitter immediately disables the transmitter and clears usr n [txemp,txrdy]. no other registers are altered. because it places t he transmitter in a known state, use this command instead of transmitter disable when reconfiguring the transmitter. 100 reset error status clears usr n [rb,fe,pe,oe]. also used in block mode to clear all error bits after a data block is received. 101 reset break ? change interrupt clears the delta break bit, uisr n [db]. 110 start break forces utxd n low. if the transmitter is empty, break may be delayed up to one bit time. if the transmitter is active, br eak starts when character transmission completes. break is delayed until any charac ter in the transmitte r shift register is sent. any character in the transmitter holding register is sent after the break. transmitter must be enabled for the co mmand to be accepted. this command ignores the state of ucts n . 111 stop break causes utxd n to go high (mark) within two bit times. any characters in the transmit buffer are sent. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 uart modules freescale semiconductor 23-11 23.3.6 uart receive buffers (urb n ) the receive buffers contain one serial shift register and three receiver holding registers, which act as a fifo. urxd n is connected to the serial shift register. the cpu reads from the top of the fifo while the receiver shifts and updates from the bottom when the sh ift register is full (see figure 23-18 ). rb contains the character in the receiver. 3?2 tc transmit command field. selects a single transmit command. 1?0 rc receive command field. selects a single receive command. table 23-7. ucr n field descriptions (continued) field description command description 00 no action taken causes the transmitter to stay in its current mode: if the transmitter is enabled, it remains enabled; if the transmitter is disabled, it remains disabled. 01 transmitter enable enables operation of the uart?s transmitter. usr n [txemp,txrdy] are set. if the transmitter is already enabled, this command has no effect. 10 transmitter disable terminates transmitter operation and clears usr n [txemp,txrdy]. if a character is being sent when the transmitter is disabled, transmission completes before the transmitter becomes inactive. if the trans mitter is already disabled, the command has no effect. 11 ? reserved, do not use. command description 00 no action taken causes the receiver to stay in its curre nt mode. if the receiver is enabled, it remains enabled; if disabled, it remains disabled. 01 receiver enable if the uart module is not in multidrop mode (umr1 n [pm] 11), receiver enable enables the uart's receiver and forces it into search-for-start-bit state. if the receiver is already enabled, this command has no effect. 10 receiver disable disables the receiver immediately. any character being received is lost. the command does not affect receiver status bits or other control registers. if the uart module is programmed for local loopback or multidrop mode, the receiver operates even though this command is selected. if the receiver is already disabled, the command has no effect. 11 ? reserved, do not use. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 uart modules 23-12 freescale semiconductor 23.3.7 uart transmit buffers (utb n ) the transmit buffers consist of th e transmitter holding register and th e transmitter shift register. the holding register accepts characters fr om the bus master if uart?s usr n [txrdy] is set. a write to the transmit buffer clears usr n[txrdy], inhibiting any more characters until the shift register can accept more data. when the shift register is empty, it checks if the holding regist er has a valid char acter to be sent (txrdy = 0). if there is a va lid character, the shift register loads it and sets usr n [txrdy] again. writes to the transmit buffer when the uart?s txrdy is clear ed and the transmitter is disabled have no effect on the transmit buffer. figure 23-9 shows utb n . tb contains the character in the transmit buffer. 23.3.8 uart input port change registers (uipcr n ) the uipcrs hold the current state and the change-of-state for ucts n . ipsbar offset: 0x00_020c (urb0) 0x00_024c (urb1) 0x00_028c (urb2) access: user read-only 76543210 r rb w r e s e t :11111111 figure 23-8. uart receive buffer (urb n ) ipsbar offset: 0x00_020c (utb0) 0x00_024c (utb1) 0x00_028c (utb2) access: user write-only 76543210 r w tb r e s e t :00000000 figure 23-9. uart transmit buffer (utb n ) ipsbar offset: 0x00_0210 (uipcr0) 0x00_0250 (uipcr1) 0x00_0290 (uipcr2) access: user read-only 76543210 r 0 0 0 cos 1 1 1 cts w r e s e t :0000111u c t s n figure 23-10. uart input port changed registers (uipcr n ) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 uart modules freescale semiconductor 23-13 23.3.9 uart auxiliary control register (uacr n ) the uacrs control the input enable. 23.3.10 uart interrupt status/mask registers (uisr n /uimr n ) the uisrs provide status for all potential interrupt sources. uisr n contents are masked by uimr n. if corresponding uisr n and uimr n bits are set, internal interrupt output is asserted. if a uimr n bit is cleared, state of the corresponding uisr n bit has no effect on the output. the uisr n and uimr n registers share the same space in memory . reading this regist er provides the user with interrupt status, while writing controls the mask bits. table 23-8. uipcr n field descriptions field description 7?5 reserved 4 cos change of state (high-to-low or low-to-high transition). 0 no change-of-state since the cpu last read uipcr n . reading uipcr n clears uisr n [cos]. 1 a change-of-state longer than 25?50 s occurred on the ucts n input. uacr n can be programmed to generate an interrupt to the cpu when a change of state is detected. 3?1 reserved 0 cts current state of clear-to-send. starting two serial cloc k periods after reset, cts reflects the state of ucts n . if ucts n is detected asserted at that time, cos is set, which initiates an interrupt if uacr n [iec] is enabled. 0 the current state of the ucts n input is asserted. 1 the current state of the ucts n input is deasserted. ipsbar offset: 0x00_0210 (uacr0) 0x00_0250 (uacr1) 0x00_0290 (uacr2) access: user write-only 76543210 r w 0 0 0 0 0 0 0 iec r e s e t :00000000 figure 23-11. uart auxiliary control registers (uacr n ) table 23-9. uacr n field descriptions field description 7?1 reserved, must be cleared. 0 iec input enable control. 0 setting the corresponding uipcr n bit has no effect on uisr n [cos]. 1uisr n [cos] is set and an interrupt is generated when the uipcr n [cos] is set by an external transition on the ucts n input (if uimr n [cos] = 1). mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 uart modules 23-14 freescale semiconductor note true status is pr ovided in the uisr n regardless of uimr n settings. uisr n is cleared when the uart module is reset. ipsbar offset: 0x00_0214 (uisr0) 0x00_0254 (uisr1) 0x00_0294 (uisr2) access: user read/write 76543210 r (uisr n ) cos 0 0 0 0 db ffull/ rxrdy txrdy w (uimr n ) cos 0 0 0 0 db ffull/ rxrdy txrdy reset:00000000 figure 23-12. uart interrupt status/mask registers (uisr n /uimr n ) table 23-10. uisr n /uimr n field descriptions field description 7 cos change-of-state. 0uipcr n [cos] is not selected. 1 change-of-state occurred on ucts n and was programmed in uacr n [iec] to cause an interrupt. 6?3 reserved, must be cleared. 2 db delta break. 0 no new break-change condition to report. section 23.3.5, ?uart command registers (ucrn) ,? describes the reset break - change interrupt command. 1 the receiver detected the beginning or end of a received break. 1 ffull/ rxrdy status of fifo or receiver, depending on umr1[ffull/rxrdy] bit. duplicate of usr n [fifo] and usr n [rxrdy] 0 txrdy transmitter ready. this bit is the duplication of usr n [txrdy]. 0 the transmitter holding register was loaded by the cpu or the transmitter is disabled. characters loaded into the transmitter holding register when txrdy is cleared are not sent. 1 the transmitter holding register is empt y and ready to be loaded with a character. uimr n [ffull/rxrdy] uisr n [ffull/rxrdy] umr1n [ffull/rxrdy] 0 (rxrdy) 1 (fifo) 0 0 receiver not ready fifo not full 1 0 receiver not ready fifo not full 0 1 receiver is ready, do not interrupt fifo is full, do not interrupt 1 1 receiver is ready, interrupt fifo is full, interrupt mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 uart modules freescale semiconductor 23-15 23.3.11 uart baud rate ge nerator registers (ubg1 n /ubg2 n ) the ubg1 n registers hold the msb, and the ubg2 n registers hold the lsb of the preload value. ubg1 n and ubg2 n concatenate to provide a divider to the inte rnal bus clock for tran smitter/receiver operation, as described in section 23.4.1.2.1, ?internal bus clock baud rates .? note the minimum value loaded on the concatenation of ubg1 n with ubg2 n is 0x0002. the ubg2 n reset value of 0x00 is invali d and must be written to before the uart transmitter or receiver are enabled. ubg1 n and ubg2n are write-only and cannot be read by the cpu. 23.3.12 uart input port register (uip n ) the uip n registers show the current state of the ucts n input. ipsbar offset: 0x00_0218 (ubg10) 0x00_0258 (ubg11) 0x00_0298 (ubg12) access: user write-only 76543210 r w divider msb r e s e t :00000000 figure 23-13. uart baud rate generator registers (ubg1 n ) ipsbar offset: 0x00_021c (ubg20) 0x00_025c (ubg21) 0x00_029c (ubg22) access: user write-only 76543210 r w divider lsb reset:00000000 figure 23-14. uart baud rate generator registers (ubg2 n ) ipsbar offset: 0x00_0234 (uip0) 0x00_0274 (uip1) 0x00_02b4 (uip2) access: user read-only 76543210 r 1 1 1 1 1 1 1 cts w r e s e t :11111111 figure 23-15. uart input port registers (uip n ) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 uart modules 23-16 freescale semiconductor 23.3.13 uart output port command registers (uop1 n /uop0 n ) the urts n output can be asserted by writing a 1 to uop1 n [rts] and negated by writing a 1 to uop0 n [rts]. 23.4 functional description this section describes operation of the clock source generator, transmitter, and receiver. 23.4.1 transmitter/receiver clock source the internal bus clock serves as the basic timing reference for the clock source generator logic, which consists of a clock generator and a programmable 16-bit divider dedicated to each uart. the 16-bit divider is used to produce standard uart baud rates. table 23-11. uip n field descriptions field description 7?1 reserved 0 cts current state of cl ear-to-send. the ucts n value is latched and reflects t he state of the input pin when uip n is read. note: this bit has the same function and value as uipcr n [cts]. 0 the current state of the ucts n input is logic 0. 1 the current state of the ucts n input is logic 1. ipsbar offset: 0x00_0238 (uop10) 0x00_023c (uop00) 0x00_0278 (uop11) 0x00_027c (uop01) 0x00_02b8 (uop12) 0x00_02bc (uop02) access: user write-only 76543210 r w 0 0 0 0 0 0 0 rts r e s e t :00000000 figure 23-16. uart output port command registers (uop1 n/uop0 n ) table 23-12. uop1 n /uop0 n field descriptions field description 7?1 reserved, must be cleared. 0 rts output port output. controls asse rtion (uop1)/negation (uop0) of urts n output. 0 not affected. 1 asserts urts n in uop1. negates urts n in uop0. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 uart modules freescale semiconductor 23-17 23.4.1.1 programmable divider as figure 23-17 shows, the uart n transmitter and receiver can us e the following clock sources: ? an external clock signal on the dtin n pin. when not divided, dtin n provides a synchronous clock; when divided by 16, it is asynchronous. ? the internal bus clock supplie s an asynchronous clock source divi ded by 32 and then divided by the 16-bit value programmed in ubg1n and ubg2 n. see section 23.3.11, ?uart baud rate generator registers (ubg1n/ubg2n) .? the choice of dtin or internal bus clock is programmed in the ucsr. figure 23-17. clocking source diagram note if dtin n is a clocking source for the ti mer or uart, that timer module cannot use dtin n for timer input capture. 23.4.1.2 calculati ng baud rates the following sections describe how to calculate baud rates. 23.4.1.2.1 internal bus clock baud rates when the internal bus clock is the uart clocking source, it goes through a di vide-by-32 prescaler and then passes through the 16-bit divider of the concatenated ubg1 n and ubg2n registers. the baud-rate calculation is: eqn. 23-1 uart on-chip tin 1 16 16-bit divider 32 tin clocking sources programmed in ucsr timer module internal tx rx rx buffer tx buffer f sys bus clock urxdn utxd n dtin n dtout n baudrate f sys 32 x divider [] ------------------------------------ = mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 uart modules 23-18 freescale semiconductor using a 80-mhz internal bus clock and letting baud rate equal 9600, then eqn. 23-2 therefore, ubg1 n equals 0x01 and ubg2 n equals 0x04. 23.4.1.2.2 external clock an external source clock (dtin n) passes through a divide-by- 1 or 16 prescaler. if f extc is the external clock frequency, baud rate can be described with this equation: eqn. 23-3 23.4.2 transmitter and re ceiver operating modes figure 23-18 is a functional block diagra m of the transmitter and receiver showing the command and operating registers, which are describe d generally in the following sections . for detailed descriptions, refer to section 23.3, ?memory map/register definition .? figure 23-18. transmitter and receiver functional diagram 23.4.2.1 transmitter the transmitter is enabled thr ough the uart command register (ucr n). when it is ready to accept a character, uart sets usr n [txrdy]. the transmitter converts parallel data from the cpu to a serial bit stream on utxd n . it automatically sends a st art bit followed by the program med number of data bits, an divider 80 mhz 32 x 9600 [] ------------------------------ - 260 decimal () 0x 0104 hex adecimal () == = baudrate f extc (16 or 1) -------------------- - = receiver shift register uart command register (ucr n )w uart status register (usr n ) r transmitter shift register uart mode register 1 (umr1 n )r/w uart mode register 2 (umr2 n )r/w transmitter holding register w receiver holding register 3 receiver holding register 2 receiver holding register 1 r uart receive uart buffer (urb n ) (4 registers) uart n external interface transmit buffer (utb n ) (2 registers) fifo urxdn utxd n mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 uart modules freescale semiconductor 23-19 optional parity bit, and the programmed number of st op bits. the lsb is sent first. data is shifted from the transmitter output on the falling edge of the clock source. after the stop bits are sent, if no new character is in the transmitter holding register, the utxd n output remains high (mark condition) and the transmitter empty bit (usr n [txemp]) is set. transmission resumes and txemp is cleared when the cpu load s a new character into the uart transmit buffer (utb n). if the transmitter r eceives a disable command, it continues until any charact er in the transmitter shift register is completely sent. if the transmitter is reset through a software command, opera tion stops immediately (see section 23.3.5, ?uart command registers (ucrn) ?). the transmitter is reenabled through the ucr n to resume operation after a disabl e or software reset. if the clear-to-send operation is enabled, ucts n must be asserted for the character to be transmitted. if ucts n is negated in the middle of a transmission, the character in the shift register is sent and utxd n remains in mark state until ucts n is reasserted. if transm itter is forced to send a continuous low condition by issuing a send break command, transmitter i gnores the state of ucts n . if the transmitter is programme d to automatically negate urts n when a message transmission completes, urts n must be asserted manually before a message is se nt. in applications in which the transmitter is disabled after transmissi on is complete and urts n is appropriately programmed, urts n is negated one bit time after the character in the sh ift register is completely transmit ted. the transmitter must be manually reenabled by reasserting urts n before the next message is sent. figure 23-19 shows the functional timing information for the transmitter. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 uart modules 23-20 freescale semiconductor figure 23-19. transmitter timing diagram 23.4.2.2 receiver the receiver is enabled through its ucr n, as described in section 23.3.5, ?uart command registers (ucrn) .? when the receiver detects a hi gh-to-low (mark-to-space) tran sition of the start bit on urxd n, the state of urxd n is sampled eight times on the e dge of the bit time clock starting one-half clock afte r the transition (asynchronous operation) or at the next rising edge of the bit time clock (synchronous operation). if urxd n is sampled high, start bit is invalid and the search for the valid start bit begins again. if urxd n remains low, a valid start bit is assumed. th e receiver continues sampli ng the input at one-bit time intervals at the theoretical center of the bit until the proper number of data bi ts and parity, if any, is assembled and one stop bit is detected. data on the urxd n input is sampled on the rising edge of the programmed clock source. the lsb is received first. the data then transfers to a receiver holding register and usr n[rxrdy] is set. if the character is less than 8 bits, the most significant unused bits in the receiver holding regi ster are cleared. after the stop bit is detected, receiv er immediately looks for the next start bit. however, if a non-zero character is received without a stop bit (fr aming error) and urxd n remains low for one-half of the bit period after the stop bit is sampled, receiver operates as if a new start bit were detected. parity error, c1 1 c2 c3 break c4 c6 tr a n s m i t t e r enabled usr n [txrdy] w 2 ww ww www manually asserted by bit - set command manually asserted start break c5 not transmitted c6 c4 stop break c3 c2 c1 1 c1 in transmission 3 umr2 n [txcts] = 1 1 c n = transmit characters 2 w = write 4 umr2 n [txrts] = 1 internal module select utxd n ucts n 3 urts n 4 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 uart modules freescale semiconductor 23-21 framing error, overrun error, and received break conditions set the respective pe, fe, oe, and rb error and break flags in the usr n at the received character bounda ry. they are valid only if usr n [rxrdy] is set. if a break condition is detected (urxd n is low for the entire character in cluding the stop bi t), a character of all 0s loads into the rece iver holding register and usr n[rb,rxrdy] are set. urxd n must return to a high condition for at least one-half bit time before a search for the next start bit begins. the receiver detects the beginning of a break in the middle of a character if the break pe rsists through the next character time. the receiver pl aces the damaged character in the rx fifo and sets the corresponding usr n error bits and usr n[rxrdy]. then, if the break lasts until the next character time, the receiver places an all-zero character into the rx fifo and sets usr n[rb,rxrdy]. figure 23-20 shows receiver functional timing. figure 23-20. receiver timing diagram 23.4.2.3 fifo the fifo is used in the uart?s receive buffer logic. th e fifo consists of three receiver holding registers. the receive buffer consists of the fifo and a receiver shift register connected to the urxd n (see figure 23-18 ). data is assembled in the receiver shift register and loaded into the top empty receiver holding register position of the fifo. therefore, data flowing from the receiver to the cpu is quadruple-buffered. in addition to the data byte, three status bits?parity error (pe), framing error (fe), and received break (rb)?are appended to each data character in th e fifo; overrun error (oe) is not appended. by c1 c2 c4 c6 c7 c8 c3 c5 c6, c7, and c8 is lost (c2) status data (c3) status data (c4) status data c5 is lost reset by command receiver enabled usr n [rxrdy] overrun internal module select usr n [ffull] (c1) status data usr n [oe] automatically asserted when ready to receive manually asserted first time, automatically negated if overrun occurs uop0[rts] = 1 1 umr2 n [rxrts] = 1 urxdn urts n 1 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 uart modules 23-22 freescale semiconductor programming the err bit in the uart?s mode re gister (umr1 n), status is provided in character or block modes. usr n [rxrdy] is set when at least one character is availa ble to be read by the cpu. a read of the receive buffer produces an output of data from the top of the fifo. after the read cycle, the data at the top of the fifo and its associated st atus bits are popped and the receiver shift register can add new data at the bottom of the fifo. the fifo-full st atus bit (ffull) is set if all three pos itions are filled with data. the rxrdy or ffull bit can be selected to ca use an interrupt and tx rdy or rxrdy can be us ed to generate a dma request. the two error modes are selected by umr1 n [err]: ? in character mode (umr1 n [err] = 0), status is given in the usr n for the character at the top of the fifo. ? in block mode, the usr n shows a logical or of all character s reaching the top of the fifo since the last reset error status command. status is updated as characters reach the top of the fifo. block mode offers a data-reception speed advantage where the software overhead of error-checking each character cannot be tolerated. ho wever, errors are not detected until the check is performed at the end of an entire message?the faulting character is not identified. in either mode, reading the usrn does not affect the fifo. the fifo is popped only when the receive buffer is read. the usr n should be read before reading the rece ive buffer. if all three receiver holding registers are full, a new character is held in the receive r shift register until space is available. however, if a second new character is received, the contents of the ch aracter in the receiver shift register is lost, the fifos are unaffected, and usr n[oe] is set when the receiver det ects the start bit of the new overrunning character. to support flow control, the receiver can be pr ogrammed to automatically negate and assert urts n , in which case the receiver automatically negates urts n when a valid start bit is detected and the fifo is full. the receiver asserts urts n when a fifo position becomes ava ilable; therefore, connecting urts n to the ucts n input of the transmitting devi ce can prevent overrun errors. note the receiver continues read ing characters in the fifo if the receiver is disabled. if the receiver is reset, the fifo, urts n control, all receiver status bits, interrupts, and dma requests ar e reset. no more characters are received until the receiver is reenabled. 23.4.3 looping modes the uart can be configured to operate in various looping modes. these modes are useful for local and remote system diagnostic functions. the modes are described in the following paragraphs and in section 23.3, ?memory map/ register definition.? the uart?s transmitter and receiver should be disabl ed when switching between modes. the selected mode is activated immediately upon mode selection, regardless of whether a character is being received or transmitted. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 uart modules freescale semiconductor 23-23 23.4.3.1 automatic echo mode in automatic echo mode, shown in figure 23-21 , the uart automatically rese nds received data bit by bit. the local cpu-to-receiver communi cation continues normally, but th e cpu-to-transmitter link is disabled. in this mode, received data is cl ocked on the receiver clock and re-sent on utxd n . the receiver must be enabled, but the transmitter need not be. figure 23-21. automatic echo because the transmitter is inactive, usr n [txemp,txrdy] is inactive and data is sent as it is received. received parity is checked but no t recalculated for transmission. charac ter framing is also checked, but stop bits are sent as they are recei ved. a received break is echoed as rece ived until the next valid start bit is detected. 23.4.3.2 local loopback mode figure 23-22 shows how utxd n and urxd n are internally connected in local loopback mode. this mode is for testing the operation of a uart by sending data to the transmitter and checking data assembled by the receiver to ensure proper operations. figure 23-22. local loopback features of this local loopback mode are: ? transmitter and cpu-to-receiver communications continue normally in this mode. ?urxd n input data is ignored. ?utxd n is held marking. ? the receiver is clocked by the transmitter clock. the transmitter must be enabled, but the receiver need not be. 23.4.3.3 remote loopback mode in remote loopback mode, shown in figure 23-23 , the uart automatically tr ansmits received data bit by bit on the utxd n output. the local cpu-to-transmitter link is di sabled. this mode is useful in testing receiver and transmitter operation of a remote uart. for this mode, transmitter uses the receiver clock. because the receiver is not active, received data cannot be read by the cpu and all status conditions are inactive. received parity is not check ed and is not recalculated for transm ission. stop bits ar e sent as they are received. a received break is echoed as received until next valid start bit is detected. disabled disabled tx rx cpu urxdn input urxdn input utxd n output cpu disabled disabled tx rx urxdn input utxd n output mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 uart modules 23-24 freescale semiconductor figure 23-23. remote loopback 23.4.4 multidrop mode setting umr1 n [pm] programs the uart to ope rate in a wake-up mode for multidrop or multiprocessor applications. in this mode, a mast er can transmit an address charac ter followed by a block of data characters targeted for one of up to 256 slave stations. although slave stations have their receivers disabled, they continuous ly monitor the master?s data stream. when the master sends an address character, the slave receiver notifies its respective cpu by setting usr n[rxrdy] and generating an interrupt (if program med to do so). each slave station cpu then compares the received address to its station address and enables its receiv er if it wishes to receive the subsequent data characters or block of data from the master station. unaddressed slave stations continue monitoring the data stream. data fiel ds in the data stream are separate d by an address character. after a slave receives a block of data, it s cpu disables the receiver and rep eats the process. functional timing information for multidrop mode is shown in figure 23-24 . cpu disabled disabled tx rx disabled disabled utxd n output urxdn input mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 uart modules freescale semiconductor 23-25 figure 23-24. multidrop mode timing diagram a character sent from the master st ation consists of a start bit, a programmed number of data bits, an address/data (a/d) bit flag, and a programmed number of stop bits. a/d equals 1 indicates an address character; a/d equals 0 indicates a data charac ter. the polarity of a/d is selected through umr1 n [pt]. umr1 n should be programmed before en abling the transmitter and loading the corresponding data bits into the transmit buffer. in multidrop mode, the receiver continuously monitors the received data stream, regardless of whether it is enabled or disabled. if the receiver is disabled, it sets the rxrdy bit and loads the character into the receiver holding register fifo provi ded the received a/d bit is a 1 (address tag). the character is discarded if the received a/d bit is 0 (data tag). if the receiver is enabled, all received characters are transferred to the cpu through the receive r holding register during read operations. in either case, data bits load into the data portion of the fi fo while the a/d bit load s into the status portion of the fifo normally used for a parity error (usr n [pe]). framing error, overrun error, and break detection operate normally. th e a/d bit takes the place of the parity bit; therefore, parity is neither calculated nor checked. mess ages in this mode may continues containing error detection and correction information. if 8-bit charact ers are not required, one way to provide error detection is to use soft ware to calculate parity and append it to the 5-, 6-, or 7-bit character. add1 transmitter enabled usrn [txrdy] c0 add2 11 internal module select a/d a/d a/d add1 receiver enabled usrn [rxrdy] c0 add2 11 internal module select a/d a/d a/d 0 a/d 0 a/d (c0) status data (add 2) status data add 1 peripheral station master station umr1 n [pm] = 11 umr1 n[pm] = 11 umr1 n[pt] = 1 add 1 umr1n [pt] = 0 c0 umr1 n [pt] = 1 add 2 utxd n urxdn mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 uart modules 23-26 freescale semiconductor 23.4.5 bus operation this section describes bus operati on during read, write, and interrupt acknowledge cycles to the uart module. 23.4.5.1 read cycles the uart module responds to reads with byte data. reserved registers return zeros. 23.4.5.2 write cycles the uart module accepts write data as bytes only. wr ite cycles to read-only or reserved registers complete normally wit hout an error termination, but data is ignored. 23.5 initialization/application information the software flowchart, figure 23-25 , consists of: ? uart module initialization?these routines c onsist of sinit and ch chk (see sheet 1 p. 23-30 and sheet 2 p. 23-31). before sinit is called at sy stem initialization, the calling routine allocates 2 words on the system fifo. on return to the calling routine, sinit passes uart status data on the fifo. if sinit finds no errors , the transmitter and receiver are enabled. sinit calls chchk to perform the checks. when called, sinit place s the uart in local loopback mode and checks for the following errors: ? transmitter never ready ? receiver never ready ? parity error ? incorrect character received ? i/o driver routine?this routine (see sheet 4 p. 23-33 and sheet 5 p. 23-34) consists of inch, the terminal input character routine which gets a character from the receiver, and outch, which sends a character to the transmitter. ? interrupt handling?this consists of sirq (see sheet 4 p. 23-33), which is executed after the uart module generates an interrupt caused by a ch ange-in-break (beginning of a break). sirq then clears the interrupt source, waits for the next change-in-break interrupt (end of break), clears the interrupt source again, then returns from exception processing to the system monitor. 23.5.1 interrupt and dma request initialization 23.5.1.1 setting up the uart to generate core interrupts the list below provides steps to pr operly initialize the uart to genera te an interrupt request to the processor?s interrupt controller. see section 10.3.6.1, ?interrupt sources,? for details on interrupt assignments for the uart modules. 1. initialize the appropriate icr x register in the interrupt controller. 2. unmask appropriate bits in imr in the interrupt controller. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 uart modules freescale semiconductor 23-27 3. unmask appropriate bits in the core?s st atus register (sr) to enable interrupts. 4. if txrdy or rxrdy generates interrupt requests, verify that dmareqc (in th e scm) does not also assign the uart?s txrdy and rxrdy into dma channels. 5. initialize interrupts in the uart, see table 23-13 . 23.5.1.2 setting up the uart to request dma service the uart is capable of generating two internal dma request signals: transmit and receive. the transmit dma request signal is asserted when the txr dy (transmitter ready) in the uart interrupt status register (uisr n [txrdy]) is set. when the transmit dma request signal is asserted, the dma can initiate a data copy, reading the next character tr ansmitted from memory and writing it into the uart transmit buffer (utb n ). this allows the dma channel to stre am data from memory to the uart for transmission without processor intervention. after the entire message has been moved into the uart, the dma would typically generate an end-of-data-transfer interrupt re quest to the cpu. the resulting interrupt service routine (isr) could query the uart programming model to determine the end-of-transmission status. similarly, the receive dma request signal is asserted when the fifo full or receive ready (ffull/rxrdy) flag in the inte rrupt status register (uisr n [ffull/rxrdy]) is set. when the receive dma request signal is asserted, the dma can initiate a data move, read ing the appropriate characters from the uart receive buffer (urb n ) and storing them in memory. this allows the dma channel to stream data from the uart receive buffer into memory without processor inte rvention. after the entire message has been moved from the uart, the dma would typical ly generate an end-of-d ata-transfer interrupt request to the cpu. the resulting interrupt service routine (isr) should query the uart programming model to determine the end-of-transmission status. in typical applications, the receive dma request should be configured to use rxrdy directly (and not ffull) to remove any complications related to retrieving the final characte rs from the fifo buffer. the implementation described in this section allows independent dma processi ng of transmit and receive data while continuing to s upport interrupt notification to the processor for cts change-of-state and delta break error managing. table 23-13. uart interrupts register bit interrupt umr1n 6rxirq uimr n 7 change of state (cos) uimr n 2 delta break uimr n 1 rxfifo full uimr n 0txrdy mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 uart modules 23-28 freescale semiconductor to configure the uart for dma requests: 1. initialize the dmareqc in the scm to map th e desired uart dma requests to the desired dma channels. for example, setting dmareqc[7:4] to 1000 maps uart0 re ceive dma requests to dma channel 1, setting dmareqc[11:8] to 1101 maps uart1 transmit dma requests to dma channel 2, and so on. it is possible to independent ly map transmit-based and receive-based uart dma requests in the dmareqc. 2. disable interrupts using the uimr register. the appropriate uimr bits must be cleared so that interrupt requests are disabled for those conditions for which a dma request is desired. for example, to generate transmit dma requests from uart1, uimr1[txrdy] should be cleared. this prevents txrdy from generating an interrupt request while a transmit dma request is generated. 3. enable dma access to the uart n registers by setting the corresponding pacr register in the scm for read/write in s upervisor and user modes. 4. enable dma access to sram by setting the spv bit in the core rambar, and the bde bit in the scm rambar 5. initialize the dma channel. th e dma should be configur ed for cycle steal m ode and a source and destination size of one byte. this causes a single byte to be transferred for each uart dma request. set the disable request bit (dcr n[d_req] to disable extern al requests when the bcr reaches zero. 6. for a transmit process: ? set the dma sar register to the address of the source data ?set dcr n [sinc] to increment the source pointer ? set dar to the address if the uart transmit buffer (utb) ?clear dcr n [dinc] ? set bcr to the number of bytes to transmit. 7. for a receive process: ? set the dma sar register to the addr ess of the uart receive buffer (urb) ?clear dcr n [sinc] ? set dar to the address of the source data ?set dcr n[dinc] to increment the destination pointer ? set bcr to the number of bytes to transmit. 8. start the data transfer by setting dcr n [eext], which enables the uart channel to issue dma requests. table 23-14 shows the dma requests. table 23-14. uart dma requests register bit dma request uisr n 1 receive dma request uisr n 0 transmit dma request mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 uart modules freescale semiconductor 23-29 23.5.2 uart module initialization sequence the following shows the uart module initialization sequence. 1. ucr n: a) reset the receiver and transmitter. b) reset the mode point er (misc[2?0] = 0b001). 2. uimr n: enable the desired interrupt sources. 3. uacr n: initialize the input enable control (iec bit). 4. ucsr n : select the receiver and transmitter clock. use timer as source if required. 5. umr1 n: a) if preferred, program operation of receiver ready-to-send (rxrts bit). a) select receiver-ready or fifo-f ull notification (rxrdy/ffull bit). b) select character or block error mode (err bit). c) select parity mode and type (pm and pt bits). d) select number of bits per character (b/cx bits). 6. umr2 n: a) select the mode of operation (cm bits). b) if preferred, program operation of transmitter ready-to-send (txrts). c) if preferred, program operation of clear-to-send (txcts bit). d) select stop-bit length (sb bits). 7. ucr n : enable transmitter and/or receiver. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 uart modules 23-30 freescale semiconductor figure 23-25. uart mode programming flowchart (sheet 1 of 5) serial module sinit initiate: channel interrupts chk1 call chchk save channel status enable any errors? y n enable receiver assert request to send sinitr return mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 uart modules freescale semiconductor 23-31 figure 23-25. uart mode programming flowchart (sheet 2 of 5) chchk chchk place channel in local loopback mode enable transmitter clear status word txchk is transmitter ready? y n sndchr rxchk send character to transmitter has character been received? n y a waited too long? n n waited too long? y y set transmitter- never-ready flag set receiver- never-ready flag b mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 uart modules 23-32 freescale semiconductor figure 23-25. uart mode programming flowchart (sheet 3 of 5) a b b frchk have framing error? set framing error flag prchk have parity error? set parity error flag get character from receiver same as transmitted character? set incorrect character flag n n y chrchk y n disable transmitter rstchn restore to original mode return y mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 uart modules freescale semiconductor 23-33 figure 23-25. uart mode programming flowchart (sheet 4 of 5) was irq caused by beginning of a break? sirq abrki n clear change-in- break status bit abrki1 n has end-of-break irq arrived ye t ? y y clear change-in- break status bit remove break character from receiver fifo replace return address on system stack and monitor warm start address sirqr rte n y does channel a receiver have a character? inch place character in d0 return mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 uart modules 23-34 freescale semiconductor figure 23-25. uart mode programming flowchart (sheet 5 of 5) outch is transmitter ready? n y send character to transmitter return mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor 24-1 chapter 24 i 2 c interface 24.1 introduction this chapter describes the i 2 c module, clock synchronization, and i 2 c programming model registers. it also provides extensiv e programming examples. 24.1.1 block diagram figure 24-1 is a i 2 c module block diagram, illu strating the interaction of the registers described in section 24.2, ?memory map/ register definition?. figure 24-1. i 2 c module block diagram address compare in/out data shift start, stop, input sync clock control registers and slave interface address decode i 2 c address data mux address irq data and arbitration control register internal bus register i 2 c frequency divider register i 2 c data i/o register i 2 c status register i 2 c control register i2c_scl i2c_sda (i2fdr) (i2cr) (i2sr) (i2dr) (i2adr) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 i 2 c interface 24-2 freescale semiconductor 24.1.2 overview i 2 c is a two-wire, bidirectional seri al bus that provides a simple, efficient method of data exchange, minimizing the interconnecti on between devices. this bus is suit able for applications that require occasional communication betwee n many devices over a short distance. the flexible i 2 c bus allows additional devices to connect to the bus for expansion and system development. the interface operates up to 100 kbps with maximum bus loading and timing. the device is capable of operating at higher baud rates, up to a maximum of the internal bus cloc k divided by 20, with reduced bus loading. the maximum communication length and the number of devices connected are limited by a maximum bus capacitance of 400 pf. the i 2 c system is a true multiple-master bus; it uses arbitration and collision detection to prevent data corruption in the event that multip le devices attempt to control the bus simultaneously. this feature supports complex applications with multiprocessor cont rol and can be used for ra pid testing and alignment of end products through external connect ions to an assembly-line computer. note the i 2 c module is compatible with the philips i 2 c bus protocol. for information on system configurati on, protocol, and restrictions, see the i 2 c bus specification, version 2.1 . note the gpio module must be configured to enable the peripheral function of the appropriate pins (refer to chapter 26, ?general purpose i/o module? ) prior to configuring the i 2 c module. 24.1.3 features the i 2 c module has these key features: ? compatibility with i 2 c bus standard version 2.1 ? multiple-master operation ? software-programmable for one of 50 different serial clock frequencies ? software-selectable acknowledge bit ? interrupt-driven, byte-by-byte data transfer ? arbitration-lost interrupt with automatic mode switching from master to slave ? calling address iden tification interrupt ? start and stop signal generation/detection ? repeated start signal generation ? acknowledge bit generation/detection ? bus-busy detection mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 i 2 c interface freescale semiconductor 24-3 24.2 memory map/register definition the below table lists the configur ation registers used in the i 2 c interface. 24.2.1 i 2 c address register (i2adr) i2adr holds the address the i 2 c responds to when addressed as a slav e. it is not the address sent on the bus during the address transf er when the module is perfo rming a master transfer. 24.2.2 i 2 c frequency divider register (i2fdr) the i2fdr, shown in figure 24-3 , provides a programmable pres caler to configure the i 2 c clock for bit-rate selection. table 24-1. i 2 c module memory map ipsbar offset register access reset value section/page 0x00_0300 i 2 c address register (i2adr) r/w 0x00 24.2.1/24-3 0x00_0304 i 2 c frequency divider register (i2fdr) r/w 0x00 24.2.2/24-3 0x00_0308 i 2 c control register (i2cr) r/w 0x00 24.2.3/24-4 0x00_030c i 2 c status register (i2sr) r/w 0x81 24.2.4/24-5 0x00_0310 i 2 c data i/o register (i2dr) r/w 0x00 24.2.5/24-6 ipsbar offset: 0x00_0300 (i2adr) access: user read/write 76543210 r adr 0 w r e s e t :00000000 figure 24-2. i 2 c address register (i2adr) table 24-2. i2adr field descriptions field description 7?1 adr slave address. contains the specific slave address to be used by the i 2 c module. slave mode is the default i 2 c mode for an address match on the bus. 0 reserved, must be cleared. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 i 2 c interface 24-4 freescale semiconductor 24.2.3 i 2 c control register (i2cr) i2cr enables the i 2 c module and the i 2 c interrupt. it also cont ains bits that govern operation as a slave or a master. ipsbar offset: 0x00_0304 (i2fdr) access: user read/write 76543210 r 0 0 ic w r e s e t :00000000 figure 24-3. i 2 c frequency divide r register (i2fdr) table 24-3. i2fdr field descriptions field description 7?6 reserved, must be cleared. 5?0 ic i 2 c clock rate. prescales the clock for bit -rate selection. the serial bit clock frequency is equal to the internal bus clock divided by the divider shown below. due to potentially slow i2c_scl and i2c_sda rise and fall times, bus signals are sampled at the prescaler frequency. ic divider ic divider ic divider ic divider 0x00 28 0x10 288 0x20 20 0x30 160 0x01 30 0x11 320 0x21 22 0x31 192 0x02 34 0x12 384 0x22 24 0x32 224 0x03 40 0x13 480 0x23 26 0x33 256 0x04 44 0x14 576 0x24 28 0x34 320 0x05 48 0x15 640 0x25 32 0x35 384 0x06 56 0x16 768 0x26 36 0x36 448 0x07 68 0x17 960 0x27 40 0x37 512 0x08 80 0x18 1152 0x28 48 0x38 640 0x09 88 0x19 1280 0x29 56 0x39 768 0x0a 104 0x1a 1536 0x2a 64 0x3a 896 0x0b 128 0x1b 1920 0x2b 72 0x3b 1024 0x0c 144 0x1c 2304 0x2c 80 0x3c 1280 0x0d 160 0x1d 2560 0x2d 96 0x3d 1536 0x0e 192 0x1e 3072 0x2e 112 0x3e 1792 0x0f 240 0x1f 3840 0x2f 128 0x3f 2048 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 i 2 c interface freescale semiconductor 24-5 24.2.4 i 2 c status register (i2sr) i2sr contains bits that indicate transaction direction and status. ipsbar offset: 0x00_0308 (i2cr) access: user read/write 76543210 r e s e t :00000000 figure 24-4. i 2 c control register (i2cr) table 24-4. i2cr field descriptions field description 7 ien i 2 c enable. controls the software reset of the entire i 2 c module. if the module is enabled in the middle of a byte transfer, slave mode ignores the current bus transfer and star ts operating when the next start condition is detected. master mode is not aware that the bus is busy; initiating a start cycle ma y corrupt the current bus cycle, ultimately causing the current master or the i 2 c module to lose arbitration, after which bus operation returns to normal. 0the i 2 c module is disabled, but registers can be accessed. 1the i 2 c module is enabled. this bit must be set before any other i2cr bits have any effect. 6 iien i 2 c interrupt enable. 0i 2 c module interrupts are disabled, but currently pending interrupt condition is not cleared. 1i 2 c module interrupts are enabled. an i 2 c interrupt occurs if i2sr[iif] is also set. 5 msta master/slave mode select bit. if the master loses arbitr ation, msta is cleared without generating a stop signal. 0 slave mode. changing msta from 1 to 0 generates a stop and selects slave mode. 1 master mode. changing msta from 0 to 1 signals a start on the bus and selects master mode. 4 mtx transmit/receive mode select bit. selects th e direction of master and slave transfers. 0 receive 1 transmit. when the device is addressed as a slave, soft ware must set mtx according to i2sr[srw]. in master mode, mtx must be set according to the type of transfer required. therefore, when the mcu addresses a slave device, mtx is always 1. 3 txak transmit acknowledge enable. specifies the value driven ont o i2c_sda during acknowledge cycles for master and slave receivers. writing txak applies only when the i 2 c bus is a receiver. 0 an acknowledge signal is sent to the bus at the ninth clock bit after receiving one byte of data. 1 no acknowledge signal response is sent (acknowledge bit = 1). 2 rsta repeat start. always read as 0. attempting a repeat star t without bus mastership ca uses loss of arbitration. 0 no repeat start 1 generates a repeated start condition. 1 reserved, must be cleared. ipsbar offset: 0x00_030c (i2sr) access: user read/write 76543210 r icf iaas ibb ial 0 srw iif rxak w r e s e t :10000001 figure 24-5. i 2 c status register (i2sr) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 i 2 c interface 24-6 freescale semiconductor 24.2.5 i 2 c data i/o register (i2dr) in master-receive mode, readi ng i2dr allows a read to occur and for the next data byte to be received. in slave mode, the same function is available after the i 2 c has received its slave address. table 24-5. i2sr field descriptions field description 7 icf i 2 c data transferring bit. while one byte of data is transferred, icf is cleared. 0 transfer in progress 1 transfer complete. set by falling edge of ninth clock of a byte transfer. 6 iaas i 2 c addressed as a slave bit. the cpu is interrupted if i2cr [iien] is set. next, the cpu must check srw and set its tx/rx mode accordingly. writing to i2cr clears this bit. 0 not addressed. 1 addressed as a slave. set when its own address (iadr) matches the calling address. 5 ibb i 2 c bus busy bit. indicates the status of the bus. 0 bus is idle. if a stop signal is detected, ibb is cleared. 1 bus is busy. when start is detected, ibb is set. 4 ial i 2 c arbitration lost. set by hardware in the following circum stances. (ial must be cleared by software by writing zero to it.) ? i2c_sda sampled low when the master drives high during an address or data-transmit cycle. ? i2c_sda sampled low when the master drives hi gh during the acknowledge bit of a data-receive cycle. ? a start cycle is attempted when the bus is busy. ? a repeated start cycle is requested in slave mode. ? a stop condition is detected wh en the master did not request it. 3 reserved, must be cleared. 2 srw slave read/write. when iaas is set, srw indicates the va lue of the r/w command bit of the calling address sent from the master. srw is valid only when a complete transf er has occurred, no other transfers have been initiated, and the i 2 c module is a slave and has an address match. 0 slave receive, master writing to slave. 1 slave transmit, master reading from slave. 1 iif i 2 c interrupt. must be cleared by software by writing a 0 in the interrupt routine. 0no i 2 c interrupt pending 1 an interrupt is pending, which causes a processor interrup t request (if iien = 1). set when one of the following occurs: ? complete one byte transfer (set at the falling edge of the ninth clock) ? reception of a calling address that matches it s own specific address in slave-receive mode ? arbitration lost 0 rxak received acknowledge. the val ue of i2c_sda during the acknowledge bit of a bus cycle. 0 an acknowledge signal was received after the completion of 8-bit data transmission on the bus 1 no acknowledge signal was detected at the ninth clock. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 i 2 c interface freescale semiconductor 24-7 24.3 functional description the i 2 c module uses a serial da ta line (i2c_sda) and a serial clock line (i2c_scl ) for data transfer. for i 2 c compliance, all devices connected to these two signals must have ope n drain or open collector outputs. the logic and function is exercised on both lines with external pull-up resistors. out of reset, the i 2 c default state is as a slave receiver. theref ore, when not programme d to be a master or responding to a slave transmit address, the i 2 c module should return to the de fault slave receiver state. see section 24.4.1, ?initialization sequence,? for exceptions. normally, a standard communication is composed of four parts: start signal, slave addr ess transmission, data transfer, and stop signal. these ar e discussed in the following sections. 24.3.1 start signal when no other device is bus master (i2c_scl and i2c_sda lines are at logic high), a device can initiate communication by sending a start signal (see a in figure 24-7 ). a start signal is defined as a high-to-low transition of i2c_sda while i2c_scl is high. this signal denotes the beginning of a data transfer (each data transfer can be se veral bytes long) and awakens all slaves. ipsbar offset: 0x00_0310 (i2dr) access: user read/write 76543210 r data w reset:00000000 figure 24-6. i 2 c data i/o register (i2dr) table 24-6. i2dr field description field description 7?0 data i 2 c data. when data is written to this register in master trans mit mode, a data transfer is in itiated. the most significant bit is sent first. in master receive mode, reading this register initiates the reception of the next byte of data. in slave mode, the same functions are available after an address match has occurred. note: in master transmit mode, the first byte of data writte n to i2dr following assertion of i2cr[msta] is used for the address transfer and should comprise the calling address (in position d7?d1) concatenated with the required r/w bit (in position d0). this bit (d0) is not automatically appended by t he hardware, software must provide the appropriate r/w bit. note: i2cr[msta] generates a start when a master does not already own the bus. i2cr[rsta] generates a start (restart) without the master first issuing a stop (i.e., the master already owns the bus). to start the read of data, a dummy read to this register starts the read process from the slave. the next read of the i2dr register contains the actual data. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 i 2 c interface 24-8 freescale semiconductor figure 24-7. i 2 c standard communication protocol 24.3.2 slave address transmission the master sends the slave address in the first byte after the start signa l (b). after the seven-bit calling address, it sends the r/w bit (c), which tells the slav e data transfer direction (0 equals write transfer, 1 equals read transfer). each slave must have a unique address. an i 2 c master must not transmit it s own slave address; it cannot be master and slave at the same time. the slave whose address matches that sent by the master pulls i2c_sda low at the ninth serial clock (d) to return an acknowledge bit. 24.3.3 data transfer when successful slave addressing is achiev ed, data transfer can proceed (see e in figure 24-7 ) on a byte-by-byte basis in the dire ction specified by the r/w bi t sent by the calling master. data can be changed only while i2c_scl is low and must be held stable while i2c_scl is high, as figure 24-7 shows. i2c_scl is pulsed once fo r each data bit, with the msb being sent first. the receiving device must acknowledge each byte by pulling i2c_sda low at the ninth clock; therefore, a data byte transfer takes nine clock pulses. see figure 24-8 . figure 24-8. data transfer 12345678 12345678 9 9 ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w xxx d7 d6 d5 d4 d3 d2 d1 d0 calling address r/w ack bit data byte no ack bit stop signal lsb msb lsb msb start signal a b d c e f interrupt bit set (byte complete) i2c_scl i2c_sda i2c_ scl held low while interrupt is serviced 123456789 5678 4321 bit6 bit4 bit3 bit2 bit1 bit5 bit7 bit0 bit6 bit4 bit3 bit2 bit1 bit5 bit0 bit7 start signal ack from receiver stop no ack bit data byte slave address r/w signal interrupt bit set (byte complete) 9 i2c_scl i2c_sda i2c_ scl held low while interrupt is serviced mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 i 2 c interface freescale semiconductor 24-9 24.3.4 acknowledge the transmitter releases the i2 c_sda line high during the acknow ledge clock pulse as shown in figure 24-9 . the receiver pulls down the i2c_sda line dur ing the acknowledge cloc k pulse so that it remains stable low during the high period of the clock pulse. if it does not acknowledge the master, the slave receiver must l eave i2c_sda high. the master can then generate a stop signal to abort data transfer or generate a start signal (repeated start, shown in figure 24-10 and discussed in section 24.3.6, ?repeated start? ) to start a new calling sequence. figure 24-9. acknowledgement by receiver if the master receiver does not acknowledge the slav e transmitter after a byte transmission, it means end-of-data to the slave. the slave releases i2c_sda for the master to generate a stop or start signal ( figure 24-9 ). 24.3.5 stop signal the master can terminate communicat ion by generating a stop signal to free the bus. a stop signal is defined as a low-to-high transition of i2c_sda while i2c_scl is at logical high (see f in figure 24-7 ). the master can generate a stop even if the slave has generated an acknowledgment, at which point the slave must release the bus. the master may also ge nerate a start signal foll owing a calling address, without first generating a stop signal. refer to section 24.3.6, ?repeated start.? 24.3.6 repeated start a repeated start signal is a start signal generated without first generating a stop signal to terminate the communication, as shown in figure 24-10 . the master uses a repeated start to communicate with another slave or with the same slave in a different mode (transmit/receive mode ) without releasing the bus. 56789 4321 bit6 bit4 bit3 bit2 bit1 bit5 bit7 bit0 start signal r/w ack i2c_scl i2c_sda by transmitter i2c_sda by receiver mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 i 2 c interface 24-10 freescale semiconductor figure 24-10. repeated start various combinations of read/w rite formats are then possible: ? the first example in figure 24-11 is the case of master-transmitter transmitting to slave-receiver. the transfer directi on is not changed. ? the second example in figure 24-11 is the master readi ng the slave immediately after the first byte. at the moment of the first acknowledge, the mast er-transmitter becomes a master-receiver and the slave-receiver becomes slave-transmitter. ? in the third example in figure 24-11 , start condition and slave address are repeated using the repeated start signal. this is to communicate with same slave in a different mode without releasing the bus. the master transmits data to the slave first, and then the master reads data from slave by reve rsing the r/w bit. figure 24-11. data transfer, combined format 1234567 8 1 2 5 678 34 ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w 99 xx new calling address r/w no ack bit stop signal repeated start signal ack bit r/w calling address start msb lsb msb lsb signal a i2c_scl i2c_sda st a 7bit slave address 0 a data data a/a r/w sp from master to slave from slave to master st a 7bit slave address 1 a data a r/w sp st a 1 a data r/w rept a 7-bit slave 0 a data data a/a r/w sp st address 7-bit slave address example 1: example 2: example 3: master reads from slave master writes to slave note: no acknowledge on the last byte data st = start sp = stop a = acknowledge ( i2c_ sda low) a = not acknowledge ( i2c_ sda high) rept st = repeated start mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 i 2 c interface freescale semiconductor 24-11 24.3.7 clock synchronization and arbitration i 2 c is a true multi-master bus that allows more than one ma ster connected to it. if two or more master devices simultaneously request control of the bus, a clock synchronization proc edure determines the bus clock. because wire-and logic is performed on the i2c_scl line, a high-to-low transition on the i2c_scl line affects all the devices connected on the bus. the devices start counting their low period and after a device?s clock has gone low, it holds the i2c_scl line low until the clock high state is reached. however, change of low to high in this device?s cl ock may not change the state of the i2c_scl line if another device clock remains within its low period. th erefore, synchronized clock i2c_scl is held low by the device with the longest low period. devices with shorter low periods enter a high wait state during this time (see figure 24-12 ). when all devices concerned have counted off their low period, the synchronized clock (i2c_scl) line is released and pulled high. at this poi nt, the device clocks and the i2c_scl line are synchronize d, and the devices start counting their high periods. the first device to complete its high period pulls the i2c_scl line low again. figure 24-12. clock synchronization a data arbitration procedure determin es the relative priority of the c ontending masters. a bus master loses arbitration if it transmits logic 1 while another master transmits lo gic 0. the losing masters immediately switch over to slave receive mode and stop driving i2c_sda output (see figure 24-13 ). in this case, transition from master to slave mode does not generate a stop c ondition. meanwhile, hardware sets i2sr[ial] to indicate loss of arbitration. figure 24-13. arbitration procedure internal counter reset wait start counting high period i2c_scl1 i2c_scl2 i2c_scl master 2 loses arbitration, and becomes slave-receiver i2c_scl i2c_sda by master1 i2c_sda by master2 i2c_sda mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 i 2 c interface 24-12 freescale semiconductor 24.3.8 handshaking and clock stretching the clock synchronization m echanism can acts as a handshake in da ta transfers. slave devices can hold i2c_scl low after completing one byte transfer. in such a case, the cl ock mechanism halts the bus clock and forces the master clock into wait states until the slave releases i2c_scl. slaves may also slow down the transf er bit rate. after the master has driven i2c_scl low, the slave can drive i2c_scl low for the required period and then re lease it. if the slave i2c_scl low period is longer than the master i2c_scl low period, the resulting i2c_scl bus signal low period is stretched. 24.4 initialization/application information the following examples show programming for initia lization, signaling start, post-transfer software response, signaling stop, and generating a repeated start. 24.4.1 initialization sequence before the interface can transfer serial data, registers must be initialized: 1. set i2fdr[ic] to obtain i2c_scl frequency from the system bus clock. see section 24.2.2, ?i 2 c frequency divider register (i2fdr).? 2. update the i2adr to de fine its slave address. 3. set i2cr[ien] to enable the i 2 c bus interface system. 4. modify the i2cr to select or deselect master/slave mode, transmit/receive mode, and interrupt-enable or not. note if i2sr[ibb] is set when the i 2 c bus module is enabled, execute the following pseudocode sequence before proceeding with normal initialization code. this issues a stop command to the slave device, placing it in idle state as if it were power-cycled on. i2cr = 0x0 i2cr = 0xa0 dummy read of i2dr i2sr = 0x0 i2cr = 0x0 i2cr = 0x80 ; re-enable 24.4.2 generation of start after completion of the initialization procedure, seri al data can be transmitted by selecting the master transmitter mode. on a multiple-mast er bus system, i2sr[ibb] must be tested to determine whether the serial bus is free. if the bus is free (ibb is cleared), the start signal and the firs t byte (the slave address) can be sent. the data written to th e data register comprises the addre ss of the desired slave and the lsb indicates the transfer direction. the free time between a stop and the next start conditi on is built into the hard ware that generates the start cycle. depending on the relative frequencies of the system clock and the i2c_scl period, the mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 i 2 c interface freescale semiconductor 24-13 processor may need to wait until the i2c is busy af ter writing the calling address to the i2dr before proceeding with the following instructions. the following example signals start and transm its the first byte of da ta (slave address): 1. check i2sr[ibb]. if it is set, wait until it is clear. 2. after cleared, set to transmit mode by setting i2cr[mtx]. 3. set master mode by setting i2cr[msta ]. this generates a start condition. 4. transmit the calling address via the i2dr. 5. check i2sr[ibb]. if it is clear, wa it until it is set and go to step #1. 24.4.3 post-transfer software response sending or receiving a byte sets the i2sr[icf], which indicates one byte co mmunication is finished. i2sr[iif] is also set. an interrupt is generated if the interrupt func tion is enabled during initialization by setting i2cr[iien]. software must first clear i2sr[iif ] in the interrupt routine. reading from i2dr in receive mode or writing to i2dr in transmit mode can clear i2sr[icf]. software can service the i 2 c i/o in the main program by monitoring th e iif bit if the interrupt function is disabled. polling should monitor iif ra ther than icf, because that operation is different when arbitration is lost. when an interrupt occurs at the end of the address cycle, the master is always in transmit mode; the address is sent. if master recei ve mode is required, i2cr[mtx] should be toggled. during slave-mode address cycles (i2 sr[iaas] = 1), i2sr[srw] is read to determine the direction of the next transfer. mtx is programmed accordingly. for slave-mode data cycles (iaas = 0) , srw is invalid. mtx should be read to determine the current transfer direction. the following is an example of a software response by a master transm itter in the interrupt routine (see figure 24-14 ). 1. clear the i2cr[iif] flag. 2. check if acknowledge has been received, i2sr[rxak]. 3. if no ack, end transmission. else, tr ansmit next byte of data via i2dr. 24.4.4 generation of stop a data transfer ends when the master signals a stop, which can occur af ter all data is sent, as in the following example. 1. check if acknowledge has been received, i2sr[r xak]. if no ack, end transmission and go to step #5. 2. get value from transmitting counter, tx cnt. if no more data, go to step #5. 3. transmit next byte of data via i2dr. 4. decrement txcnt and go to step #1 5. generate a stop condition by clearing i2cr[msta]. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 i 2 c interface 24-14 freescale semiconductor for a master receiver to terminate a data transf er, it must inform the sl ave transmitter by not acknowledging the last data byte. this is done by set ting i2cr[txak] before re ading the next-to-last byte. before the last byte is re ad, a stop signal must be generated, as in the following example. 1. decrement rxcnt. 2. if last byte (rxcnt = 0) go to step #4. 3. if next to last byte (rxcnt = 1), set i2cr[txak] to disable ack and go to step #5. 4. this is last byte, so clear i2cr [msta] to generate a stop signal. 5. read data from i2dr. 6. if there is more data to be read (rxcnt 0), go to step #1 if desired. 24.4.5 generation of repeated start if the master wants the bus after the data transfer , it can signal another star t followed by another slave address without signaling a stop, as in the following example. 1. generate a repeated start by setting i2cr[rsta]. 2. transmit the calling address via i2dr. 24.4.6 slave mode in the slave interrupt service routine, software must poll the i2sr[iaas] bit to determine if the controller has received its slave address. if iaas is set, soft ware must set the transmit /receive mode select bit (i2cr[mtx]) according to the i2sr[srw]. writing to i2cr clears iaas automatically. the only time iaas is read as set is from the interrupt at the e nd of the address cycle where an address match occurred; interrupts resulting from subsequent data transfers have iaas cleared. a data transfer can now be initiated by writing information to i2dr for slave transmits, or read from i2 dr in slave-receive mode. a dummy read of i2dr in slave/receive mode releases i2c_scl, allowing the master to send data. in the slave transmitter routine, i2 sr[rxak] must be tested before sending the next byte of data. setting rxak means an end-of-data signal fr om the master receiver, after wh ich software must switch it from transmitter to receiver mode. reading i2dr releases i2c_scl so the master can generate a stop signal. 24.4.7 arbitration lost if several devices try to engage the bus at the sa me time, one becomes mast er. hardware immediately switches devices that lose arbitration to slave receive mode. data output to i2c_sda stops, but i2c_scl continues generating until the end of the byte during which arbitration is lost. an interrupt occurs at the falling edge of the ninth clock of this tran sfer with i2sr[ial] set and i2cr[msta] cleared. if a non-master device tries to tran smit or execute a start, hardware inhibits the transmission, clears msta without signaling a stop, generates an interrupt to the cpu, and sets ial to indicate a failed attempt to engage the bus. when considering these ca ses, slave service routine should first test ial and software should clear it if it is set. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 i 2 c interface freescale semiconductor 24-15 figure 24-14. flow-chart of typical i 2 c interrupt routine clear master mode? tx/rx ? last byte transmitted ? rxak= 0 ? end of addr cycle (master rx) ? write next byte to i2dr switch to rx mode dummy read from i2dr generate stop signal read data from i2dr and store set txak =1 generate stop signal 2nd last byte to be last byte to be ? arbitration lost? clear ial iaas=1 ? iaas=1 ? srw=1 ? tx/rx ? set tx mode write data to i2dr set rx mode dummy read from i2dr ack from receiver ? tx next byte read data from i2dr and store switch to rx mode dummy read from i2dr rte yn y y y y y y y y y n n n n n n n n n y tx rx rx tx (write) (read) n iif address cycle data cycle read read? mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 i 2 c interface 24-16 freescale semiconductor mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor 25-1 chapter 25 flexcan the flexcan module is a communication controller implementing the controller area network (can) protocol, an asynchronous communications protocol used in automotive and industrial control systems. it is a high speed (1 mbit/sec), short distance, priority base d protocol which can communicate using a variety of mediums (for example, fiber opt ic cable or an unshiel ded twisted pair of wi res). the flexcan supports both the standard and extended id entifier (id) message formats specified in the can protocol specification, revision 2.0, part b. the can protocol was primarily, but not only, designed to be used as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the emi environment of a vehicle, cost-effectiveness and required bandwidth. a general work ing knowledge of the can protocol revision 2.0 is assumed in this docu ment. for details, refer to the ca n protocol revision 2.0 specification. 25.1 features ? based on and includes all existing freescale toucan module features ? freescale ip interface architecture ? full implementation of the can pr otocol specification version 2.0 ? standard data and remote frames (up to 109 bits long) ? extended data and remote fr ames (up to 127 bits long) ? 0?8 bytes data length ? programmable bit rate up to 1mbit/sec ? up to 16 flexible message buffers of 0?8 bytes da ta length, each configurable as rx or tx, all supporting standard and extended messages ? listen-only mode capability ? content-related addressing ? no read/write semaphores ? three programmable mask regist ers: global (for mbs 0-13), sp ecial for mb14, and special for mb15 ? programmable transmit-first scheme: lowest id or lowest buffer number ? ?time stamp?, based on 16-bit free-running timer ? global network time, synchr onized by a specific message ? programmable i/o modes ? maskable interrupts ? independent of the transmission medium (external transceiver is assumed) ? open network architecture ? multimaster bus ? high immunity to emi ? short latency time for high-priority messages ? low-power ?sleep? mode, with pr ogrammable ?wake up? on bus activity mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 flexcan 25-2 freescale semiconductor a block diagram describing th e various submodules of the flexcan module is shown in figure 25-1 . each submodule is described in detail in subsequent sections. figure 25-1. flexcan block diagram and pinout 25.1.1 flexcan memory map the flexcan module address space is sp lit into 128 bytes star ting at the base addres s, and then an extra 256 bytes starting at the base addr ess +128. the upper 256 are fully used for the message buffer structures, as described in section 25.3.2, ?message buffer memory map .? out of the lower 128 bytes, only part is occupied by various registers. table 25-1. flexcan memory map ipsbar offset [31:24] [23:16] [15:8] [7:0] 0x1c_0000 module configuration register (mcr) reserved 0x1c_0004 reserved control register 0 (canctrl0) control register 1 (canctrl1) mb0 mb2 mb1 mb3 mb12 mb14 mb13 mb15 0.25k/0.5kb ram bus interface unit mb # (0-15) transmitter receiver control cantx canrx internal bus mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 flexcan freescale semiconductor 25-3 25.1.2 external signals the flexcan module/can transceive r is composed of two signals: cantx, which is the serial transmitted data, and canrx, whic h is the serial received data. 0x1c_0008 prescaler divider (presdiv) control register 2 (canctrl2) free running timer (timer) 0x1c_000c reserved reserved 0x1c_0010 rx global mask (rxgmask) 0x1c_0014 rx buffer 14 mask (rx14mask) 0x1c_0018 rx buffer 15 mask (rx15mask) 0x1c_0020 error and status (estat) interrupt masks (imask) 0x1c_0024 interrupt flags (iflag) rx error counter (rxectr) tx error counter (txectr) 0x1c_0034? 0x1c_007f reserved reserved 0x1c_0080? 0x1c_017f message buffers 0?15 table 25-1. flexcan memory map (continued) ipsbar offset [31:24] [23:16] [15:8] [7:0] mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 flexcan 25-4 freescale semiconductor 25.2 the can system a typical can system is shown below in figure 25-2 . figure 25-2. typical can system each can station is conn ected physically to the can bus through a transceiver. the tr ansceiver provides the transmit drive, waveshaping, and receive/compare f unctions required for communicating on the can bus. it can also provide protection against damage to the flex can caused by a defective can bus or defective stations. 25.3 message buffers 25.3.1 message buffer structure figure 25-3 shows the extended (29 bit) id message buffer structure. figure 25-4 displays the standard (11 bit) id message buffer structure. can bus flexcan canrx transceiver can station 1 can station 2 can station n cantx coldfire processor mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 flexcan freescale semiconductor 25-5 figure 25-3. extended id message buffer structure figure 25-4. standard id message buffer structure 25.3.1.1 common fields for extend ed and standard format frames table 25-2 describes the message buffer fi elds that are common to both ex tended and standard identifier format frames. 15?8 7?4 3?0 0x0 time stamp code length control/status 0x2 id[28:18] srr ide id[17-15] id_high 0x4 id[14-0] rtr id_low 0x6 data byte 0 data byte 1 0x8 data byte 2 data byte 3 0xa data byte 4 data byte 5 0xc data byte 6 data byte 7 0xe reserved 15?8 7?4 3?0 0x0 time stamp code length control/status 0x2 id[28:18] rtr 0 0 0 0 id_high 0x4 16-bit time stamp id_low 0x6 data byte 0 data byte 1 0x8 data byte 2 data byte 3 0xa data byte 4 data byte 5 0xc data byte 6 data byte 7 0xe reserved mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 flexcan 25-6 freescale semiconductor table 25-2. common extended/standard format frames field description time stamp contains a copy of the high byte of the free running timer, which is captured at the beginning of the identifier field of the frame on the can bus. code refer to ta bl e 2 5 - 3 and table 25-4 . rx length length (in bytes) of the rx da ta stored in offset 0x6 through 0xd of the buffer. this field is written by the flexcan module, copied from the data length code (dlc) field of the received frame. tx length length (in bytes) of the data to be transmitted, located in offset 0x6 through 0xd of the buffer. this field is written by the cpu, and is used as the dlc field value. if remote transmission request (rtr)) = 1, the frame is a remote frame and will be transmi tted without the data field, regardless of the value in tx length. data this field can store up to eight data bytes for a frame. for rx frames, the data is stored as it is received from the bus. for tx frames, the cpu prov ides the data to be transmitted within the frame. reserved this word entry field (16 bits) should not be accessed by the cpu. table 25-3. message buffer codes for receive buffers rx code before rx new frame description rx code after rx new frame comment 0000 not active ? message buffer is not active. ? ? 0100 empty ? message buffer is active and empty. 0010 ? 0010 full ? message buffer is full. 0110 if a cpu read occurs before the new frame, new receive code is 0010. 0110 overrun ? second frame wa s received into a full buffer before the cpu read the first one. 0101 1 1 for transmit message buffers, upon read, the busy bit should be ignored. busy ? message buffer is now being filled with a new receive frame. this condition will be cleared within 20 cycles. 0010 an empty buffer was filled. 0011 1 0110 a full buffer was filled. 0111 1 0110 an overrun buffer was filled. table 25-4. message buffer codes for transmit buffers rtr initial tx code description code after successful transmission x 1000 message buffer not ready for transmit. ? 0 1100 data frame to be transmitted once, unconditionally. 1000 1 1100 remote frame to be transmitted once, and message buffer becomes an rx message buffer for data frames. 0100 0 1010 1 1 when a matching remote request frame is detected, th e code for such a message buffer is changed to be 1110. data frame to be transmitted only as a response to a remote frame. 1010 0 1110 data frame to be transmitted only once, unconditionally, and then only as a response to remote frame. 1010 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 flexcan freescale semiconductor 25-7 25.3.1.2 fields for extended format frames table 25-5 describes the message buffer fields used only for extended identifier format frames. 25.3.1.3 fields for standard format frames table 25-6 describes the message buffer fields used only for standard identifier format frames. 25.3.2 message buffer memory map the message buffer memory map starts at an of fset of 0x80 from the fl excan?s base address (0x1c_0000). the 256-byte me ssage buffer space is fully used by the 16 message buffer structures. table 25-5. extended format frames field description id[28:18]/[17:15] contains the 14 most si gnificant bits of the extended identifier , located in the id high word of the message buffer. substitute remote request (srr) contains a fixed recessive bit, used only in extended format. should be set to one by the user for tx buffers. it will be stored as received on the can bus for rx buffers. this is a bit in the id high word of the message buffer. id extended (ide) if extended format frame is used, this field should be set to one. if zero, standard format frame should be used. this is a bit in the id high word of the message buffer. id[14:0] bits [14:0] of the exten ded identifier, located in the id low word of the message buffer. remote transmission request (rtr) this bit is located in the least significant bit of the id low word of the message buffer; 0 data frame 1 remote frame. table 25-6. standard format frames field description id[28:18] contains bits [28:18] of the identifier, located in the id high word of the message buffer. the four least significant bits in this register (correspo nding to the ide bit and id[17:15] for an extended identifier message) must all be written as logic zeros to ensure proper operation of the flexcan. rtr remote transmission request. this bit is located in the id high word of the message buffer. 0 data frame 1 remote frame. if the flexcan transmits this bit as a one and re ceives it as a zero, an ?arbitration loss? is indicated. if the flexcan transmits this bit as a zero and receives it as a one, a bit error is indicated. if the flexcan transmits a value and receives a matching response, a successful bit transmission is indicated. 16-bit time stamp the 16-bit time stamp, located in the id low word of the message buffer, is not needed for standard format, and is used in a standard format buffer to store the 16-bit value of the free-running timer. the timer value is captured at the beginning of the identifier field of the frame on the can bus. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 flexcan 25-8 freescale semiconductor figure 25-5. flexcan memory map 25.4 functional overview the flexcan module is flexible in that each one of its 16 message buffers (mbs) can be assigned either as a transmit buffer or a receive buf fer. each mb, which is up to 8 bytes long, is also assigned an interrupt flag bit that indicates successful comple tion of either trans mission or reception. note note that for both processes, the firs t cpu action in preparing a mb should be to deactivate it by setting its code field to the proper value. this requirement is mandatory to assure proper operation. 25.4.1 transmit process the cpu prepares or changes an mb for transmission by ex ecuting the following steps: ? writing the control/status word to hold tx mb inactive (code = 1000). ? writing the id_high and id_low words. id_high id_low control/status reserved 8 bytes data field 0x80-0x8f 0x82 0x84 0x86 message buffer 0 message buffer 1 message buffer 2 message buffer 15 0x8c 0x90 0xa0 0x170 message buffers 0x8e 0x17e 0x9e 0xae 0xb0 0x16e flexcan base address offset message buffer 3 through message buffer 14 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 flexcan freescale semiconductor 25-9 ? writing the data bytes ? writing the control/status word (active code, length) note the first and last steps are mandatory! starting from the last step, this mb will participate in the internal ar bitration process, which takes place every time the can bus is sensed as fr ee by the receiver or at the inter-frame space, and there is at least one mb ready for transmission. this in ternal arbitration process is intend ed to select the mb from which the next frame is transmitted. when this process is over, and there is a ?winner? mb for tr ansmission, the frame is tr ansferred to the serial message buffer (smb) for transmission (move out). while transmitting, the flexcan tran smits up to eight data bytes, even if the dlc is bigger in value. at the end of the successful transmission, the value of the free-running ti mer (which was captured at the beginning of the identifier field on the can bus), is written into the ?time stamp? field in the mb, the code field in the control/status word of the mb is updated and a status flag is set in the iflag register. 25.4.2 receive process the cpu prepares or changes an mb for frame reception by executing the following steps: ? writing the control/status word to hold rx mb inactive (code = 0000). ? writing the id_high and id_low words. ? writing the control/status word to mark the rx mb as active and empty. note the first and last steps are mandatory! starting from the last step, this mb is an active receive buffer and will participate in the internal matching process, which takes place every time the receiver receives an error-free frame. in this process, all active receive buffers compare their id va lue to the newly received one, a nd if a match occurs, the frame is transferred (move in) to the first (that is, lowest entry) matching mb. the valu e of the free-running timer (which was captured at the beginni ng of the identifier field on the ca n bus) is written into the ?time stamp? field in the mb, the id fi eld, data field (8 bytes at most) and the lengt h field are stored, the code field is updated and a status fl ag is set in the iflag register. the cpu should read a receive frame from its mb in the following way: ? control/status word (mandatory?activat es internal lock for this buffer). ? id (optional?needed only if a mask was used). ? data field word(s). ? free-running timer (release s internal lock ?optional). the read of the free-runni ng timer is not mandatory. if not execu ted, the mb remains locked, unless the cpu starts the read process for a nother mb. note that only a single mb is locked at a time. the only mandatory cpu read operation is of the control/status word, to assure data cohe rency. if the busy bit is set in the mb code, then the cpu should defer until this bit is negated. the cpu should synchronize to frame reception by the status flag for the specific mb (see section 25.5.10, ?interrupt fl ag register (iflag) ?), and not by the control/stat us word code field for that mb. this is because polling the c ontrol/status word may lock the mb (see above), and the code may change before the full frame is received into the mb. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 flexcan 25-10 freescale semiconductor note that the received identifier field is always stored in the matc hing mb, thus the contents of the identifier field in a mb may cha nge if the match was due to mask. 25.4.2.1 self-received frames the flexcan receives self-transmitted frames if there exists a matching receive mb. 25.4.3 message buffer handling to maintain data coherency a nd proper flexcan operation, the cpu must obey the rules listed in section 25.4.1, ?transmit process ? and in section 25.4.2, ?receive process .? deactivation of a message buffer (mb) is a host action that causes that messag e buffer to be excluded fr om flexcan transmit or receive processes. any cpu write access to a c ontrol/status word of mb st ructure deactivates that mb, thus excluding it from rx/tx proces ses. any form of cpu mb struct ure access within the flexcan (other than those specified in section 25.4.1, ?transmit process ? and in section 25.4.2, ?receive process ?) may cause the flexcan to behave in an unpredictable manner. the match/arbitration pr ocesses are performed only during one period by the flexcan. once a winner or match is determined, there is no re-e valuation whatsoever, in order to ensure that a receive frame is not lost. two receive mbs or more that hold a matching id to a received fr ame do not assure reception in the flexcan if the user has deactivated the matc hing mb after flexcan has scanned the second. 25.4.3.1 serial message buffers (smbs) to allow double buffering of mess ages, the flexcan has two shadow buffers called serial message buffers. these two buffers are used by the flexcan for buffering both received messages and messages to be transmitted. only one smb is active at a time, and its functi on depends upon the operation of the flexcan at that time. at no time does the user ha ve access to or visibility of these two buffers. 25.4.3.2 transmit message buffer deactivation any write access to the control/status word of a transmit message buffe r during the process of selecting a message buffer for transmission immediately deactivat es that message buffer, removing it from the transmission process. if the user deactivates the transmit mb while a messag e is being transferred from a transmit message buffer to a smb the message will not be transmitted. if the user deactivates the transmit message buffer af ter the message is transferred to the smb, the message will be transmitted, but no interr upt will be requested and the tr ansmit code will not be updated. if a message buffer containing the lowest id is deactivated while th at message is undergoing the internal arbitration process to determine which message should be sent, then th at message may not be transmitted. 25.4.3.3 receive message buffer deactivation any write access to the cont rol/status word of a receive message buffer during the proc ess of selecting a message buffer for reception immediatel y deactivates that messa ge buffer, removing it from the reception process. if a receive message buffer is deactivat ed while a message is be ing transferred into it, the transfer is halted and no interrupt is requeste d. if this occurs, that receive message buffer may contain mixed data from two different frames. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 flexcan freescale semiconductor 25-11 data should never be written into a receive message buffer. if this is done whil e a message is being transferred from an smb, the control/status word will reflect a full or over run condition, but no interrupt will be requested. 25.4.3.4 locking and releasing message buffers the lock/release/busy mechanism is de signed to guarantee data coherenc y during the receive process. the following examples demonstrate how the lock/release/busy mechanism will affect flexcan operation. 1. reading a control/status word of a message buffe r triggers a lock for that message buffer. a new received message frame which matc hes the message buffer cannot be written into this message buffer while it is locked. 2. to release a locked message buffer, the cpu ei ther locks another message buffer (by reading its control/status word) or globally releases any locked message buff er (by reading the free-running timer). 3. if a receive frame with a matchi ng id is received during the time the message buffer is locked, the receive frame will not be immediat ely transferred into that message buffer, but will remain in the smb. there is no indication when this occurs. 4. when a locked message buffer is released, if a fr ame with a matching identifier exists within the smb, then this frame will be transferred to the matching message buffer. 5. if two or more receive frames with matchi ng ids are received while a message buffer with a matching id is locked, the last received frame with that id is kept within the serial message buffer, while all preceding ones are lost. th ere is no indication when this occurs. 6. if the user reads the control/ status word of a receive messag e buffer while a frame is being transferred from a serial message buffer, the bu sy code will be indicate d. the user should wait until this code is cleared before continuing to read from the message buffer to ensure data coherency. in this situation, the read of the cont rol/status word will not lock the message buffer. polling the control/status word of a receive message buffer can lock it, preventing a message from being transferred into that buffer. if the control/status word of a receive mess age buffer is read, it should then be followed by a read of the control/status word of another buffer, or by reading the free-running timer, to ensure that the locked buffer is unlocked. 25.4.4 remote frames the remote frame is a message frame which is transm itted to request a data frame. the flexcan can be configured to transmit a data frame automatically in response to a remo te frame, or to transmit a remote frame and then wait for the responding data frame to be received. when transmitting a remote frame, the user initiali zes a message buffer as a transmit message buffer with the rtr bit set to one. once this remote frame is transmitted successf ully, the transmit message buffer automatically becomes a receive message buffer, with the same id as the remote frame which was transmitted. when a remote frame is received by the flexcan, the remote frame id is comp ared to the ids of all transmit message buffers programmed with a code of 1010. if there is an exact matching id, the data frame in that message buffer is transmitted. if the rtr bit in the matching transmit me ssage buffer is set, the flexcan will transmit a remote frame as a response. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 flexcan 25-12 freescale semiconductor a received remote fram e is not stored in a receive message buffer. it is only us ed to trigger the automatic transmission of a frame in response. the mask regist ers are not used in remote frame id matching. all id bits (except rtr) of the incoming received frame mu st match for the remote fr ame to trigger a response transmission. 25.4.5 overload frames overload frame transmissions are not initiated by the flexcan unless certain conditions are detected on the can bus. these conditions include: ? detection of a dominant bit in the first or second bit of intermission. ? detection of a dominant bit in th e seventh (last) bit of the end- of-frame (eof) field in receive frames. ? detection of a dominant bit in the eighth (last) bit of the error frame de limiter or overload frame delimiter. 25.4.6 time stamp the value of the free-runni ng 16-bit timer is sampled at the begi nning of the identifier field on the can bus. for a message being received, the time stamp will be stored in th e time stamp entry of the receive message buffer at the time the message is written into that buffer. for a message being transmitted, the time stamp entry will be written into the transmit message buffer on ce the transmission has completed successfully. the free-running timer can optionally be reset upon the reception of a frame into message buffer 0. this feature allows network time synchronization to be performed. 25.4.7 listen-only mode in listen-only mode, the flexcan m odule is able to receiv e messages without gi ving an acknowledgment. whenever the module enters this mode the status of the error counters is fro zen and the flexcan module operates like in error passive mode . since the module does not influenc e the can bus in this mode the host device is capable of functioning like a monitor or fo r automatic bit-rate detection. 25.4.8 bit timing the flexcan module uses three 8-bi t registers to set up the bit timing parameters required by the can protocol. control registers 1 and 2 (canctrl1, canctrl2) cont ain the propseg, pseg1, pseg2, and the rjw fields which allow the user to confi gure the bit timing paramete rs. the prescaler divide register (presdiv) allows the user to select the ra tio used to derive the s- clock from the system clock. the time quanta clock operates at the s-clock frequency. table 25-7 provides examples of system clock, can bit rate, and s-clock bit timing parameters. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 flexcan freescale semiconductor 25-13 25.4.8.1 configuring the flexcan bit timing the following considerations must be observed when programming bit timing functions. ? if the programmed presdiv value results in a single system clock per one time quantum, then the pseg2 field in canctrl1 register should not be programmed to zero. ? if the programmed presdiv value results in a single system clock per one time quantum, then the information processing time (ipt) equals three ti me quanta, otherwise it equals two time quanta. if pseg2 equals two, then the flexcan transmits one time quantum late relative to the scheduled sync segment. ? if the prescaler and bit timing control fields are pr ogrammed to values that result in fewer than ten system clock periods per can bit time and the can bus loading is 100%, anytim e the rising edge of a start-of-frame (sof) symbol transmitted by another node occu rs during the third bit of the intermission between messages, the flexcan may not be able to prepare a message buffer for transmission in time to begi n its own transmission and arbitrate against the message which transmitted the early sof. ? the flexcan bit time must be pr ogrammed to be greater than or e qual to nine system clocks, or correct operation is not guaranteed. 25.4.9 flexcan error counters there are two error counter s in the flexcan: transmit error count er (txectr), and re ceive error counter (rxctr). the rules for increasing and decreasing these counters are de scribed in the can protocol, and are fully implemented in the flexcan. each counter comprises the following: ? 8 bit up/down counter ? increment by 8 (rx_err_counter also by 1) ? decrement by 1 ? avoid decrement when equal to zero ? rx_err_counter preset to a value 119 x 127 ? value after reset = zero ? detect values for error passive, bus off and er ror active transitions and for alerting the host. both counters are read only (excep t for test/freeze/halt modes). table 25-7. examples of system clock/can bit-rate/s-clock system clock freq (mhz) can bit-rate (mhz) possible s-clock freq (mhz) possible number of time-quanta/bit pre-scaler programed value + 1 comments 48 1 8,12,24 8,12,24 3,2,1 min 8 time-quanta max 25 time-quanta 40 1 10,20 10,20 2,1 32 1 8,16 8,16 2,1 48 0.125 1,1.5,2,3 8,12,16,24 24,16,12,8 40 0.125 1,2,2.5 8,16,20 20,10,8 32 0.125 1,2 8,16 16,8 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 flexcan 25-14 freescale semiconductor the flexcan responds to any bus stat e as described in the protocol, e.g. transmit error active or error passive flag, delay it s transmission start time (err or passive) and avoid any influence on the bus when in bus off state. the following are the basi c rules for flexcan bus state transitions: ? if the value of txctr or rxctr in creases to be greater than or equal to 128, the fcs field in the error status register is updated to re flect it (set error passive state). ? if the flexcan state is error passive, and either txctr counter or rxctr then decrements to a value less than or equal to 127 while the other already satisfies this condition, the estat[fcs] field is updated to reflect it (set error active state). ? if the value of the txctr increases to be great er than 255, the estat[fcs] field is updated to reflect it (set bus off state) and an interrupt ma y be issued. the value of txctr is then reset to zero. ? if the flexcan state is bus_off, then txctr, toge ther with an internal counter are cascaded to count the 128 occurrences of 11 c onsecutive recessive bits on the bus. hence, txctr is reset to zero, and counts in a manner where the internal c ounter counts 11 such bits and then wraps around while incrementing the txctr. when txctr r eaches the value of 128, estat[fcs] is updated to be error active, and both error counters are reset to zero. at any instance of dominant bit following a stream of less than 11 consecutive r ecessive bits, the internal counter resets itself to zero, but does not affect the txctr value. ? if during system start-up, only one node is operating, then its txct r increases with each message it?s trying to transmit as a result of ack_erro r. a transition to bus st ate error passive should be executed as described, while this de vice never enters the bus_off state. ? if the rxctr increases to a value greater than 127, it is no longer incremented, ev en if more errors are detected while being a receiver. at the next successful me ssage reception, the counter is set to a value between 119 and 127, in order to return to error active state. 25.4.10 flexcan initialization sequence initialization of the flexcan include s the initial configuration of the message buffers and configuration of the can communication parameters following a reset, as well as any reconfigurat ion which may be required during operation. the following is a ge neric initialization sequence for the flexcan: 1. initialize all operation modes a) initialize the transmit and receive pin modes in control register 0 (canctrl0). b) initialize the bit timing paramete rs propseg, psegs1, pseg2, and rjw in control registers 1 and 2 (canctrl[1:2]). c) select the s-clock rate by pr ogramming the presdiv register. d) select the internal arbitrati on mode (lbuf bit in canctrl1). 2. initialize message buffers a) the control/status word of all me ssage buffers must be written ei ther as an active or inactive message buffer. b) all other entries in each message buffer should be initia lized as required. 3. initialize mask registers for acceptance mask as needed 4. initialize flexcan interrupt handler a) initialize the interrupt configuration register (icr n) with a specific request level and vector base address. b) set the required mask bits in the imask register (for all message buffer interrupts), in canctrl0 (for bus off and error interrupts) , and in canmcr for the wake interrupt. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 flexcan freescale semiconductor 25-15 5. negate the halt bit in th e module configuration register a) at this point, the flexcan will at tempt to synchronize with the can bus. note in both the transmit and receive processes, the fi rst action in preparing a message buffer should be to deactivate the buffer by setting its code field to the proper value. this requirement is mandatory to assure data coherency. 25.4.11 special operating modes 25.4.11.1 debug mode debug mode is entered by setting the halt bit in the canmcr, or by assertion of the bkpt line. in both cases, the frz bit in canmcr must al so be set to allow halt or bkpt to place the flexcan in debug mode. once entry into debug mode is reque sted, the flexcan waits until an in termission or idle condition exists on the can bus, or until the flexcan enters the erro r passive or bus off stat e. once one of these conditions exists, the flexcan waits for the completion of all internal activity . when this happens, the following events occur: ? the flexcan stops tran smitting/receiving frames. ? the prescaler is disabled, thus halting all can bus communication. ? the flexcan ignores its rx pins an d drives its tx pins as recessive. ? the flexcan loses synchronization with the can bus and the notrdy and frzack bits in canmcr are set. ? the cpu is allowed to read and write the error counter registers. after engaging one of the mechanisms to place the flexcan in debug m ode, the user must wait for the frzack bit to be set before ac cessing any other registers in the flexcan, otherwise unpredictable operation may occur. to exit debug mode, the bkpt line must be negated or the halt bit in canmcr must be cleared. once debug mode is exited, the flexcan will resynchronize with the can bus by waiting for 11 consecutive recessive bits before beginni ng to participate in can bus communication. 25.4.11.2 low-power stop mode for power saving before entering low-power stop mode, the flexcan will wait for the can bus to be in an idle state, or for the third bit of intermission to be recessive. the flexcan then wait s for the completion of all internal activity (except in the can bus interface) to be complete. afterwards, the following events occur: ? the flexcan shuts down its clocks, stopping most internal circuits, thus achieving maximum power savings. ? the bus interface unit continues to operate, allowing the cpu to access the module configuration register. ? the flexcan ignores its rx pins an d drives its tx pins as recessive. ? the flexcan loses synchroniza tion with the can bus, and the stopack and notrdy bits in the module configuration register are set. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 flexcan 25-16 freescale semiconductor to exit low-power stop mode: ? reset the flexcan either by asserting rsti or by setting the softrst bit canmcr. ? clear the stop bit in canmcr. ? the flexcan module can optionally exit low-power stop mode via the self-wake mechanism. if the selfwake bit in canmcr was set at the time the flex can entered stop mode, then upon detection of a recessive to dom inant transition on the can bus, the flexcan clears the stop bit in canmcr and its clocks begin running. when in low-power stop mode, a recessive to domin ant transition on the can bus causes the wakeint bit in the error and status register (estat) to be set. this event can ge nerate an interrupt if the wakemsk bit in canmcr is set. consider the following notes re garding low-power stop mode: ? when the self-wake mechanism activates, the flexcan tries to rece ive the frame that woke it up. (it assumes that the dominant bit de tected is a start-of-frame bit). it will not arbitrate for the can bus at this time. ? the cpu should disable all interrupts in the flexcan before enteri ng low-power stop mode. otherwise it may be interrupted while in stop mode upon a non wake-up condition; if desired, the wakemask bit should be set to enable the wakeint. ? if the stop bit is set while the flexcan is in the bus off state, then the flexcan will enter low-power stop mode and stop counting recessive bi t times. the count will continue when stop is cleared. ? to place the flexcan in low-power stop mode w ith the self-wake mechanism engaged, write to canmcr with both stop and selfwake set, th en wait for the flexca n to set the stopack bit. ? to take the flexcan out of low-power stop mode when the self-wake mechanism is enabled, write to canmcr with both stop and selfwake clear , then wait for the flexcan to clear the stopack bit. ? the selfwake bit should not be set after the flexcan has already entered low-power stop mode. ? if both stop and selfwake are set and a recessi ve to dominant edge immediately occurs on the can bus, the flexcan may never set the stopac k bit, and the stop bit will be cleared. ? to prevent old frames from being sent when th e flexcan awakes from low-power stop mode via the self-wake mechanism, disable all transmit s ources, including transmit buffers configured for remote request responses, before placing the flexcan in low-power stop mode. ? if the flexcan is in debug mode when the stop bit is set, the flexcan will assume that debug mode should be exited. as a result, it will try to synchronize wi th the can bus, and only then will it await the conditions required fo r entry into low-power stop mode. ? unlike other modules, the flexca n does not come out of reset in low-power stop mode. the basic flexcan initialization procedure (see section 25.4.10, ?flexcan in itialization sequence ?) should be executed before placing the module in low-power stop mode. ? if the flexcan is in low-power stop mode with the self-wake me chanism engaged and is operating with a single system clock per time quantum, there can be extreme cases in which flexcan wake-up on recessive to dominant edge may not conform to the can protocol. flexcan synchronization will be shifted one time quantum from the wake-up ev ent. this shift lasts until the next recessive to dominant edge, which resynchr onizes the flexcan to be in conformance with the can protocol. the same holds true when th e flexcan is in auto-power save mode and awakens on a recessive to dominant edge. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 flexcan freescale semiconductor 25-17 25.4.11.3 auto-power save mode auto-power save mode enables normal operation with optimized pow er savings. once the auto-power save (aps) bit in canmcr is set, th e flexcan looks for a set of conditi ons in which there is no need for its clocks to be running. if these conditions are met, the flexcan stops its clocks, thus saving power. the following conditions will activ ate auto-power save mode. ? no rx/tx frame in progress. ? no transfer of rx/tx frames to and from an smb, and no tx frame awaiting transmission in any message buffer. ? no cpu access to the flexcan module. ? the flexcan is not in debug mode, low- power stop mode, or the bus off state. while its clocks are stopped, if th e flexcan senses that any one of the aforementioned conditions is no longer true, it restarts its clocks. the flexcan then conti nues to monitor these conditions and stops/restarts its clocks accordingly. 25.4.12 interrupts the module can generate up to 19 inte rrupt sources (16 interrupts due to message buffers and 3 interrupts due to bus-off, error and wake-up). each one of the message buffers can be an interrupt source, if its corresponding imask bit is set. there is no distinction betw een tx and rx interrupts fo r a particular buffer, unde r the assumption that the buffer is initialized for either tr ansmission or reception, and thus its interrupt routine can be fixed at compilation time. each of the buffers is assigned a bit in the iflag register. the bit is set when the corresponding buffer completes a suc cessful transmission or reception, and cleared when the cpu reads the interrupt flag register (iflag) while the associated bit is set, and then writes it back as ?1? (and no new event of the same type occurs betw een the read and the write actions). the other 3 interrupt sources (bus-off, error and wake-up) act in the same way, and are located in the error & status register. the bus-off and error interrupt mask bits are locat ed in the canctrl0 register, and the wake-up interrupt mask bit is located in the canmcr. 25.5 programmer?s model this section describes the regi sters in the flexcan module. note the flexcan has no hard-wired prot ection against invalid bit/field programming within its regi sters. specifically, no protection is provided if the programming does not meet can protocol requirements. programming the flexcan control regi sters is typically done during system initialization, prior to the flexcan becoming synchronized with the can bus. the configuration registers can be changed after synchronization by halting the flexcan module. this is done when the user sets the halt bit in the flexcan module configuration register (canmcr). the flexcan responds by setting the canmcr[notrdy] bit. additionall y, the control regist ers can be modified while the mcu is in background debug mode. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 flexcan 25-18 freescale semiconductor 25.5.1 can module configur ation register (canmcr) table 25-8 describes the canmcr fields. 15 14 13 12 11 10 9 8 field stop frz ? halt notrdy wakemsk softrst frzack reset 0101_1001 r/w r/w 76543 0 field supv selfwake aps stopack ? reset 1000_0000 r/w r/w address ipsbar + 0x1c_0000 figure 25-6. can module conf iguration register (canmcr) table 25-8. canmcr field descriptions bits name description 15 stop low-power stop mode enable. the stop bit may on ly be set by the cpu. it may be cleared either by the cpu or by the flexcan, if the selfwake bit is set. 0 enable flexcan clocks 1 disable flexcan clocks 14 frz freeze assertion response. when frz = 1, the flexcan can enter debug mode when the bkpt line is asserted or the halt bit is set. clearing this bit field causes the flexcan to exit debug mode. refer to section 25.4.11.1, ?debug mode ? for more information. 0 flexcan ignores the bkpt signal and the halt bit in the module configuration register. 1 flexcan module enabled to enter debug mode. 13 ? reserved 12 halt halt flexcan s-clock. setting the halt bit ha s the same effect as assertion of the bkpt signal on the flexcan without requiring that bkpt be asserted. this bit is set to one after reset. it should be cleared after initializing the message buffers and control registers. flexcan message buffer receive and transmit functions are inactive until this bit is cleared. when halt is set, write access to certain registers and bits that are normally read-only is allowed. 0 the flexcan operates normally 1 flexcan enters debug mode if frz = 1 11 notrdy flexcan not ready. this bit indica tes that the flexcan is either in low-power stop mode or debug mode. this bit is read-only and is set only when the flexcan enters low-power stop mode or debug mode. it is cleared once the flexcan exits either mode, either by synchronization to the can bus or by the self-wake mechanism. 0 flexcan has exited low-power stop mode or debug mode. 1 flexcan is in low-power stop mode or debug mode. 10 wakems k wakeup interrupt mask. the wakemsk bit enables wake-up interrupt requests. 0 wake up interrupt is disabled. 1 wake up interrupt is enabled. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 flexcan freescale semiconductor 25-19 9softrst soft reset. when this bit is asse rted, the flexcan resets its inte rnal state machines (sequencer, error counters, error flags, and timer) and the host interface register s (canmcr, canicr, cantcr, imask, and iflag). the configuration registers that control the interface with the can bus are not changed (can- ctrl[0:2] and presdiv). message buffers and receive message masks are also not changed. this allows softrst to be used as a debug feature while the system is running. setting softrst also clear s the stop bit in canmcr. after setting softrst, allow one complete bus cycle to elapse for the internal flexcan circuitry to completely reset before exec uting another access to canmcr. the flexcan clears this bit once t he internal reset cycle is completed. 0 soft reset cycle completed 1 soft reset cycle initiated 8frzack flexcan disable. when the flexcan enters debug m ode, it sets the frzack bit. this bit should be polled to determine if the flexcan has enter ed debug mode. when debug mode is exited, this bit is negated once the flexcan prescale r is enabled. this is a read-only bit. 0 the flexcan has exited debug mode and the prescaler is enabled. 1 the flexcan has entered debug mode, and the prescaler is disabled. 7supv supervisor/user data space. the supv bit places th e flexcan registers in either supervisor or user data space. 0 registers with access controlled by the supv bit ar e accessible in either user or supervisor privilege mode. 1 registers with access controlled by the supv bit are restricted to supervisor mode. 6 self- wake self wake enable. this bit allows the flexcan to wake up when bus activi ty is detected after the stop bit is set. if this bit is set when the fl excan enters low-power stop mode, the flexcan will monitor the bus for a recessive to dominant transition. if a recessive to dominant transition is detected, the flexcan imm ediately clears the stop bi t and restarts its clocks. if a write to canmcr with selfwake set occurs at the same time a rece ssive-to-dominant edge appears on the can bus, the bit will not be se t, and the module clocks will not stop. the user should verify that this bit has been set by reading canmcr. refer to section 25.4.11.2, ?low-power stop mode for power saving ? for more information on entry into and exit from low-power stop mode. 0 self wake disabled. 1 self wake enabled. 5 aps auto-power save. the aps bit allows the flexcan to automatically shut off its clocks to save power when it has no process to ex ecute, and to aut omatically restart these clocks when it has a task to execute without any cpu intervention. 0 auto-power save mode disabled; clocks run normally. 1 auto-power save mode enabled; clocks stop and restart as needed. 4 stopack stop acknowledge. when the flexcan is placed in low-power stop mode and shuts down its clocks, it sets the sto pack bit. this bit should be polled to determine if the flexcan has entered low-power stop mode. when the flexcan exits low-power stop mode, the stopack bit is cleared once the flexca n?s clocks are running. 0 the flexcan is not in low-power stop mode and its clocks are running. 1 the flexcan has entered low-power st op mode and its clocks are stopped 3?0 ? reserved, should be cleared. table 25-8. canmcr field descriptions (continued) bits name description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 flexcan 25-20 freescale semiconductor 25.5.2 flexcan control register 0 (canctrl0) table 25-9 describes the canctrl0 fields. 76543210 field boffmsk errmsk ? rxmode txmode reset 0000_0000 r/w r/w address ipsbar + 0x1c_0006 figure 25-7. flexcan cont rol register 0 (canctrl0) table 25-9. canctrl0 field descriptions bits name description 7 boffm- sk bus off interrupt mask. the boff mask bit provides a mask for the bus off interrupt. 0 bus off interrupt disabled. 1 bus off interrupt enabled. 6 errmsk error interrupt mask. the errmsk bit pr ovides a mask for the error interrupt. 0 error interrupt disabled. 1 error interrupt enabled. 5?3 ? reserved 2rxmode receive pin configuration control. this bi t determines the polarity of the canrx pin. 0 a logical ?0? is interpreted as a dominant bit; a logical ?1? is interpreted as a recessive bit. 1 a logical ?1? is interpreted as a dominant bit; a logical ?0? is interpreted as a recessive bit. 1?0 txmode transmit pin configuration control. this bit field controls the configuration of the cantx pin. see table 25-10 . table 25-10. transmit pin configuration txmode[1:0] transmit pin configuration 00 full cmos 1 ; positive polarity (cantx= 0 is a dominant level) 1 full cmos drive indicates that both dominant and recessive levels are driven by the chip. 01 full cmos 1 ; negative polarity (cantx = 1 is a dominant level) 1x open drain 2 ; positive polarity 2 open drain drive indicates that only a dominant level is driven by the chip. during a recessive level, the cantx pin is disabled (t hree stated), and the electrical level is achieved by external pull-up/pull-down devices. the assertion of both tx mode bits causes the polarity inversion to be cancelled (open drain mode forces the polarity to be positive). mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 flexcan freescale semiconductor 25-21 25.5.3 flexcan control register 1 (canctrl1) table 25-11 describes the canctrl1 fields. 76543210 field samp ? tsync lbuf lom propseg reset 0000_0000 r/w r/w address ipsbar + 0x1c_0007 figure 25-8. flexcan cont rol register 1 (canctrl1) table 25-11. canctrl1 field descriptions bits name description 7 samp sampling mode. the samp bit determines whether the flexcan module will sample each received bit one time or three times to determine its value. 0 one sample, taken at the end of phase buffer segm ent 1, is used to dete rmine the value of the received bit. 1 three samples are used to determine the value of the received bit. the samples are taken at the normal sample point and at the two preceding periods of the s-clock. 6 ? reserved, should be cleared. 5 tsync timer synchronize mode. the tsync bit enables th e mechanism that resets the free-running timer each time a message is received in message buffer 0. this feature provides the means to synchro- nize multiple flexcan stations with a spec ial ?sync? message (global network time). 0 timer synchronization disabled. 1 timer synchronization enabled. note: there can be a bit clock skew of four to five counts between different flexcan modules that are using this feature on the same network. 4lbuf lowest buffer transmitted first. the lb uf bit defines the transmit-first scheme. 0 message buffer with lowest id is transmitted first. 1 lowest numbered buffer is transmitted first. 3lom listen only mode. in this mode the flexcan is able to receive messages without giving an acknowledgment or being active on the bus. 0 regular operation (listen only mode off). 1 enable listen only mode. 2?0 propse g propagation segment time. propseg defines the le ngth of the propagation segment in the bit time. the valid programmed values are 0 to 7. the propagation segment ti me is calculated as follows: propagation segment time = (p ropseg + 1) time quanta where 1 time quantum = 1 seri al clock (s-clock) period mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 flexcan 25-22 freescale semiconductor 25.5.4 prescaler divide register (presdiv) table 25-12 describes the presdiv fields. 25.5.5 flexcan control register 2 (canctrl2) table 25-13 describes the canctrl2 fields. 7 0 field pres_div reset 0000_0000 r/w r/w address ipsbar + 0x1c_0008 figure 25-9. prescaler divide register (presdiv) table 25-12. presdiv field descriptions bits name description 7?0 pres_div prescaler divide factor. presdiv determin es the ratio between the system clock frequency and the serial clock (s-clock). the s-clock is determined by the following calculation: the reset value of presdiv is 0x00, which forces the s-clock to default to the same frequency as the system clock. the valid progra mmed values are 0 through 255. see section 25.4.8, ?bit timing ? for more information. 765 32 0 field rjw pseg1 pseg2 reset 0000_0000 r/w r/w address ipsbar + 0x1c_0009 figure 25-10. flexcan control register 2 (canctrl2) table 25-13. canctrl2 field descriptions bits name description 7?6 rjw resynchronization jump width. the rjw field defi nes the maximum number of time quanta a bit time may be changed during resynchronization. the valid programmed values are 0 through 3. the resynchronization jump width is calculated as follows: resynchronizaton jump width = (rjw + 1) time quanta s-clock f sys 2 presdiv + 1 () -------------------------------------------- - = mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 flexcan freescale semiconductor 25-23 25.5.6 free running timer (timer) table 25-14 describes the timer fields. 25.5.7 rx mask registers these registers are used as acceptance masks for recei ved frame ids. 3 masks ar e defined: a global mask, used for rx buffers 0-13, and 2 more separate masks for buffers 14 and 15. mask bit = 0: the corresponding incoming id bit is ?don?t care?. mask bit = 1: the corresponding id bit is checked agai nst the incoming id bit, to see if a match exists. note that these masks are used both for standard and extended id formats. the value of mask registers should not be changed while in nor mal operation, as locked frames wh ich matched a mb through a mask, may be transferred into the mb ( upon release) but may no longer match. 5?3 pseg 1 pseg1[2:0] ? phase buffer segment 1. the pseg1 fi eld defines the length of phase buffer segment 1 in the bit time. the valid programmed values are 0 through 7. the length of phase buffer segment 1 is calculated as follows: phase buffer segment 1 = (pseg1 + 1) time quanta 2?0 pseg 2 pseg2 ? phase buffer segment 2. the pseg2 field defines the length of phase buffer segment 2 in the bit time. the valid programmed values are 0 through 7. the length of phase buffer segment 2 is calculated as follows: phase buffer segment 2 = (pseg2 + 1) time quanta 15 0 field timer reset 0000_0000_0000_0000 r/w r/w address ipsbar + 0x1c_000a figure 25-11. free running timer (timer) table 25-14. timer field descriptions bits name description 15?0 timer the free running timer counter can be read and wr itten by the cpu. the timer starts from zero after reset, counts linearly to 0xffff, and wraps around. the timer is clocked by the flexcan bit-clock. du ring a message, it increments by one for each bit that is received or transmitted. when there is no message on the bus, it increments at the nominal bit rate. the timer value is captured at the beginning of the identifier field of any frame on the can bus. the captured value is written into the ?time stamp? entry in a message buffer after a successful reception or transmission of a message. table 25-13. canctrl2 field descriptions (continued) bits name description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 flexcan 25-24 freescale semiconductor 25.5.7.1 receive mask registers (rxgmask, rx14mask, rx15mask) the rx global mask regi ster (rxgmask) is composed of 4 bytes . the mask bits are applied to all rx-identifiers excluding rx-buffers 14-15, that have their specific rx-mask registers (rx14mask and rx15mask). table 25-15. mask examples for normal/extended messages base id id28.................id18 i d e extended id id17......................................id0 match mb2-id 1 1 1 1 1 1 1 1 0 0 0 0 mb3-id 1 1 1 1 1 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 mb4-id 0 0 0 0 0 0 1 1 1 1 1 0 mb5-id 0 0 0 0 0 0 1 1 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 mb14-id 1 1 1 1 1 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 rx_global_mas k 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 rx_msg in 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 3 1 1 match for extended format (mb3). rx_msg in 1 1 1 1 1 1 1 1 0 0 1 0 2 2 2 match for standard format. (mb2). rx_msg in 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 3 3 un-match for mb3 because of id0. rx_msg in 0 1 1 1 1 1 1 1 0 0 0 0 4 4 un-match for mb2 because of id28. rx_msg in 0 1 1 1 1 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 5 5 un-match for mb3 because of id28, match for mb14. rx_14_mask 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 rx_msg in 1 0 1 1 1 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 6 6 un-match for mb14 because of id27. rx_msg in 0 1 1 1 1 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 14 7 7 match for mb14. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 flexcan freescale semiconductor 25-25 25.5.8 flexcan error and st atus register (estat) estat reflects various error conditions, some general status of the device, and is the source of three interrupts to the host. the reported e rror conditions (bits 15:10) are those occurred since the last time the host read this register. the read action clears these bits to 0. all the bits in this register are read only, ex cept for boff_int, wake_int and err_int, which are interrupt sources and can be written by the host to ?1?. section 25.4.12, ?interrupts .? 31 21 20 19 18 17 16 field mid[28:18] ? mid[17:15] reset 1111_1111_1110_1111 r/w r/w 15 10 field mid[14:0] ? reset 1111_1111_1111_1110 r/w r/w address ipsbar + 0x1c_0010 (rxgmask), 0x1c_0014 (rx14mask), 0x1c_0018 (rx15mask) figure 25-12. rx mask registers (rxgmask, rx14mask, and rx15mask) table 25-16. rxgmask, rx14mask, and rx15mask field descriptions bits name description 31?21 mid mask id. mid[28:18] are used to mask standard or extended format frames. 0 corresponding incoming id bit is ?don?t care?. 1 corresponding id bit is checked against the incoming id bit, to see if a match exists. 20 ? reserved. the ide bit of a received frame is al ways compared. its location in the mask (bit 19) is always 1, regardless of any cpu write to this bit. 19 ? reserved. the rtr/srr bit of a received frame is never compared to the corresponding bit in the mb id field. note, however, that remote request frames (rtr = 1) are never received into mbs. rtr mask bits locations in the mask (bits 20 and 0) are always read as ?0?, regardless of any cpu write to these bits. 18?1 mid mask id. mid[17:0] are only used to mask extended format frames. 0 corresponding incoming id bit is ?don?t care?. 1 corresponding id bit is checked against the incoming id bit, to see if a match exists. 0 ? reserved. the rtr/srr bit of a received frame is never compared to the corresponding bit in the mb id field. note, however, that remote request frames (rtr = 1) are never received into mbs. rtr mask bits locations in the mask (bits 20 and 0) are always read as ?0?, regardless of any cpu write to these bits. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 flexcan 25-26 freescale semiconductor table 25-17 describes the estat fields. 15 14 13 12 11 10 9 8 field biterr ackerr crcerr formerr stufferr txwarn rxwarn reset 0000_0000 r/w r 76543210 field idle tx/rx fcs ? boffint errint wakeint reset 0000_0000 r/w r r/w address ipsbar + 0x1c_0020 figure 25-13. flexcan error and status register (estat) table 25-17. estat field descriptions bits name description 15?14 biterr transmit bit error. the biterr[1:0] field is used to indicate when a transmit bit error occurs. 00 no transmit bit error 01 at least one bit sent as dominant was received as recessive 10 at least one bit sent as recessive was received as dominant 11 reserved note: the transmit bit error field is not modified during the arbitration field or the ack slot bit time of a message, or by a transmitter t hat detects dominant bits while sending a passive error frame. 13 ackerr acknowledge error. the ackerr bit indicates whether an acknowledgment has been correctly received for a transmitted message. 0 no ack error was detected since the last read of this register. 1 an ack error was detected since t he last read of this register. 12 crcerr cyclic redundancy check error. the crcerr bit indicates whether or not the crc of the last transmitted or received message was valid. 0 no crc error was detected since the last read of this register. 1 a crc error was detected since the last read of this register. 11 formerr message format error. the formerr bit indicates whether or not the message format of the last transmitted or received message was correct. 0 no format error was detected since the last read of this register. 1 a format error was detected since the last read of this register. 10 stuferr bit stuff error. the stufferr bit indicate s whether or not the bit stuffing that occurred in the last transmitted or received message was correct. 0 no bit stuffing error was detected since the last read of this register. 1 a bit stuffing error was detected sinc e the last read of this register. 9 txwarn transmit error status flag. the txwarn st atus flag reflects the status of the flexcan transmit error counter. 0 transmit error counter < 96. 1 transmit error counter 96. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 flexcan freescale semiconductor 25-27 25.5.9 interrupt mask register (imask) imask contains one interrupt mask bit per buffer. it enables the cpu to determine which buffer will generate an interrupt after a succes sful transmission/reception (that is , when the corresponding iflag bit is set). 8 rxwarn receiver error status flag. the rxwarn st atus flag reflects the status of the flexcan receive error counter. 0 receive error counter < 96. 1 receive error counter 96. 7 idle idle status. the idle bit indicates when there is activity on the can bus. 0 the can bus is not idle. 1 the can bus is idle. 6 tx/rx transmit/receive status. the tx/rx bit indi cates when the flexcan module is transmitting or receiving a message. tx/rx has no meaning when idle = 1. 0 the flexcan is receiving a message if idle = 0. 1 the flexcan is transmitting a message if idle = 0. 5?4 fcs fault confinement state. the fcs[1:0] fi eld describes the state of the flexcan. if the softrst bit in canmcr is asserted while the flex can is in the bus off state, the error and status register is reset, including fcs[1:0]. however, as soon as the flexcan exits reset, fcs[1:0] bits will again reflect the bus off state. refer to section 25.5.11, ?flexcan receive error counter (rxectr) ? for more information on entry into and exit from the various fault confinement states. 00 error active 01 error passive 1x reserved 3 ? reserved, should be cleared. 2 boffint bus off interrupt. the boffint bit is used to request an interrupt when the flexcan enters the bus off state. to clear this bit, first read it as a one, then write a one. writing zero has no effect. 0 no bus off interrupt requested. 1 when the flexcan state changes to bus off, th is bit is set, and if the boffmsk bit in canctrl0 is set, an interrupt request is generated. this interrupt is not requested after reset. 1 errint error interrupt. the errint bit is used to request an interrupt when the flexcan detects a transmit or receive error. to clear this bit, first read it as a one, then write a one. writing zero has no effect. 0 no error interrupt request. 1 if an event which causes one of the error bits in the error and status register to be set occurs, the error interrupt bit is set. if the errmsk bit in canctrl0 is set, an interrupt request is generated. 0 wakeint wake interrupt. the wakei nt bit indicates that bus acti vity has been det ected while the flexcan module is in low-power stop mode. to clear this bit, first read it as a one, then write a one. writing zero has no effect. 0 no wake interrupt requested. 1 when the flexcan is in low-power stop mode and a recessive to dominant transition is detected on the can bus, th is bit is set. if the wakemsk bit is set in canmcr, an interrupt request is generated. table 25-17. estat field descriptions (continued) bits name description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 flexcan 25-28 freescale semiconductor the interrupt mask register contai ns two 8-bit fields: b its 15-8 (imask_h) and bi ts 7-0 (imask_l). the register can be accessed by the mast er as a 16-bit register, or each byt e can be accessed individually using an 8-bit (byte) access cycle. table 25-18 describes the imask fields. 25.5.10 interrupt flag register (iflag) iflag contains one interr upt flag bit per buffer. each succe ssful transmission/reception sets the corresponding iflag bit and, if the corresponding imask bit is set, will generate an interrupt. this register contains tw o 8-bit fields: bits 15-8 (i flag_h) and bits 7-0 (ifl ag_l). the register can be accessed by the master as a 16-bit re gister, or each byte can be accessed individually using an 8-bit (byte) access cycle. 15 14 13 12 11 10 9 8 field buf15m buf14m buf13m buf12 buf11m buf10m buf9m buf8m reset 0000_0000 r/w r/w 76543 0 field buf7m buf6m buf5m buf4m buf3m buf2m buf1m buf0m reset 0000_0000 r/w r/w address ipsbar + 0x1c_0022 figure 25-14. interrupt mask register (imask) table 25-18. imask field descriptions bits name description 15?0 buf n m imask contains one interrupt mask bit per buffer. it allows the cpu to designate which buffers will generate interrupts after succe ssful transmission/reception. 0 the interrupt for the corresponding buffer is disabled. 1 the interrupt for the corresponding buffer is enabled. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 flexcan freescale semiconductor 25-29 table 25-19 describes the iflag fields. 25.5.11 flexcan receive error counter (rxectr) table 25-20 describes the rxectr fields. 15 14 13 12 11 10 9 8 field buf15i buf14i buf13i buf1i buf11i buf10i buf9i buf8i reset 0000_0000 r/w r/w 76543 0 field buf7i buf6i buf5i buf4i buf3i buf2i buf1i buf0i reset 0000_0000 r/w r/w address ipsbar + 0x1c_0024 figure 25-15. interrupt flag register (iflag) table 25-19. iflag field descriptions bits name description 15?0 buf n i iflag contains one interrupt flag bit per buffer. each successful transmission/reception sets the corresponding iflag bit and, if the corresponding imask bit is set, an interrupt request will be generated. to clear an interrupt flag, first read the flag as a one, and then write it as a one. should a new flag setting event occur between the time that the cpu r eads the flag as a one and writes the flag as a zero, the flag is not cleared. this register can be written to zeros only. 0 the interrupt for the corresponding buffer is disabled. 1 the interrupt for the corresponding buffer is enabled. 7 0 field rxectr reset 0000_0000 r/w r address ipsbar + 0x1c_0026 figure 25-16. flexcan receive error counter (rxectr) table 25-20. rxectr field descriptions bits name description 7?0 rxect r receive error counter. indicates the current receive error count as defined in the can protocol. see section 25.4.9, ?flexcan error counters ? for more details. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 flexcan 25-30 freescale semiconductor 25.5.12 flexcan transmit error counter (txectr) table 25-21 describes the txectr fields. 7 0 field txectr reset 0000_0000 r/w r address ipsbar + 0x1c_0028 figure 25-17. flexcan transmit error counter (txectr) table 25-21. txectr field descriptions bits name description 7?0 txect r transmit error counter. indicates th e current transmit error count as defined in the can protocol. see section 25.4.9, ?fle xcan error counters ? for more details. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor 26-1 chapter 26 general purpose i/o module 26.1 introduction many of the pins associated with the external interf ace may be used for severa l different functions. their primary function is to provide an external memory interf ace to access off-chip resources. when not used for their primary function, many of the pins may be used as general-purpose digital i/o pins. in some cases, the pin function is set by the operating mode, a nd the alternate pin functions are not supported. the digital i/o pins are grouped into 8-bit ports. some ports do not use all eight bits. each port has registers that configure, monitor, and control the port pins. figure 26-1 and figure 26-2 are block diagrams of the ports for the mcf521 x and mcf528 x . mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose i/o module 26-2 freescale semiconductor 1. although ports nq, qa, qb, ta, and tb are not part of t he ports module, they are included here for comprehensiveness. figure 26-1. mcf5214 and mcf5216 ports module block diagram r/w / pe4 oe / pe7 siz0 / pe2 / syncb ta / pe6 tea / pe5 d[7:0] / pd[7:0] d[15:8] / pc[7:0] d[23:16] / pb[7:0] d[31:24] / pa[7:0] bs [3:0] / pj[7:4] cs [3:0] / pj[3:0] port e port d port c port b port a port j ts / pe1 / synca tip / pe0 / syncb a[7:0] / ph[7:0] a[15:8] / pg[7:0] a[23:21] / pf[7:5] / port h port g port f ddata[3:0] / pdd[7:4] pst[3:0] / pdd[3:0] pel[7] pel[6] pel[5] pel[4] pel[3] pel[2] pel[1] pel[0] pas5 / urxd2 pas4 / utxd2 canrx / pas3 / urxd2 cantx / pas2 / utxd2 sda / pas1 / urxd2 scl / pas0 / utxd2 qspi_clk / pqs2 qspi_din / pqs1 qspi_dout / pqs0 qspi_cs[3:0] / pqs[6:3] sras / psd5 scas / psd4 dramw / psd3 scke / psd0 sdram_cs[1:0] / dtin3 / ptc[3] / urts1 / urts0 dtin2 / ptc[1] / ucts1 / ucts0 dtout2 / ptc[0] / ucts1 / ucts0 dtin1 / ptd[3] / urts1 / urts0 dtout1 / ptd[2] / urts1 / urts0 dtin0 / ptd[1] / ucts1 / ucts0 dtout0 / ptd[0] / ucts1 / ucts0 urxd1 / pua[3] utxd1 / pua[2] urxd0 / pua[1] utxd0 / pua[0] a[20:16] / pf[4:0] siz1 / pe3 / synca port dd port el port qb 1 port qa 1 port nq 1 port as port tb 1 port ta 1 port sd port qs port tc port td port ua dtout3 / ptc[2] / urts1 / urts0 cs[6:4] psd[2:1] an3 / pqb3 / anz an2 / pqb2 / any an1 / pqb1 / anx an0 / pqb0 / anw an56 / pqa4 / etrig2 an55 / pqa3 / etrig1 an53 / pqa1 / ma1 an52 / pqa0 / ma0 irq[7:1] / pnq[7:1] gpta[3:0] / pta[3:0] gptb[3:0] / ptb[3:0] mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose i/o module freescale semiconductor 26-3 1. although ports nq, qa, qb, ta, and tb are not part of t he ports module, they are included here for comprehensiveness. figure 26-2. mcf5280, mcf5281, and mcf5282 ports module block diagram r/w / pe4 oe / pe7 siz0 / pe2 / syncb ta / pe6 tea / pe5 d[7:0] / pd[7:0] d[15:8] / pc[7:0] d[23:16] / pb[7:0] d[31:24] / pa[7:0] bs [3:0] / pj[7:4] cs [3:0] / pj[3:0] port e port d port c port b port a port j ts / pe1 / synca tip / pe0 / syncb a[7:0] / ph[7:0] a[15:8] / pg[7:0] a[23:21] / pf[7:5] / port h port g port f ddata[3:0] / pdd[7:4] pst[3:0] / pdd[3:0] etxclk / peh[7] etxen / peh[6] etxd[0] / peh[5] ecol / peh[4] erxclk / peh[3] erxdv / peh[2] erxd[0] / peh[1] ecrs / peh[0] etxd[3] / pel[7] etxd[2] / pel[6] etxd[1] / pel[5] etxer / pel[4] erxd[3] / pel[3] erxd[2] / pel[2] erxd[1] / pel[1] erxer / pel[0] emdio / pas5 / urxd2 emdc / pas4 / utxd2 canrx / pas3 / urxd2 cantx / pas2 / utxd2 sda / pas1 / urxd2 scl / pas0 / utxd2 qspi_clk / pqs2 qspi_din / pqs1 qspi_dout / pqs0 qspi_cs[3:0] / pqs[6:3] sras / psd5 scas / psd4 dramw / psd3 scke / psd0 sdram_cs[1:0] / dtin3 / ptc[3] / urts1 / urts0 dtin2 / ptc[1] / ucts1 / ucts0 dtout2 / ptc[0] / ucts1 / ucts0 dtin1 / ptd[3] / urts1 / urts0 dtout1 / ptd[2] / urts1 / urts0 dtin0 / ptd[1] / ucts1 / ucts0 dtout0 / ptd[0] / ucts1 / ucts0 urxd1 / pua[3] utxd1 / pua[2] urxd0 / pua[1] utxd0 / pua[0] a[20:16] / pf[4:0] siz1 / pe3 / synca port dd port eh port el port qb 1 port qa 1 port nq 1 port as port tb 1 port ta 1 port sd port qs port tc port td port ua dtout3 / ptc[2] / urts1 / urts0 cs[6:4] psd[2:1] an3 / pqb3 / anz an2 / pqb2 / any an1 / pqb1 / anx an0 / pqb0 / anw an56 / pqa4 / etrig2 an55 / pqa3 / etrig1 an53 / pqa1 / ma1 an52 / pqa0 / ma0 irq[7:1] / pnq[7:1] gpta[3:0] / pta[3:0] gptb[3:0] / ptb[3:0] mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose i/o module 26-4 freescale semiconductor 26.1.1 overview the ports module controls the configuration for various external pins, including those used for: ? external bus accesses ? chip selects ? debug data ? processor status ? ethernet data and control (not present on the mcf5214 and mcf5216) ? flexcan transmit/receive data ?i 2 c serial control ? qspi ? sdram control ? 32-bit dma timers ? uart transmit/receive 26.1.2 features the ports includes these distinctive features: ? control of primary function use on all ports ? digital i/o support for all ports ? registers for storing output pin data ? registers for controlling pin data direction ? registers for reading current pin state ? registers for setting and cleari ng output pin data registers 26.1.3 modes of operation the operational modes for the ports are listed below. fo r more detailed descriptions of each mode, refer to section 26.4, ?functional description .? ? single-chip mode all pins are configured as dig ital i/o by default, except for de bug data pins (ddata[3:0]) and processor status pins (pst[3:0]). ? master mode ports a and b function as the upper external data bus. ports c and d can function as the lower external data bus. ports e?j are conf igured to support external memory. 26.2 external signal description the ports control the functional ity of several external pins . these pins are listed in table 26-1 . mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose i/o module freescale semiconductor 26-5 table 26-1. ports external signals primary function (pin name) 1 gpio (default function) alternate function 1 alternate function 2 description d[31:0] 2 pa, pb, pc, pd ? ? external data bus / ports a, b, c, d oe 1 pe[7] ? ? output enable for external reads / port e[7] ta 1 pe[6] ? ? transfer acknowledge for external data transfer / port e[6] tea 1 pe[5] ? ? transfer error acknowledge for external data transfer / port e[5] r/w 1 pe[4] ? ? read/write indication for external data transfer / port e[4] siz1 1 pe[3] synca ? size of the external data transfer / port e[3] / timer a sync siz0 1 pe[2] syncb ? size of the external data transfer / port e[3:2] / timer b sync ts 1 pe[1] synca ? transfer start indication for external data transfer / port e[1] / timer a sync tip 1 pe[0] syncb ? transfer in progress indication for external data transfer / port e[0] / timer b sync a[23:21] 1 pf[7:5] cs [6:4] ? external address bus [23:21] / port f[7:5] / chip selects 6?4 a[20:0] 1 pf[4:0], pg, ph ? ? external address bus [20: 0] / ports f[4:0], g, h bs [3:0] 1 pj[7:4] ? ? byte strobes for external data transfer / port j[7:4] / sdram column address strobes cs [3:0] 1 pj[3:0] ? ? chip selects 3 - 0 / port j[3:0] ddata[3:0] pdd[7:4] ? ? de bug data / port dd[7:4] pst[3:0] pdd[7:4] ? ? processor status / port dd[3:0] canrx pas[3] urxd2 ? flexcan receive data / port as[3] / urxd2 cantx pas[2] utxd2 ? flexcan transmit data / port as[2] / utxd2 sda pas[1] urxd2 ? i 2 c serial data / port as[1] / urxd2 scl pas[0] utxd2 ? i 2 c serial clock / port as[0] / utxd2 irq[7:1] 3 pnq[7:1] ? ? edge port external interrupt pins / port nq[7:1] an[56:55:53:52] 2 pqa [4:3:1:0] etrig[2:1], ma[1:0] ? qadc analog inputs / port qa [4:3:1:0] / external triggers / external multiplex control an[3:0] 2 pqb[3:0] anz, any, anx, anw ? qadc analog inputs / port qb[3:0] / multiplexed analog inputs qspi_cs [3:0] pqs[6:3] ? ? qspi synchronous peripher al chip selects / port qs[3:6] qspi_clk pqs[2] ? ? qspi seri al clock / port qs[2] qspi_din pqs[1] ? ? qspi serial data input / port qs[1] qspi_dout pqs[0] ? ? qspi serial data output / port qs[0] sras psd[5] ? ? sdram synchronous row address strobe / port sd[5] mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose i/o module 26-6 freescale semiconductor scas psd[4] ? sdram synchronous column address strobe / port sd[4] dramw psd[3] ? ? sdram write enable / port sd[3] sdram_cs [1:0] psd[2:1] ? ? sdram row address strobes 1, 0 / port sd[2:1] scke psd[0] ? ? sdram clock enable / port sd[0] gpta[3:0] 2 pta[3:0] ? ? general purpose timer a input/output / port ta[3:0] gptb[3:0] 2 ptb[3:0] ? ? general purpose timer b input/output / port tb[3:0] dtin3 ptc[3] urts1 urts0 dma timer 3 input / port tc[3] / uart1 request to send / uart0 request to send dtout3 ptc[2] urts1 urts0 dma timer 3 output / port tc[2] / uart1 request to send / uart0 request to send dtin2 ptc[1] ucts1 ucts0 dma timer 2 input / port tc[1] / uart1 clear to send / uart0 clear to send dtout2 ptc[0] ucts1 ucts0 dma timer 2 output / port tc[0] / uart1 clear to send / uart0 clear to send dtin1 ptd[3] urts1 urts0 dma timer 1 input / port td[3] / uart1 request to send / uart0 request to send dtout1 ptd[2] urts1 urts0 dma timer 1 output / port td[2] / uart1 request to send / uart0 request to send dtin0 ptd[1] ucts1 ucts0 dma timer 0 input / port td[1] / uart1 clear to send / uart0 clear to send dtout0 ptd[0] ucts1 ucts0 dma timer 0 output / port td[0] / uart1 clear to send / uart0 clear to send urxd1 pua[3] ? ? uart1 receive serial data / port ua[3] utxd1 pua[2] ? ? uart1 transmit serial data / port ua[2] urxd0 pua[1] ? ? uart0 receive serial data / port ua[1] utxd0 pua[0] ? ? uart0 transmit serial data / port ua[0] the following signals apply to the mcf5280, mcf5281, and mcf5282 etxclk peh[7] ? ? ethernet transmit clock / peh[7] etxen peh[6] ? ? ethernet transmit enable / peh[6] etxd[0] peh[5] ? ? ethernet transmit data [0] / peh[5] ecol peh[4] ? ? ethernet collision / peh[4] erxclk peh[3] ? ? ethernet receive clock / peh[3] erxdv peh[2] ? ? ethernet receive data valid / peh[2] erxd[0] peh[1] ? ? ethernet receive data [0] / peh[1] table 26-1. ports external signals (continued) primary function (pin name) 1 gpio (default function) alternate function 1 alternate function 2 description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose i/o module freescale semiconductor 26-7 refer to chapter 14, ?signal descriptions ? for more detailed descriptions of these pins. the function of the pins (primary function, gpio, etc.) is determined by the various ports registers and the mode of operation. refer to table 14-1 for detailed descriptions of pin functions. 26.3 memory map/register definition 26.3.1 register overview table 26-2 summarizes all the registers in the ports address space. ecrs peh[0] ? ? ethernet carrier receive sense / peh[0] etxd[3:1] pel[7:5] ? ? ethernet transmit data / port el[7:5] etxer pel[4] ? ? ethernet transmit error / port el[4] erxd[3:1] pel[3:1] ? ? ethernet receive data [3:1] / port el[3:1] erxer pel[0] ? ? ethernet receive error / port el[0] emdio pas[5] urxd2 ? ethernet management data control / port as[5] / urxd2 emdc pas[4] utxd2 ? ethernet management data clock / port as[4] / utxd2 the following sign als apply to mcf5214 and mcf5216 only pel[0] ? ? ? port el[0] pas[4] utxd[2] ? ? port as[4] / utxd2 pel[7:5] ? ? ? port el[7:5] pel[4] ? ? ? port el[4] pel[3:1] ? ? ? port el[3:1] pas[5] urxd2 ? ? port as[5] / urxd2 1 the primary functionality of a pin is not necessarily the default function of the pin after reset. pins that have muxed gpio functionality will default to gpio inputs. 2 function available in master mode only 3 pins not actually part of port module, but included here for complete listing of available i/o ports. see separate section for description of this port. table 26-2. ports module memory map ipsbar + offset 31?24 23?16 15?8 7?0 access 1 port output data registers 0x10_0000 porta portb portc portd s/u 0x10_0004 porte portf portg porth s/u table 26-1. ports external signals (continued) primary function (pin name) 1 gpio (default function) alternate function 1 alternate function 2 description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose i/o module 26-8 freescale semiconductor 0x10_0008 portj portdd porteh (reserved on mcf521x) portel s/u 0x10_000c portas portqs portsd porttc s/u 0x10_0010 porttd portua reserved 2 s/u table 26-2. ports module memory map (continued) ipsbar + offset 31?24 23?16 15?8 7?0 access 1 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose i/o module freescale semiconductor 26-9 port data direction registers 0x10_0014 ddra ddrb ddrc ddrd s/u 0x10_0018 ddre ddrf ddrg ddrh s/u 0x10_001c ddrj ddrdd ddreh (reserved on mcf521x) ddrel s/u 0x10_0020 ddras ddrqs ddrsd ddrtc s/u 0x10_0024 ddrtd ddrua reserved 2 s/u port pin data/set data registers 0x10_0028 portap/seta portbp/setb portcp/setc portdp/setd s/u 0x10_002c portep/sete portfp/set f portgp/setg porthp/seth s/u 0x10_0030 portjp/setj portddp/setdd portehp/seteh (reserved on mcf521x) portelp/setel s/u 0x10_0034 portasp/setas portqsp/setqs portsdp/setsd porttcp/settc s/u 0x10_0038 porttdp/settd portuap/setua reserved 2 s/u port clear output data registers 0x10_003c clra clrb clrc clrd s/u 0x10_0040 clre clrf clrg clrh s/u 0x10_0044 clrj clrdd clreh (reserved on mcf521x) clrel s/u 0x10_0048 clras clrqs clrsd clrtc s/u 0x10_004c clrtd clrua reserved 2 s/u port pin assignment registers 0x10_0050 pbcdpar pfpar pepar s/u 0x10_0054 pjpar psdpar paspar s/u 0x10_0058 pehlpar pqspar ptcpar ptdpar s/u 0x10_005c puapar reserved 2 s/u 0x10_0060 ? 0x10_007c reserved 2 1 s/u = supervisor or user mode access. user mode accesses to supervisor-only addresses have no effect and cause a cycle termination transfer error. 2 writing to reserved address locations has no effect and reading returns 0s. table 26-2. ports module memory map (continued) ipsbar + offset 31?24 23?16 15?8 7?0 access 1 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose i/o module 26-10 freescale semiconductor 26.3.2 register descriptions 26.3.2.1 port output data registers (port n) the port n registers store the data to be driven on the corresponding port n pins when the pins are configured for digital output. most port n registers have a full 8-bi t implementation, as shown in figure 26-3 . the remaining port n registers use fewer than eight bits. their bit definitions are shown in figure 26-4 , figure 26-5 , and figure 26-6 . at reset, all bits in the port n registers are set. reading a port n register returns the current values in the register, not the port n pin values. port n bits can be set by setting the portn register, or by setting the corresponding bits in the port np/set n register. they can be cleared by clearing the port n register, or by clearing the corresponding bits in the clr n register. 76543210 field port n 7port n 6port n 5port n 4port n 3port n 2port n 1port n 0 reset 1111_1111 r/w: r/w address ipsbar + 0x10_0000 (porta), 0x10_0001 (por tb), 0x10_0002 (portc), 0x10_0003 (portd), 0x10_0004 (porte), 0x10_0005 (portf), 0x10_0006 (portg), 0x10_0007 (porth), 0x10_0008 (portj), 0x10_0009 (portdd), 0x10_000a (porteh), 0x10_000b (portel) figure 26-3. port output data registers (8-bit) 76543210 field ? port n 6port n 5port n 4port n 3port n 2port n 1port n 0 reset 0011_1111 r/w: r r/w address ipsbar + 0x10_000d (portqs) figure 26-4. port output data register (7-bit) 76543210 field ? port n 5port n 4port n 3port n 2port n 1port n 0 reset 0011_1111 r/w: r r/w address ipsbar + 0x10_000c (portas), 0x10_000e (portsd) figure 26-5. port output data registers (6-bit) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose i/o module freescale semiconductor 26-11 port n bits are described in table 26-3 . 26.3.2.2 port data direction registers (ddr n) the ddrs control the direction of the port n pin drivers when the pins are configured for digital i/o. most ddrs have a full 8-bi t implementation, as shown in figure 26-7 . the remaining ddrs use fewer than eight bits. their bit definitions are shown in figure 26-8 , figure 26-9 , and figure 26-10 . the ddrs are read/write. at reset, all bits in the ddrs are cleared. setting any bit in a ddr n register configures the corresponding port n pin as an output. clearing any bit in a ddr n register configures the corresponding pin as an input. 7 43210 field ? port n 3port n 2port n 1port n 0 reset 0000_1111 r/w: r r/w address ipsbar + 0x10_000f (porttc), 0x10_0010 (porttd), 0x10_0011 (portua) figure 26-6. port output data registers (4-bit) table 26-3. port n (8-bit, 7-bit, 6-bit, and 4-bit) field descriptions register bits name description 8-bit 7?0 port nx port output data bits. 1 drives 1 when the port n pin is a digital output 0 drives 0 when the port n pin is a digital output 7-bit 6?0 6-bit 5?0 4-bit 3?0 7-bit 7 ? reserved, should be cleared. 6-bit 7?6 4-bit 7?4 76543210 field ddr n 7ddr n 6ddr n 5ddr n 4ddr n 3ddr n 2ddr n 1ddr n 0 reset 0000_0000 r/w: r/w address ipsbar + 0x10_0014 (ddra), 0x10_0015 (ddrb), 0x10_0016 (ddrc), 0x10_0017 (ddrd), 0x10_0018 (ddre), 0x10_0019 (ddrf), 0x10_001a (ddrg), 0x10_001b (ddrh), 0x10_001c (ddrj), 0x10_001d (ddrdd), 0x10_001e (ddreh), 0x10_001f (ddrel) figure 26-7. port data direction registers (8-bit) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose i/o module 26-12 freescale semiconductor 76 0 field ? ddr n 6ddr n 5ddr n 4ddr n 3ddr n 2ddr n 1ddr n 0 reset 0000_0000 r/w: r r/w address ipsbar + 0x10_0021(ddrqs) figure 26-8. port data di rection register (7-bit) 76543210 field ? ddr n 5ddr n 4ddr n 3ddr n 2ddr n 1ddr n 0 reset 0000_0000 r/w: r r/w address ipsbar + 0x10_0020 (ddras), 0x10_0022 (ddrsd) figure 26-9. port data direction registers (6-bit) 7 43210 field ? ddr n 3ddr n 2ddr n 1ddr n 0 reset 0000_0000 r/w: r r/w address ipsbar + 0x10_0023 (ddrtc), 0x10_0024 (ddrtd), 0x10_0025 (ddrua) figure 26-10. port data direction registers (4-bit) table 26-4. ddr n (8-bit, 6-bit, and 4-bit) field descriptions register bits name description 8-bit 7?0 ddr nx port n data direction bits. 1port n pin configured as an output 0port n pin configured as an input 7-bit 6?0 6-bit 5?0 4-bit 3?0 7-bit 7 ? reserved, should be cleared. 6-bit 7?6 4-bit 7?4 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose i/o module freescale semiconductor 26-13 26.3.2.3 port pin data/set data registers (port np/set n) the port np/set n registers reflect the current pin states and control the setting of output pins when the pin is configured for digital i/o. most port n registers have a full 8-bi t implementation, as shown in figure 26-11 . the remaining port n registers use fewer than eight bits. their bit definiti ons are shown in figure 26-12 , figure 26-13 , and figure 26-14 . the port np/set n registers are read/write. at reset, the bits in the port n p/setn registers are set to the current pin states. reading a port np/set n register returns the cu rrent state of the port n pins. setting a port np/set n register sets the corr esponding bits in the port n register. writing 0s has no effect. 7 6543210 field port n p7/ set n 7 port n p6/ set n 6 port n p5/ set n 5 port n p4/ set n 4 port n p3/ set n 3 port n p2/ set n 2 port n p1/ set n 1 port n p0/ set n 0 reset current pin state r/w: r/w address ipsbar + 0x10_0028 (portap/seta), 0x10_ 0029 (portbp/setb), 0x10_002a (portcp/setc), 0x10_002b (portdp/setd), 0x10_002c (por tep/sete), 0x10_002d (portfp/setf), 0x10_002e (portgp/setg), 0x10_002f (porth p/seth), 0x10_0030 (portjp/setj), 0x10_0031 (portddp/setdd), 0x10_0032 (portehp/ seteh), 0x10_0033 (portelp/setel) figure 26-11. port pin data/set data registers (8-bit) 76 5 4 3 2 1 0 field ? port n p6/s et n 6 port n p5/s et n 5 port n p4/s et n 4 port n p3/s et n 3 port n p2/s et n 2 port n p1/s et n 1 port n p0/s et n 0 reset 0 current pin state r/w: ? r/w address ipsbar + 0x10_0035 (portqsp/setqs) figure 26-12. port pin data/set data register (7-bit) 76543210 field ? port n p5/ set n 5 port n p4/ set n 4 port n p3/ set n 3 port n p2/ set n 2 port n p1/ set n 1 port n p0/ set n 0 reset 00 current pin state r/w: ? r/w address ipsbar + 0x10_0034 (portasp/setas), 0x10_0036 (portsdp/setsd) figure 26-13. port pin data/set data registers (6-bit) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose i/o module 26-14 freescale semiconductor port np/set n bits are described in table 26-5 . 26.3.2.4 port clear output data registers (clr n) clearing a clr n register clears the co rresponding bits in the port n register. setting it has no effect. reading the clrn register returns 0s. most port n registers have a full 8-bit implementation, as shown in figure 26-15 . the remaining port n registers use fewer than eight bits. their bit definiti ons are shown in figure 26-16 , figure 26-17 , and figure 26-18 . the clr n registers are read/write accessible. 7 43210 field ? port n p3/ set n 3 port n p2/ set n 2 port n p1/ set n 1 port n p0/ set n 0 reset 0000 current pin state r/w: ? r/w address ipsbar + 0x10_0037 (porttcp/settc), 0x10_0038 (porttdp/settd), 0x10_0039 (portuap/setua) figure 26-14. port pin data/set data registers (4-bit) table 26-5. port n p/set n (8-bit, 6-bit, and 4-bit) field descriptions register bits name description 8-bit 7?0 portx n p/setxn port x pin data/set data bits 1 port x pin state is 1 (read); set corresponding portx bit (write) 0 port x pin state is 0 (read) 7-bit 6?0 6-bit 5?0 4-bit 3?0 7-bit 7 ? reserved, should be cleared. 6-bit 7?6 4-bit 7?4 76543210 field clr n 7clr n 6clr n 5clr n 4clr n 3clr n 2clr n 1clr n 0 reset 0000_0000 r/w: r/w address ipsbar + 0x10_003c (clra), 0x10_003d (clr b), 003e (clrc), 0x10_003f (clrd), 0x10_0040 (clre), 0x10_0041 (clrf), 0x10_0042 (clrg), 0x10_0043 (clrh), 0x10_0044 (clrj), 0x10_0045 (clrdd), 0x10_0046 (clreh), 0x10_0047 (clrel) figure 26-15. port clear output data registers (8-bit) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose i/o module freescale semiconductor 26-15 clr n register bits are described in table 26-6 . 76543210 field ? clr n 6clr n 5clr n 4clr n 3clr n 2clr n 1clr n 0 reset 0000_0000 r/w: r r/w address ipsbar + 0x10_0049 (clrqs) figure 26-16. port clear output data register (7-bit) 76543210 field ? clr n 5clr n 4clr n 3clr n 2clr n 1clr n 0 reset 0000_0000 r/w: r r/w address ipsbar + 0x10_0048 (clras), 0x10_004a (clrsd) figure 26-17. port clear output data registers (6-bit) 7 43210 field ? clr n 3clr n 2clr n 1clr n 0 reset 0000_0000 r/w: r r/w address ipsbar + 0x10_004b (clrtc), 0x10_004c (clrtd), 0x10_004d (clrua) figure 26-18. port clear output data registers (4-bit) table 26-6. clr n (8-bit,7-bit, 6-bit, a nd 4-bit) field descriptions register bits name description 8-bit 7?0 clr nx port n clear output data register bits. 1 never returned for reads; no effect for writes 0 always returned for reads; clears corresponding port n bit for writes 7-bit 6?0 6-bit 5?0 4-bit 3?0 7-bit 7 ? reserved, should be cleared. 6-bit 7?6 4-bit 7?4 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose i/o module 26-16 freescale semiconductor 26.3.2.5 port b/c/d pin assi gnment register (pbcdpar) the pbcdpar controls the pin function of ports b, c, and d. the pbcdpar register is read/write. 765 0 field pbpa pcdpa ? reset see note 1 1 1 reset state determined during reset configuration as shown in table 26-8 . see note 1 00_0000 r/w: r/w r/w r address ipsbar + 0x10_0050 figure 26-19. port b/c/d pin assignment register (pbcdpar) table 26-7. pbcdpar field descriptions bits name description 7 pbpa port b pin assignment. configures the port b pins for their primary function (d[23:16]) or digital i/o. 1 port b pins configured for primary function (d[23:16]) 0 port b pins configured for digital i/o 6 pcdpa ports c,d pin assignment. configures the port c and d pins for their primary functions (d[15:8] , d[7:0]) or digital i/o. 1 port c,d pins configured for pr imary function (d[15:8], d[7:0]) 0 port c,d pins configured for digital i/o 5?0 ? reserved, should be cleared. table 26-8. reset values for pbcdpar bits mode of operation port size of external boot device 1 1 note if the port size of the external boot device is less than the port size of the external sdram, the pbcdpar register must be written after reset to enable the primary function(s) on ports b,c, and d, before any sdram accesses are attempted. pbpa reset value pcdpa reset value master mode 8-bit 0 0 16-bit 1 0 32-bit 1 1 single chip mode n/a 0 0 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose i/o module freescale semiconductor 26-17 26.3.2.6 port e pin assignment register (pepar) the pepar controls the pin function of port e. the pepar register is read/write. 15 14 13 12 11 10 9 8 field ? pepa7 ? pepa6 ? pepa5 ? pepa4 reset 0 see note 1 1 0see note 1 1 0see note 1 1 0 see note 1 1 r/w: r r/w r r/w r r/w r r/w 7 6 5 4 3210 field ? pepa3 ? pepa2 pepa1 pepa0 reset 0 see note 1 1 1 reset state determined during reset configuration as shown in table 26-10 . 0 see note 1 1 see note 1 1 see note 1 1 r/w:rr/wrr/w r/w r/w address ipsbar + 0x10_0052 figure 26-20. port e pin assignment register (pepar) table 26-9. pepar field descriptions bits name description 14 pepa7 port e pin assignment 7. this bit configures the port e7 pin for its primary function (oe ) or digital i/o. 1 port e7 pin configured for primary function (oe ) 0 port e7 pin configured for digital i/o 12 pepa6 port e pin assignment 6. this bit configures the port e6 pin for its primary function (ta ) or digital i/o. 1 port e6 pin configured for primary function (ta ) 0 port e6 pin configured for digital i/o 10 pepa5 port e pin assignment 5. this bit configures the port e5 pin for its primary function (tea ) or digital i/o. 1 port e5 pin configured for primary function (tea ) 0 port e5 pin configured for digital i/o 8 pepa4 port e pin assignment 4. this bit configures the port e4 pin for its primary function (r/w ) or digital i/o. 1 port e4 pin configured for primary function (r/w ) 0 port e4 pin configured for digital i/o mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose i/o module 26-18 freescale semiconductor the reset values for all bits and fields in pepar are shown in table 26-10 . 6 pepa3 port e pin assignment 3 this bit configures the port e3 pin for its alternate function (synca) or digital i/o. 1 port e3 pin configured for alternate function (synca) 0 port e3 pin configured for digital i/o note: the siz1 primary function on the port e3 pin is enabled by the szen bit in the ccr register. please refer to the chapter 27, ?chip configuration module (ccm) for more information on chip configuration and the szen bit. 4 pepa2 port e pin assignment 2 this bit configures the port e2 pin for its alternate function (syncb) or digital i/o. 1 port e2 pin configured for alternate function (syncb) 0 port e2 pin configured for digital i/o note: the siz0 primary function on the port e2 pin is enabled by the szen bit in the ccr register. please refer to the chapter 27, ?chip configuration module (ccm) ,? for more information on chip configuration and the szen bit. 3?2 pepa1 port e pin assignment 1. this two-bit field in pepar[3:2] configures the port e1 pin for its primary function (ts ), alternate function (synca), or digital i/o. 0x port e1 pin configured for digital i/o 10 port e1 pin configured for alternate function (synca) 11 port e1 pin configured for primary function (ts ) 1-0 pepa0 port e pin assignment 0. this two-bit field in pepar[1:0] configures the port e0 pin for its primary function (tip ), alternate function (syncb), or digital i/o. 0x port e0 pin configured for digital i/o 10 port e0 pin configured for alternate function (syncb) 11 port e0 pin configured for primary function (tip ) table 26-10. reset values for pepar bits and fields mode of operation reset values for pepa n bits ( n = 2,3,4,5,6,7) reset values for pepa n fields ( n = 0,1) master mode 1 11 single chip mode 0 00 table 26-9. pepar field descriptions (continued) bits name description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose i/o module freescale semiconductor 26-19 26.3.2.7 port f pin assi gnment register (pfpar) the pfpar controls the pin function of port f[7:5]. 7654 0 field pfpa7 pfpa6 pfpa5 ? reset see note 1 1 1 reset state determined during reset configuration. pfpa n = 1 in master mode and 0 in all other modes. 0_0000 r/w: r/w r address ipsbar + 0x10_0051 figure 26-21. port f pin assignment register (pfpar) table 26-11. pfpar field descriptions bits name description 7 pfpa7 port f pin assignment 1. the pfpa 7 bit configures the port f7 pin for its primary function (a23), alternate function (cs6 ), or digital i/o. 1 port f7 pin configured for primary function (a23) or alternate function (cs6 ), depending on the chip configuration. 0 port f7 pin configured for digital i/o refer to chapter 27, ?chip configuration module (ccm) ? for more information on reset configuration. 6 pfpa6 port f pin assignment 6. the pfpa 6 bit configures the port f6 pin for its primary function (a22), alternate function (cs5 ), or digital i/o. 1 port f6 pin configured for primary function (a22) or alternate function (cs5 ), depending on the chip configuration. 0 port f6 pin configured for digital i/o refer to chapter 27, ?chip configuration module (ccm) ? for more information on reset configuration. 5 pfpa5 port f pin assignment 5. the pfpar bit configures the port f5 pin for its primary function (a21), alternate function (cs4 ), or digital i/o. 1 port f5 pin configured for primary function (a21) or alternate function (cs4 ), depending on the chip configuration. 0 port f5 pin configured for digital i/o refer to chapter 27, ?chip configuration module (ccm) ? for more information on reset configuration. 4?0 ? reserved, should be cleared. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose i/o module 26-20 freescale semiconductor 26.3.2.8 port j pin assi gnment register (pjpar) the pjpar controls the pin function of port j. 76543210 field pjpa7 pjpa6 pjpa5 pjpa4 pjpa3 pjpa2 pjpa1 pjpa0 reset see note 1 1 1 reset state determined during reset configuration. pjpa n = 1 in master mode and 0 in all other modes. r/w: r/w address ipsbar + 0x10_0054 figure 26-22. port j pin assignment register (pjpar) table 26-12. pjpar field descriptions bits name description 7 pjpa7 port j pin assignment 7. this bit configures the port j7 pin for its primary function (bs3 ) or digital i/o. 1 port j7 pin configured for its primary function (bs3 ) 0 port j7 pin configured for digital i/o 6 pjpa6 port j pin assignment 6. this bit configures the port j6 pin for its primary function (bs2 ) or digital i/o. 1 port j6 pin configured for its primary function (bs2 ) 0 port j6 pin configured for digital i/o 5 pjpa5 port j pin assignment 5. this bit configures the port j5 pin for its primary function (bs1 ) or digital i/o. 1 port j5 pin configured for its primary function (bs1 ) 0 port j5 pin configured for digital i/o 4 pjpa4 port j pin assignment 4. this bit configures the port j4 pin for its primary function (bs0 ) or digital i/o. 1 port j4 pin configured for its primary function (bs0 ) 0 port j4 pin configured for digital i/o 3 pjpa3 port j pin assignment 3. this bit configures the port j3 pin for its primary function (cs3 ) or digital i/o. 1 port j3 pin configured for its primary function (cs3 ) 0 port j3 pin configured for digital i/o 2 pjpa2 port j pin assignment 2. this bit configures the port j2 pin for its primary function (cs2 ) or digital i/o. 1 port j2 pin configured for its primary function (cs2 ) 0 port j2 pin configured for digital i/o 1 pjpa1 port j pin assignment 1. this bit configures the port j1 pin for its primary function (cs1 ) or digital i/o. 1 port j1 pin configured for its primary function (cs1 ) 0 port j1 pin configured for digital i/o 0 pjpa0 port j pin assignment 0. this bit configures the port j0 pin for its primary function (cs0 ) or digital i/o. 1 port j0 pin configured for its primary function (cs0 ) 0 port j0 pin configured for digital i/o mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose i/o module freescale semiconductor 26-21 26.3.2.9 port sd pin assi gnment register (psdpar) the psdpar controls the pin function of port sd. 26.3.2.10 port as pin assi gnment register (paspar) the paspar controls the pin function of port as. 76 0 field psdpa ? reset see note 1 1 1 reset state determined during reset configuration. pjpa n = 1 in master mode and 0 in all other modes. 000_0000 r/w: r/w r address ipsbar + 0x10_0055 figure 26-23. port sd pin assignment register (psdpar) table 26-13. psdpar field descriptions bits name description 7 psdpa port sd pin assignment. this bit configures the port sd[5:0] pins for their primary functions (sras , scas , dramw , sdram_cs [1:0], scke) or digital i/o. 1 port sd[5:0] pins configured for primary functions (sras , scas , dramw , sdram_cs [1:0], scke) 0 port sd[5:0] pin configured for digital i/o 6?0 ? reserved, should be cleared. 15 12 11 10 9 8 field ? paspa5 paspa4 reset 0000_0000 r/w: r r/w 76543210 field paspa3 paspa2 paspa1 paspa0 reset 0000_0000 r/w: r/w address ipsbar + 0x10_0056 figure 26-24. port as pin assignment register (paspar) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose i/o module 26-22 freescale semiconductor 26.3.2.11 port eh/el pin assignment register (pehlpar) the pehlpar controls the pin function of ports eh and el. note port eh is not available on the mcf5214 and mcf5216. the pehlpar is read/write accessible. table 26-14. paspar field descriptions bits name description 15?12 ? reserved, should be cleared. 11?10 paspa5 port as pin assignment 5. these bits configure the as5 pin for its primary function (emdio), alternate function (urxd2), or digital i/o. 0x port as5 pin configured for digital i/0 10 port as5 pin configured for alternate function (urxd2) 11 port as5 pin configured for primary function (emdio) note: setting 11 is reserved for the mcf5214 and mcf5216. 9-8 paspa4 port as pin assignment 4. these bits configure the as4 pin for its primary function (emdc), alternate function (utxd2), or digital i/o. 0x port as4 pin configured for digital i/0 10 port as4 pin configured for alternate function (utxd2) 11 port as4 pin configured for primary function (emdc) note: setting 11 is reserved for the mcf5214 and mcf5216. 7-6 paspa3 port as pin assignment 3. these bits configure the as3 pin for its primary function (canrx), alternate function (urxd2), or digital i/o. 0x port as3 pin configured for digital i/0 10 port as3 pin configured for alternate function (urxd2) 11 port as3 pin configured for primary function (canrx) 5-4 paspa2 port as pin assignment 2. these bits configure the as2 pin for its primary function (cantx), alternate function (utxd2), or digital i/o. 0x port as2 pin configured for digital i/0 10 port as2 pin configured for alternate function (utxd2) 11 port as2 pin configured for primary function (cantx) 3-2 paspa1 port as pin assignment 1. these bits configure the as1 pin for its primary function (sda), alternate function (urxd2), or digital i/o. 0x port as1 pin configured for digital i/0 10 port as1 pin configured for alternate function (urxd2) 11 port as1 pin configured for primary function (sda) 1-0 paspa0 port as pin assignment 0. these bits configure the as0 pin for its primary function (scl), alternate function (utxd2), or digital i/o. 0x port as0 pin configured for digital i/0 10 port as0 pin configured for alternate function (utxd2) 11 port as0 pin configured for primary function (scl) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose i/o module freescale semiconductor 26-23 26.3.2.12 port qs pin assignment register (pqspar) the pqspar controls the pin function of port qs. 765 0 field pehpa pelpa ? reset 0000_0000 r/w: r/w r address ipsbar + 0x10_0058 figure 26-25. port eh/el pin assignment register (pehlpar) table 26-15. pehlpar field descriptions bits name description 7 pehpa port eh pin assignment. this bit configures the port eh pins for its primary functions (etxclk, etxen, etxd[0], ecol, erxclk, erxdv, erxd[0], ecrs) or digital i/o. 0 port eh pins configured for digital i/o 1 port eh pins configured for primary functi ons (etxclk, etxen, etxd[0], ecol, erxclk, erxdv, erxd[0], ecrs) note: this bit is reserved for the mcf5214 and mcf5216. 6 pelpa port el pin assignment. this bit configures t he port el pins for their primary functions (etxd[3], etxd[2], etxd[1], et xer, erxd[3], erxd [2], erxd[1], erxer ) or digital i/o. 0 port el pins configured for digital i/o 1 port el pins configured for primary function s (etxd[3], etxd[2], et xd[1], etxer, erxd[3], erxd[2], erxd[1], erxer) note: setting 1 is reserved for the mcf5214 and mcf5216. 5?0 ? reserved, should be cleared. 7 6543210 field ? pqspa6 pqspa5 pqspa4 pqspa3 pqspa2 pqspa1 pqspa0 reset 0000_0000 r/w: r r/w address ipsbar + 0x10_0059 figure 26-26. port qs pin assignment register (pqspar) table 26-16. pqspar field description bits name description 7 ? reserved, should be cleared. 6 pqspa6 port qs pin assignment 6. this bit configures the port qs6 pin for its primary function (qspi _cs3) or digital i/o. 1 port qs6 pin configured for primary function (qspi_cs3) 0 port qs6 pin configured for digital i/o mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose i/o module 26-24 freescale semiconductor 26.3.2.13 port tc pin assi gnment register (ptcpar) the ptcpar controls the pin function of port tc. 5 pqspa5 port qs pin assignment 5. this bit configures the port qs5 pin for its primary function (qspi _cs2) or digital i/o. 1 port qs5 pin configured for primary function (qspi_cs2) 0 port qs5 pin configured for digital i/o 4 pqspa4 port qs pin assignment 4. this bit configures the port qs4 pin for its primary function (qspi _cs1) or digital i/o. 1 port qs4 pin configured for primary function (qspi_cs1) 0 port qs4 pin configured for digital i/o 3 pqspa3 port qs pin assignment 3. this bit configures the port qs3 pin for its primary function (qspi _cs0) or digital i/o. 1 port qs3 pin configured for primary function (qspi_cs0) 0 port qs3 pin configured for digital i/o 2 pqspa2 port qs pin assignment 2. this bit configures the port qs2 pin for its primary function (qspi_clk) or digital i/o. 1 port qs2 pin configured for primary function (qspi_clk) 0 port qs2 pin configured for digital i/o 1 pqspa1 port qs pin assignment 1. this bit configures the port qs1 pin for its primary function (qspi_din) or digital i/o. 1 port qs1 pin configured for primary function (qspi_din) 0 port qs1 pin configured for digital i/o 0 pqspa0 port qs pin assignment 0. this bit configures the port qs0 pin for its primary function (qspi_dout) or digital i/o. 1 port qs0 pin configured for primary function (qspi_dout) 0 port qs0 pin configured for digital i/o 7 6543210 field ptcpa3 ptcpa2 ptcpa1 ptcpa0 reset 0000_0000 r/w: r/w address ipsbar + 0x10_005a figure 26-27. port tc pin assignment register (ptcpar) table 26-16. pqspar field description (continued) bits name description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose i/o module freescale semiconductor 26-25 26.3.2.14 port td pin assi gnment register (ptdpar) the ptdpar controls the pin function of port td. table 26-17. ptcpar field descriptions bits name description 7?6 ptcpa3 port tc pin assignment 3. this field conf igures the port tc3 pin for its primary function (dtin3), alternate 1 function (urts1 ), alternate 2 function (urts0 ) or digital i/o. 00 port tc3 pin configured for digital i/o 01 port tc3 pin configured for alternate 2 function (urts0 ) 10 port tc3 pin configured for alternate 1 function (urts1 ) 11 port tc3 pin configured for primary function (dtin3) 5-4 ptcpa2 port tc pin assignment 2. this field conf igures the port tc2 pin for its primary function (dtout3), alternate 1 function (urts1 ), alternate 2 function (urts0 ) or digital i/o. 00 port tc2 pin configured for digital i/o 01 port tc2 pin configured for alternate 2 function (urts0 ) 10 port tc2 pin configured for alternate 1 function (urts1 ) 11 port tc2 pin configured for primary function (dtout3) 3-2 ptcpa1 port tc pin assignment 1. this field conf igures the port tc1 pin for its primary function (dtin2), alternate 1 function (ucts1 ), alternate 2 function (ucts0 ) or digital i/o. 00 port tc1 pin configured for digital i/o 01 port tc1 pin configured for alternate 2 function (ucts0 ) 10 port tc1 pin configured for alternate 1 function (ucts1 ) 11 port tc1 pin configured for primary function (dtin2) 1-0 ptcpa0 port tc pin assignment 0. this field conf igures the port tc0 pin for its primary function (dtout2), alternate 1 function (ucts1 ), alternate 2 function (ucts0 ) or digital i/o. 00 port tc0 pin configured for digital i/o 01 port tc0 pin configured for alternate 2 function (ucts0 ) 10 port tc0 pin configured for alternate 1 function (ucts1 ) 11 port tc0 pin configured for primary function (dtout2) 7 6543210 field ptdpa3 ptdpa2 ptdpa1 ptdpa0 reset 0000_0000 r/w: r/w address ipsbar + 0x10_005b figure 26-28. port td pin assignment register (ptdpar) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose i/o module 26-26 freescale semiconductor 26.3.2.15 port ua pin assignment register (puapar) the puapar controls the pin function of port ua. table 26-18. ptdpar field descriptions bits name description 7?6 ptdpa3 port td pin assignment 3. this field conf igures the port td3 pin for its primary function (dtin1), alternate 1 function (urts1 ), alternate 2 function (urts0 ) or digital i/o. 00 port td3 pin configured for digital i/o 01 port td3 pin configured for alternate 2 function (urts0 ) 10 port td3 pin configured for alternate 1 function (urts1 ) 11 port td3 pin configured for primary function (dtin1) 5-4 ptdpa2 port td pin assignment 2. this field conf igures the port td2 pin for its primary function (dtout1), alternate 1 function (urts1 ), alternate 2 function (urts0 ) or digital i/o. 00 port td2 pin configured for digital i/o 01 port td2 pin configured for alternate 2 function (urts0 ) 10 port td2 pin configured for alternate 1 function (urts1 ) 11 port td2 pin configured for primary function (dtout1) 3-2 ptdpa1 port td pin assignment 1. this field conf igures the port td1 pin for its primary function (dtin0), alternate 1 function (ucts1 ), alternate 2 function (ucts0 ) or digital i/o. 00 port td1 pin configured for digital i/o 01 port td1 pin configured for alternate 2 function (ucts0 ) 10 port td1 pin configured for alternate 1 function (ucts1 ) 11 port td1 pin configured for primary function (dtin0) 1-0 ptdpa0 port td pin assignment 0. this field conf igures the port td0 pin for its primary function (dtout0), alternate 1 function (ucts1 ), alternate 2 function (ucts0 ) or digital i/o. 00 port td0 pin configured for digital i/o 01 port td0 pin configured for alternate 2 function (ucts0 ) 10 port td0 pin configured for alternate 1 function (ucts1 ) 11 port td0 pin configured for primary function (dtout0) 7 43210 field ? puapa3 puapa2 puapa1 puapa0 reset 0000_0000 r/w: r r/w address ipsbar + 0x10_005c figure 26-29. port ua pin assignment register (puapar) table 26-19. puapar field descriptions bits name description 7?4 ? reserved, should be cleared. 3 puapa3 port ua pin assignment 3. this bit configures the port ua3 pin for its primary function (urxd1) or digital i/o. 1 port ua3 pin configured for primary function (urxd1) 0 port ua3 pin configured for digital i/o mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose i/o module freescale semiconductor 26-27 26.4 functional description 26.4.1 overview the initial pin function is determin ed during reset configuration. the pin assignment registers allow the user to select between digital i/o or another pin function after reset. in single-chip mode, all pins ar e configured as digital i/o by de fault, except for debug data pins (ddata[3:0]) and processor status pins (pst[3:0]). these pins are configured for their primary functions by default in all modes. every digital i/o pin is individually configurable as an i nput or an output via a data direction register (ddr n). every port has an output data register (port n ) and a pin data register (port n p/set n) to monitor and control the state of its pi ns. data written to a port n register is stored and then driven to the corresponding port n pins configured as outputs. reading a port n register returns the current state of th e register regardless of the state of the corresponding pins. reading a port np/psetn register returns the current state of the corresponding pins when configured as digital i/o, regardless of whethe r the pins are inputs or outputs. every port has a port np/set n register and a clear register (clrn) for setting or clearing individual bits in the port n register. in master mode, port a and b func tion as the upper external data bus , d[31:16]. when the pcdpa bit is set, ports c and d function as the lower external data bus, d[15:0]. ports e?j are configured to support external memory functions. the ports module does not generate interrupt requests. 26.4.2 port digital i/o timing input data on all pins configured as digital i/o is synchronized to th e rising edge of clkout, as shown in figure 26-30 . 2 puapa2 port ua pin assignment 2. this bit configures the port ua2 pin for its primary function (utxd1) or digital i/o. 1 port ua2 pin configured for primary function (utxd1) 0 port ua2 pin configured for digital i/o 1 puapa1 port ua pin assignment 1. this bit configures the port ua1 pin for its primary function (urxd0) or digital i/o. 1 port ua1 pin configured for primary function (urxd0) 0 port ua1 pin configured for digital i/o 0 puapa0 port ua pin assignment 0. this bit configures the port ua0 pin for its primary function (utxd0) or digital i/o. 1 port ua0 pin configured for primary function (utxd0) 0 port ua0 pin configured for digital i/o table 26-19. puapar field descriptions (continued) bits name description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 general purpose i/o module 26-28 freescale semiconductor figure 26-30. digital input timing data written to the port n register of any pin confi gured as a digital output is immediately driven to its respective pin, as shown in figure 26-31 . figure 26-31. digital output timing 26.5 initialization/application information the initialization for the ports modul e is done during reset configuration. some of th e registers are reset to a predetermined state, and others are reset accor ding to which mode of operation is chosen by reset configuration. refer to section 26.3, ?memory ma p/register definition ,? for more details on reset and initialization. clkout pin data input register pin clkout output data output pin register mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor 27-1 chapter 27 chip configuration module (ccm) the chip configuration module (ccm) controls the chip configuration and operating mode. 27.1 features the ccm performs these operations. ? selects the chip operating mode: ? master mode ? single-chip mode ? selects external clock or phase-lock loop (pll) mode with internal or external reference ? selects output pad drive strength ? selects boot device and data port size ? selects bus monitor configuration ? selects low-power configuration ? selects transfer size f unction of the external bus ? selects processor status (pstat) and processor debug data (ddata) functions ? selects bdm or jtag mode 27.2 modes of operation the ccm configures the chip for two modes of operation: ? master mode ? single-chip mode the operating mode is determined at reset and cannot be changed thereafter. 27.2.1 master mode in master mode, the central pro cessor unit (cpu) can access external memories and peripherals. the external bus consists of a 32-bit data bus and 24 address lines. the available bus cont rol signals include r/w , ts , tip , tsiz[1:0], ta , tea , oe , and bs [3:0]. up to seven chip selects can be programmed to select and control external devices and to provide bus cycle termina tion. when interfacing to 16-bit ports, the port c and d pins and pj[5:4] (bs [1:0]) can be configured as gene ral-purpose input/output (i/o), and when interfacing to 8-bit ports, the ports b, c and d pins and pj[7:5] (bs [3:1]) can be configured as general purpose input/output (i/o). 27.2.2 single-chip mode in single-chip mode, all memory is internal to the ch ip. all external bus pins are configured as general purpose i/o. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 chip configuration module (ccm) 27-2 freescale semiconductor 27.3 block diagram figure 27-1. chip configuration module block diagram 27.4 signal descriptions table 27-1 provides an overview of the ccm signals. 27.4.1 rcon if the external rcon pin is asserted during reset, then various chip functions, including the reset configuration pin functions after rese t, are configured according to the levels driven onto the external data pins. (see section 27.6, ?functional description ?). the internal configuration signals are driven to reflect the levels on the external configuration pins to allo w for module configuration. 27.4.2 clkmod[1:0] the state of the clkmod[1:0] pins dur ing reset determines the clock mode. table 27-1. signal properties name function reset state rcon reset configuration select internal weak pull-up device clkmod[1:0] clock mode select ? d[26:24, 21, 19:16] reset co nfiguration override pins ? reset chip mode selection boot device / port size selection output pad strength selection clock mode selection chip select configuration configuration reset configuration register chip configuration register chip identification register chip test register mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 chip configuration module (ccm) freescale semiconductor 27-3 27.4.3 d[26:24, 21, 19:16] (r eset configuration override) if the external rcon pin is asserted during reset, then the states of these da ta pins during reset determine the chip mode of operation, boot device, clock mode , and certain module configurations after reset. 27.5 memory map and registers this subsection provides a description of the memory map and registers. 27.5.1 programming model the ccm programming model cons ists of these registers: ? the chip configuration register (ccr) controls the main chip configuration. ? the reset configuration regi ster (rcon) indicates the default chip configuration. ? the chip identification register (c ir) contains a unique part number. some control register bits are implemented as write- once bits. these bits are al ways readable, but once the bit has been written, additional writes have no effect, except during debug and test operations. some write-once bits can be read and written while in debug mode. wh en debug mode is exited, the chip configuration module resumes operati on based on the current register va lues. if a write to a write-once register bit occurs while in debug mode, the register bit remains writable on exit from debug or test mode. table 27-2 shows the accessibility of write-once bits. 27.5.2 memory map table 27-2. write-once bits read/write accessibility configuration read/write access all configurations read-always debug operation (all modes) write-always master mode write-once single-chip mode write-once table 27-3. chip configuration module memory map ipsbar offset bits 31?16 bits 15?0 access 1 1 s = cpu supervisor mode access only. user mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error. 0x0011_0004 chip configuration register (ccr) low-power control register (lpcr) 2 2 see chapter 7, ?power management ,? for a description of the lpcr. it is shown her e only to warn against accidental writes to this register. s 0x0011_0008 reset configuration register (rcon) chip identification register (cir) s 0x0011_000c reserved 3 3 writing to reserved addresses with values other than 0 c ould put the device in a test mode; reading returns 0s. s 0x0011_0010 unimplemented 4 ? mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 chip configuration module (ccm) 27-4 freescale semiconductor 27.5.3 register descriptions the following subsection describes the ccm registers. 27.5.3.1 chip configur ation register (ccr) 4 accessing an unimplemented address has no effect and causes a cycle termin ation transfer error. note to safeguard against unintentionally activating test l ogic, write 0x0000 to the above reserved location during initial ization (immediately after reset) to lock out test features. se tting any bits in the ccr may lead to unpredictable results. 15 14 11 10 8 7 6 5 4 3 2 0 field load ? mode ? szen psten ? bme bmt reset see note r/w r/w read only r/w address ipsbar + 0x11_0004 note: the reset value of the load and mode fields is det ermined during reset configuration. the szen is set for master mode and cleared for all other configurations. the bme bit is set to enable the bus monitor and all other bits in the register are cleared at reset. figure 27-2. chip configuration register (ccr) table 27-4. ccr field descriptions bits name description 15 load pad driver load. the load bit selects full or partial drive strength for selected pad output drivers. for maximum capacitive load, set the load bit to select full drive strength. for reduced power consumption and reduced electromagnetic interference (emi), clear the load bit to select partial drive strength. 0 default drive strength. 1 full drive strength. table 27-2 shows the read/write accessibi lity of this write-once bit. 14?11 ? reserved, should be cleared. 10?8 mode chip configuration mode. this read-only field reflects the chip configuration mode. 000-101 reserved. 110 single-chip mode. 111 master mode. 7 ? reserved, should be cleared. 6 szen siz[1:0] enable. this read/write bit enable s the siz[1:0] function of the external pins. 0 siz[1:0] function disabled. 1 siz[1:0] function enabled. 5 psten pst[3:0]/ddata[3:0] enable. this read/write bit enables the processor status (pst) and debug data (ddata)n functions of the external pins. 0 pst/ddata function disabled. 1 pst/ddata function enabled. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 chip configuration module (ccm) freescale semiconductor 27-5 27.5.3.2 reset configuration register (rcon) at reset, rcon determines the defa ult operation of certain chip functio ns. all default functions defined by the rcon values can only be overri dden during reset configuration (see section 27.6.1, ?reset configuration ?) if the external rcon pin is asserted. rcon is a read-only register. 4 ? reserved, should be cleared. 3 bme bus monitor enable. this read/write bit enables the bus monitor to operate during external bus cycles. 0 bus monitor disabled for external bus cycles. 1 bus monitor enabled for external bus cycles. table 27-2 shows the read/write accessibi lity of this write-once bit. 2?0 bmt bus monitor timing. this fi eld selects the timeout period (in system clocks) for the bus monitor. 000 65536 001 32768 010 16384 011 8192 100 4096 101 2048 110 1024 111 512 table 27-2 shows the read/write accessibi lity of this write-once bit. 15 109876 5 43 2 1 0 field ? rcsc ? rload bootps bootsel ? mode reset 0000_0000_1110_0000 r/w r address ipsbar + 0x11_0008 figure 27-3. reset configuration register (rcon) table 27-5. rcon field descriptions bits name description 15?10 ? reserved, should be cleared. 9?8 rcsc chip select configuration. reflects the defa ult chip select configuration. the default function of the chip select configuration can be overridden during reset configuration. 00 pf[7:5] = a[23:21] (this is the value used for this device.) 01 pf[7] = cs6 / pf[6:5] = a[22:21] 10 pf[7:6] = cs6 , cs5 / pf[5] = a[21] 11 pf[7:5] = cs6 , cs5 , cs4 7?6 ? reserved, should be cleared. 5 rload pad driver load. reflects the default pad driver strength configuration. 0 partial drive strength 1 full drive strength (this is the value used for this device.) table 27-4. ccr field descriptions (continued) bits name description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 chip configuration module (ccm) 27-6 freescale semiconductor 27.5.3.3 chip identification register (cir) 27.6 functional description six functions are defined within the chip configuration module: 1. reset configuration 2. chip mode selection 3. boot device selection 4. output pad strength configuration 4?3 bootps boot port size. reflects the default selection for the boot port size if the boot device is configured to be external. 00 internal (32 bits) (this is the value used for this device.) 01 16 bits 10 8 bits 11 32 bits the default function of the boot port size can be overridden during reset configuration. 2 bootsel boot select. reflects the default selection for the boot device. 0 boot from internal boot device (this is the value used for this device.) 1 boot from external boot device 1 ? reserved, should be cleared. 0 mode chip configuration mode. reflects the default chip configuration mode. 0 single-chip mode (this is the value used for this device.) 1 master mode the default mode can be overridden during reset c onfiguration. if the default is overridden, the ccr[mode0] reflects the mode configuration. 15 8 7 0 field pin prn reset 0010_0000_0000_0000 r/w r address ipsbar + 0x11_000a figure 27-4. chip identification register (cir) table 27-6. cir field description bits name description 15?8 pin part identification number. contains a unique identification number for the device. 7?0 prn part revision number. this number is increased by one for each new full-layer mask set of this part. th e revision numbers are assigned in chronological order. table 27-5. rcon field descriptions (continued) bits name description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 chip configuration module (ccm) freescale semiconductor 27-7 5. clock mode selections 6. chip select configuration these functions are described here. 27.6.1 reset configuration during reset, the pins for the reset override func tions are immediately conf igured to known states. table 27-7 shows the states of the ex ternal pins while in reset. if the rcon pin is not asserted during reset, the chip configuration and the reset configuration pin functions after reset are determined by the rcon register or fixed defaults , regardless of th e states of the external data pins. the internal c onfiguration signals are driven to le vels specified by the rcon register?s reset state for default module configuration. if the rcon pin is asserted during reset, then various ch ip functions, including the reset configuration pin functions after reset, are configured according to the levels driven onto the external data pins. (see table 27-8 ) the internal configuration signal s are driven to reflect the levels on the external configuration pins to allow for module configuration. note during reset, the clkmod pins always determine the clock mode, regardless of the rcon pin state. table 27-7. reset configuration pin states during reset pin pin function 1 1 if the external rcon pin is not asserted during reset, pin functions are determined by the default operation mode defined in the rcon register. if the external rcon pin is asserted, pin functions are determined by the override values driven on the external data bus pins. i/o output state input state d[26:24, 21, 19:16], pa[2:0], pb[5, 3:0] digital i/o or primary function input ? must be driven by external logic rcon rcon function for all modes 2 2 during reset, the external rcon pin assumes its rcon pin function, but this pin changes to the function defined by the chip operation mode immediately after reset. see table 27-8 . input ? internal weak pull-up device clkmod1, clkmod0 not affected input ? must be driven by external logic table 27-8. configuration during reset 1 pin(s) affected default configuration override pins in reset 2,34 function d[31:0], r/w , ta , tea , tsiz[1:0], ts , tip , oe, a[23:0], bs[3:0] , cs[3:0] rcon0 = 0 d[26,17:16] chip mode selected 111 master mode 110 single-chip mode 5 100 or 0xx reserved mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 chip configuration module (ccm) 27-8 freescale semiconductor 27.6.2 chip mode selection the chip mode is selected during re set and reflected in the mode field of the chip configuration register (ccr). see section 27.5.3.1, ?chip confi guration register (ccr) .? once reset is exited, the operating mode cannot be changed. table 27-9 shows the mode selection during reset configuration. cs0 rcon[4:3] = 00 rcon2 = 0 d[19:18] boot device 00 internal with 32-bit port 5 10 external with 8-bit port 01 external with 16-bit port 11 external with 32-bit port all output pins rcon5 = 1 d21 output pad drive strength 0 partial strength 1 full strength 5 clock mode n/a clkmod1, clkmod0 clock mode 00 external clock mode (pll disabled) 01 1:1 pll mode 10 normal pll mode with external clock reference 11 normal pll mode w/crystal reference a[23:21]/cs[6:4] rcon[9:8] = 00 d[25:24] chip select configuration 00 pf[7:5] = a[23:21] 5 10 pf[7] = cs6 / pf[6:5] = a[22:21] 01 pf[7:6] = cs6 , cs5 / pf[5] = a[21] 11 pf[7:6] = cs6 , cs5 , cs4 1 modifying the default configurations is possible only if the external rcon pin is asserted. 2 the d[31:27, 23:22, 20, 15: 0] pins do not affect reset configuration. 3 the external reset override circuitry drives the data bus pins with the override values while rsto is asserted. it must stop driving the data bus pins wit hin one clkout cycle after rsto is negated. to prevent content ion with the external reset override circuitry, the reset override pins are forced to in puts during reset and do not become outputs until at least one clkout cycle after rsto is negated. 4 rcon[0] has higher priority than rcon[3:2]. when rcon[0] is configured to boot the chip in single chip mode, the part will boot internally with a 32-bit port overriding any configuration set by rcon[3:2]. 5 default configuration table 27-8. configuration during reset 1 (continued) pin(s) affected default configuration override pins in reset 2,34 function mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 chip configuration module (ccm) freescale semiconductor 27-9 note when flash security is enabled, the chip will boot in single chip mode regardless of the extern al reset configuration. during reset, certain module configurations depend on whether emulation mode is active as determined by the state of the internal emulation signal. 27.6.3 boot device selection during reset configuration, the cs0 chip select pin is optionally configured to select an external boot device. in this case, the v (valid) bit in the csmr0 re gister is ignored, and cs0 is enabled after reset. cs0 is asserted for the initial boot fetch accessed fr om address 0x0000_0000 for the stack pointer and address 0x0000_0004 for the program count er (pc). it is assumed that the reset vector loaded from address 0x0000_0004 causes the cpu to start executing from external memory space decoded by cs0 . 27.6.4 output pad stre ngth configuration output pad strength is determined dur ing reset configuration as shown in table 27-10 . once reset is exited, the output pad strength configur ation can be changed by program ming the load bit of the chip configuration register. 27.6.5 clock mode selection the clock mode is selected dur ing reset by the clkmod pins and reflected in the pllmode, pllsel, and pllref bits of synsr. after reset is exited, the clock mode cannot be changed. table 27-11 summarizes clock mode selec tion during reset configuration. table 27-9. chip configuration mode selection 1 1 modifying the default configurations is possible only if the external rcon pin is asserted low. chip configuration mode ccr register mode field mode2 mode1 mode0 master mode d26 driven high d17 driven high d16 driven high single-chip mode d26 driven high d17 driven high d16 driven low reserved d26 driven high d17 driven low d16 driven high reserved d26 driven low d17 don?t care d16 don?t care table 27-10. output pad driver strength selection 1 1 modifying the default configurations is possible only if the external rcon pin is asserted low. optional pin function selection ccr register load bit output pads configured for partial strength d21 driven low output pads configured for full strength d21 driven high mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 chip configuration module (ccm) 27-10 freescale semiconductor 27.6.6 chip select configuration the chip select configuration (cs [6:4]) is selected during reset and re flected in the rcsc field of the ccr. once reset is exited, the chip sele ct configuration cannot be changed. table 27-8 shows the different chip select configurations that can be implemented during reset configuration. 27.7 reset reset initializes ccm registers to a known startup state as described in section 27.5, ?memory map and registers .? the ccm controls chip configur ation at reset as described in section 27.6, ?functional description .? 27.8 interrupts the ccm does not generate interrupt requests. table 27-11. clock mode selection clock mode clkmod[1:0] synthesizer status register (synsr) pllsel pllref pllmod external clock mode (pll disabled) 00 0 0 0 1:1 pll mode 01 0 0 1 normal pll mode, external clock reference 10 1 0 1 normal pll mode, crystal oscillator reference 11 1 1 1 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor 28-1 chapter 28 queued analog-to-digital converter (qadc) the queued analog-to-digital convert er (qadc) is a 10-bit, unipolar, successive approximation converter. up to eight analog input channels can be supported using internal multiplexing. a maximum of 18 input channels can be supported in the e xpanded, externally multiplexed mode. the qadc consists of an analog front-end and a digital control subs ystem. the analog section includes input pins, an analog multiplexer, and sample and hold analog circuits. the digital control s ection contains queue contro l logic to sequence the conve rsion process and interrupt generation logic. also incl uded are the periodic/interval timer, cont rol and status registers, the conversion command word (ccw) table, ra ndom-access memory (ram), and the result table ram. the bus interface unit (biu) provides access to re gisters that configure the qadc, control the analog-to-digital converter and queue mechanism, and presen t formatted conversion results. 28.1 features features of the qadc module include: ? internal sample and hold ? up to eight analog input channe ls using internal multiplexing ? up to four external analog mu ltiplexers directly supported ? up to 18 total input ch annels with internal and external multiplexing ? programmable input sample time for various source impedances ? two conversion command word (ccw) queues with a total of 64 entries for setting conversion parameters of eac h a/d conversion ? subqueues possible using pause mechanism ? queue complete and pause interrupts available on both queues ? queue pointers indicating current location for each queue ? automated queue modes initiated by: ? external edge trigger and gated trigger ? periodic/interval timer, with in qadc module (queues 1 and 2) ? software command ? single scan or cont inuous scan of queues ? 64 result registers ? output data readable in three formats: ? right-justified unsigned ? left-justified signed ? left-justified unsigned ? unused analog channels can be us ed as discrete input/output pins. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) 28-2 freescale semiconductor 28.2 block diagram figure 28-1. qadc block diagram 28.3 modes of operation this subsection describes the two modes of operati on in which the qadc does not perform conversions in a regular fashion: ? debug mode ? stop mode 28.3.1 debug mode the qdbg bit in the module conf iguration register (qadcmcr) gove rns behavior of the qadc when the cpu enters background debug mode. when qdbg is clear, the qadc operates normally and is unaffected by cpu bac kground debug mode. see section 28.6.1, ?qadc module configuration register (qadcmcr) . when qdbg is set and the cpu enters background debug mode, the qadc fini shes any conversion in progress and then freezes. this is qadc debug m ode. depending on when debug mode is entered, the three possible queue freeze scenarios are: ? when a queue is not executing, the qadc freezes immediately. ? when a queue is executing, the qadc complete s the current conversion and then freezes. digital external external reference analog power 64-entry queue control of 10-bit conversion command words ipbus interface 10-bit analog-to-digital converter analog input mux and digital signal functions 64-entry table of 10-bit 10-bit to 16-bit result alignment (18 with external muxing) mux address triggers inputs inputs (ccws) results 8 analog channels mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) freescale semiconductor 28-3 ? if during the execution of the curr ent conversion, the queue operating mode for the active queue is changed, or a queue 2 abort occu rs, the qadc freezes immediately. when the qadc enters debug mode while a queue is active, the cu rrent ccw locati on of the queue pointer is saved. debug mode: ? stops the analog clock ? holds the periodic/inte rval timer in reset ? prevents external trigger events from being captured ? keeps all qadc regist ers and ram accessible although the qadc saves a pointer to the next ccw in the current que ue, software can force the qadc to execute a different ccw by reconfiguring the qad c. when the qadc exits debug mode, it looks at the queue operating modes, the curr ent queue pointer, and any pending tr igger events to decide which ccw to execute. 28.3.2 stop mode the qadc enters a low-power idle state whenever the qstop bit is se t or the cpu ente rs low-power stop mode. qadc stop: ? disables the analog-to-digi tal converter, effectively turning off the analog circuit ? aborts the conversion sequence in progress ? makes the data direction regist er (ddrqa), port data register s (portqa and portqb), control registers (qacr2, qacr1, and qa cr0) and the status registers (qasr1 and qasr0) read-only. only the module configuration register (qadcmcr) remains writable. ? makes the ram inaccessible, so that valid data cannot be read from ram (result word table and ccw) or written to ram (r esult word table and ccw) ? resets qacr1, qacr2, qasr0, and qasr1 ? holds the qadc periodic/interval timer in reset because the bias currents to the analog circuit ar e turned off in stop mode , the qadc requires some recovery time (t sr ) to stabilize the analog circuits. 28.4 signals the qadc uses the external signals shown in figure 28-2 . there are eight channel/port signals that can support up to 18 channels when external multiplexing is used (inclu ding internal channels). all of the channel signals also have some ge neral-purpose input or i nput/output (gpio) func tionality. in addition, there are also two analog reference signals and two analog submodule power signals. the qadc has external trigger input s and multiplexer outputs that are shared with some of the analog input signals. 28.4.1 port qa signal functions the four port qa signals can be used as analog inputs or as a bidirect ional 4-bit digital input/output port. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) 28-4 freescale semiconductor 28.4.1.1 port qa analog input signals when used as analog inputs, the four port qa signals are referred to as an[56:55, 53:52]. figure 28-2. qadc inpu t and output signals 28.4.1.2 port qa digital input/output signals port qa signals are referr ed to as pqa[4:3, 1:0] wh en used as a bidirectiona l 4-bit digital input/output port. these four signals may be used for general-purpose di gital input or digital output. port qa signals are conne cted to a digital input synchronizer during read s and may be used as general-purpose digital inputs when the applied voltages meet high-voltage input (v ih ) and low-voltage input (v il ) requirements. each port qa signal is co nfigured as an input or output by programming the port data direction register (ddrqa). the digital input signal states are read from the port qa data register (portqa) when ddrqa specifies that the signals are inputs. the di gital data in portqa is driven onto the port qa signals when the corresponding bi ts in ddrqa specify output. see section 28.6.4, ?port qa and qb data direction register (ddrqa & ddrqb) . 28.4.2 port qb signal functions the four port qb signals can be used as analog inputs or as a 4-bit digital i/o port. 28.4.2.1 port qb analog input signals when used as analog inputs, the four port qb signals are referre d to as an[3:0]. an52/ma0/pqa0 an53/ma1/pqa1 an55/etrig1/pqa3 an56/etrig2/pqa4 an0/anw/pqb0 an1/anx/pqb1 an2/any/pqb2 an3/anz/pqb3 digital analog v ssi analog power and ground internal digital power port qb converter results and control analog mux and port qb analog inputs external mux inputs digital inputs port qa analog inputs external trigger inputs external mux address outputs v ddi v ssa v dda v rh v rl analog references shared with other modules digital i/o port logic port qa mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) freescale semiconductor 28-5 28.4.2.2 port qb digital i/o signals port qb signals are referred to as pqb[3:0] when used as a 4-bit di gital input/output port. in addition to functioning as analog input signals, the port qb signals are also connected to th e input of a synchronizer during reads and may be used as general-purpose digital inputs wh en the applied voltages meet v ih and v il requirements. each port qb signal is configured as an input or output by programmi ng the port data di rection register (ddrqb). the digital input signal states are read from the port qb data re gister (portqb) when ddrqb specifies that the signals are inputs. the di gital data in portqb is driven onto the port qb signals when the corresponding bits in ddrqb specify output. see section 28.6.4, ?port qa and qb data direction register (ddrqa & ddrqb) . 28.4.3 external trigger input signals the qadc has two external tri gger signals, etrig2 and etrig1. e ach external trigger input is associated with one of the scan queues, queue 1 or queue 2. the assignment of etrig[2:1] to a queue is made by the trg bit in qadc control register 0 (qacr0). when trg = 0, etrig1 triggers queue 1 and etrig2 triggers queue 2. when trg = 1, etrig1 trigge rs queue 2 and etrig2 triggers queue 1. see section 28.6.5, ?control registers ?control registers.? 28.4.4 multiplexed address output signals in non-multiplexed mode, the qadc analog input signals are connected to an in ternal multiplexer which routes the analog signals into the internal a/d converter. in externally multiplexed mode, th e qadc allows automatic channel se lection through up to four external 4-to-1 multiplexer chips. the qadc provides a 2-bit multiplexed address output to the external multiplexer chips to allow selecti on of one of four inpu ts. the multiplexed addr ess output signals, ma1 and ma0, can be used as multiple xed address output bits or as general-purpose i/o when external multiplexed mode is not being used. ma[1:0] are used as the address inputs for up to four 4-channel multiplexer chips. because the ma[1:0] signals are digital outputs in multiplexed mode, the state of their corresponding data direction bits in ddrqa is ignored. 28.4.5 multiplexed analog input signals in external multiplexed m ode, four of the port qb signals are rede fined so that each represent four analog input channels. see table 28-1 . table 28-1. multiplexed analog input channels multiplexed analog input channels anw even numbered channels from 0 to 6 anx odd numbered channels from 1 to 7 any even numbered channels from 16 to 22 anz odd numbered channels from 17 to 23 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) 28-6 freescale semiconductor 28.4.6 voltage reference signals v rh and v rl are the dedicated input signa ls for the high and low refere nce voltages. separating the reference inputs from the power suppl y signals allows for additional ex ternal filtering, which increases reference voltage precision and stability, and subseque ntly contributes to a hi gher degree of conversion accuracy. note v rh and v rl must be set to v dda and v ssa potential, respectively. for more information, refer to section 28.9, ?signal connection considerations . 28.4.7 dedicated analog supply signals the v dda and v ssa signals supply power to th e analog subsystems of the qadc module. dedicated power is required to isolate the sens itive analog circuitry from the norm al levels of noise present on the digital power supply. 28.4.8 dedicated digital i/o port supply signal v ddh provides 5-v power to the dig ital i/o functions of qad c port qa and port qb . this allows those signals to tolerate 5 volts when configured as inputs and drive 5 volts when configured as outputs. 28.5 memory map the qadc occupies 1 kbyte, or 512 ha lf-word (16-bit) entries, of addr ess space. ten half-word registers are control, port, and stat us registers, 64 half-word entries are the ccw table, and 64 half-word entries are the result table which occupies 192 ha lf-word address locations because the result data is readable in three data alignment formats. table 28-2 is the qadc memory map. table 28-2. qadc memory map ipsbar + offset msb lsb access 1 0x19_0000 qadc module configuration register (qadcmcr) s 0x19_0002 qadc test register (qadctest) 2 s 0x19_0004 reserved 3 ? 0x19_0006 port qa data register (portqa) port qb data register (portqb) s/u 0x19_0008 port qa data direction register (ddrqa) port qb data direction register (ddrqb) s/u 0x19_000a qadc control register 0 (qacr0) s/u 0x19_000c qadc control register 1 (qacr1) s/u 0x19_000e qadc control register 2 (qacr2) s/u 0x19_0010 qadc status register 0 (qasr0) s/u 0x19_0012 qadc status register 1 (qasr1) s/u mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) freescale semiconductor 28-7 28.6 register descriptions this subsection describes the qadc registers. 28.6.1 qadc module configur ation register (qadcmcr) the qadcmcr contains bits that control qadc debug and stop modes and dete rmine the privilege level required to access most registers. 0x19_0014? 0x19_01fe reserved (3) ? 0x19_0200? 0x19_027e conversion command word table (ccw) s/u 0x19_0280? 0x19_02fe right justified, unsigned result register (rjurr) s/u 0x19_0300? 0x19_037e left justified, signed result register (ljsrr) s/u 0x19_0380? 0x19_03fe left justified, unsigned re sult register (ljurr) s/u 1 s = cpu supervisor mode access only. s/u = cpu supervisor or user mode access. user mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error. 2 access results in the module generating an access te rmination transfer error if not in test mode. 3 read/writes have no effect and the access te rminates with a transfer error exception. 15 14 13 8 field qstop qdbg ? reset 0000_0000 r/w: r/w r 76 0 field supv ? reset 1000_0000 r/w: r/w r address ipsbar + 0x19_0000, 0x19_0001 figure 28-3. qadc module confi guration register (qadcmcr) table 28-2. qadc memory map (continued) ipsbar + offset msb lsb access 1 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) 28-8 freescale semiconductor 28.6.2 qadc test re gister (qadctest) the qadctest is a reserved register . attempts to access this register outside of factory test mode will result in access privilege violation. 28.6.3 port data registers (portqa & portqb) qadc ports qa and qb are accessed th rough the 8-bit portqa and portqb. port qa signals are referred to as pqa[4:3, 1:0] when used as a bidirectional, 4-bit, input/output port. port qa can also be used for analog inputs (an[56:55, 53: 52]), external trigger inputs (etrig[2:1]), and external multiplexer a ddress outputs (ma[1:0]). port qb signals are referred to as pqb[3:0] when used as a 4-bit, digital input-only port. port qb can also be used for non-multiplexed (a n[3:0]) and multiple xed (anz, any, anx, anw) analog inputs. portqa and portqb are not initialized by reset. table 28-3. qadcmcr field descriptions bit(s) name description 15 qstop stop enable. 1 force qadc to idle state. 0 qadc operates normally. 14 qdbg debug enable. 1 finish any conversion in progress, then freeze in debug mode 0 qadc operates normally. 13?8 ? reserved, should be cleared. 7 supv supervisor/unrestricted data space. 1 all qadc registers are accessible in s upervisor mode only; user mode accesses have no effect and result in a cycle termination error. 0 only qadcmcr and qadctest require supervisor mode access; access to all other qadc registers is unrestricted 6?0 ? reserved, should be cleared. 76543210 field ? pqa4 (an56) (etrig2) pqa3 (an55) (etrig1) ?pqa1 (an53) (ma1) pqa0 (an52) (ma0) reset 000 see note 0 see note r/w: r r/w r r/w address ipsbar + 0x19_0006 figure 28-4. qadc port qa data register (portqa) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) freescale semiconductor 28-9 note: the reset value for these fields is the current signal state if ddr is an input; otherwise, they are undefined. 28.6.4 port qa and qb data dir ection register (ddrqa & ddrqb) ddrqa and ddrqb are associated with port qa and qb digital i/o signals. setting a bit in these registers configures the corresponding signal as an output. clearing a bit in these registers configures the corresponding signal as an input. during qadc initializati on, port qa and qb signals that will be used as direct or multiplexed analog i nputs must have their corresponding data direction register bits cleared. when a port qa or qb signal that is programmed as an output is se lected for analog conversion, the voltage sampled is that of the output di gital driver as influenced by the load. when the mux (externally multiplexed) bit is set in qacr0, the data directi on register settings are ignored for the bits corr esponding to pqa[1:0], and the two multip lexed address (ma[1: 0]) output signals. the ma[1:0] signals are forced to be digital outputs, regardless of their data direction setting, and the multiplexed address outputs are driven. the data return ed during a port data regist er read is the value of the ma[1:0] signals, regardless of their data direction setting. similarly, when the external trigger signals are assigned to port signals and external trigger queue operating mode is selected, the da ta direction setting for the corr esponding signals, pqa3 and/or pqa4, is ignored. the port signals are for ced to be digital inputs for etrig 1 and/or etrig2. th e data returned during a port data register read is the value of the etrig[2:1] signals, re gardless of their data direction setting. note use caution when mixing digital and an alog inputs. they should be isolated as much as possible. rise and fall times should be as large as possible to minimize ac coupling effects. 76543210 field ? pqb3 (an3) (anz) pqb2 (an2) (any) pqa1 (an1) (anx) pqa0 (an0) (anw) reset 0000 see note r/w: r r/w address ipsbar + 0x19_0007 figure 28-5. qadc port qb data register (portqb) 76543210 field ? ddqa4 ddqa3 ? ddqa1 ddqa0 reset 0000_0000 r/w: r r/w r r/w address ipsbar + 0x19_0008 figure 28-6. qadc port qa data direction register (ddrqa) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) 28-10 freescale semiconductor 28.6.5 control registers this subsection describes the qadc control registers. 28.6.5.1 qadc control register 0 (qacr0) qacr0 establishes the qadc samp ling clock (qclk) with prescaler parameter fields and defines whether external multiplexing is enabled. typical ly, these bits are written once when the qadc is initialized and not changed thereafter . the bits in this register are r ead anytime, write anytime (except during stop mode). 76543210 field ? ddqb3 ddqb2 ddqb1 ddqb0 reset 0000_0000 r/w r address ipsbar + 0x19_0009 figure 28-7. port qb data direction register (ddrqb) 15 14 13 12 11 8 field mux ? trg ? reset 0000_0000 r/w: r/w r r/w r 7 6 5 4 3210 field ? qpr6 qpr5 qpr4 qpr3 qpr2 qpr1 qpr0 reset 0001_0011 r/w: r r/w address ipsbar + 0x19_000a, 0x19_000b figure 28-8. qadc control register 0 (qacr0) table 28-4. qacr0 field descriptions bit(s) name description 15 mux externally multiplexed mode. configur es the qadc for operation in externally multiplexed mode, which affects the interpre tation of the channel numbers and forces the ma[1:0] signals to be outputs. 1 externally multiplexed, up to 18 possible channels 0 internally multiplexed, up to 8 possible channels 14?13 ? reserved, should be cleared. 12 trg trigger assignment. determines the que ue assignment of the etrig[2:1] signals. 1 etrig1 triggers queue 2; etrig2 triggers queue 1. 0 etrig1 triggers queue 1; etrig2 triggers queue 2. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) freescale semiconductor 28-11 11?7 ? reserved, should be cleared. 6?0 qpr prescaler clock divider. selects the system clock divi sor to generate the qadc clock as ta bl e 2 8 - 5 shows. the resulting qadc clock rate can be given as: where: 1 qpr[6:0] 127. if qpr[6:0] = 0, then the qpr register field value is read as a 1 and the prescaler divisor is 2. the prescaler should be selected so that the qadc clock rate is within the required f qclk range. see chapter 33, ?electrical characteristics? . table 28-5. prescaler f sys divide-by values qpr[6:0] f sys divisor qpr[6:0] f sys divisor qpr[6:0] f sys divisor qpr[6:0] f sys divisor 0000000 4 0100000 66 1000000 130 1100000 194 0000001 4 0100001 68 1000001 132 1100001 196 0000010 6 0100010 70 1000010 134 1100010 198 0000011 8 0100011 72 1000011 136 1100011 200 0000100 10 0100100 74 1000100 138 1100100 202 0000101 12 0100101 76 1000101 140 1100101 204 0000110 14 0100110 78 1000110 142 1100110 206 0000111 16 0100111 80 1000111 144 1100111 208 0001000 18 0101000 82 1001000 146 1101000 210 0001001 20 0101001 84 1001001 148 1101001 212 0001010 22 0101010 86 1001010 150 1101010 214 0001011 24 0101011 88 1001011 152 1101011 216 0001100 26 0101100 90 1001100 154 1101100 218 0001101 28 0101101 92 1001101 156 1101101 220 0001110 30 0101110 94 1001110 158 1101110 222 0001111 32 0101111 96 1001111 160 1101111 224 0010000 34 0110000 98 1010000 162 1110000 226 0010001 36 0110001 100 1010001 164 1110001 228 0010010 38 0110010 102 1010010 166 1110010 230 0010011 40 0110011 104 1010011 168 1110011 232 0010100 42 0110100 106 1010100 170 1110100 234 table 28-4. qacr0 field descriptions (continued) bit(s) name description f qclk = f sys 2(qpr[6:0] + 1) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) 28-12 freescale semiconductor 28.6.5.2 qadc control register 1 (qacr1) qacr1 is the mode control register for queue 1. this register govern s queue operating mode and the use of completion and/or pause interrupts. typically, these bits are wr itten once when the qadc is initialized and are not changed thereafter. stop mode resets this register. 0010101 44 0110101 108 1010101 172 1110101 236 0010110 46 0110110 110 1010110 174 1110110 238 0010111 48 0110111 112 1010111 176 1110111 240 0011000 50 0111000 114 1011000 178 1111000 242 0011001 52 0111001 116 1011001 180 1111001 244 0011010 54 0111010 118 1011010 182 1111010 246 0011011 56 0111011 120 1011011 184 1111011 248 0011100 58 0111100 122 1011100 186 1111100 250 0011101 60 0111101 124 1011101 188 1111101 252 0011110 62 0111110 126 1011110 190 1111110 254 0011111 64 0111111 128 1011111 192 1111111 256 15 14 13 12 11 10 9 8 field cie1 pie1 sse1 mq112 mq111 mq110 mq19 mq18 reset 0000_0000 r/w: r/w 7 0 field ? reset 0000_0000 r/w: r address ipsbar + 0x 19_000c, 0x19_000d figure 28-9. qadc control register 1 (qacr1) table 28-5. prescaler f sys divide-by values (continued) qpr[6:0] f sys divisor qpr[6:0] f sys divisor qpr[6:0] f sys divisor qpr[6:0] f sys divisor mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) freescale semiconductor 28-13 table 28-6. qacr1 field descriptions bit(s) name description 15 cie1 queue 1 completion interrupt enable. enables an interrupt request upon completion of queue 1. the interrupt request is initiat ed when the conversion is complete for the last ccw in queue 1. 1 enable queue 1 completion interrupt. 0 disable queue 1 completion interrupt. 14 pie1 queue 1 pause interrupt enable. enables an interrupt request when queue 1 enters the pause state. the interrupt request is in itiated when conversion is complete for a ccw that has the pause bit set. 1 enable the queue 1 pause interrupt. 0 disable the queue 1 pause interrupt. 13 sse1 queue 1 single-scan enable. enables a single-scan of queue 1 after a trigger event occurs. sse1 may be set during the same wr ite cycle that sets th e mq1 bits for one of the single-scan queue operating modes. t he single-scan enable bit can be written to 1 or 0, but is always read as a 0, unle ss the qadc is in test mode. the qadc clears sse1 when the single-scan is complete. 1 allow a trigger event to start queue 1 in a single-scan mode. 0 trigger events are ignored for queue 1 single-scan modes. 12?8 mq1 n selects the operating mode for queue 1. table 28-7 shows the bits in the mq1 field which enable different queue 1 operating modes. 7?0 ? reserved, should be cleared. table 28-7. queue 1 operating modes mq1[12:8] operating mode 00000 disabled mode, conversions do not occur 00001 software-triggered single -scan mode (start ed with sse1) 00010 external-trigger rising-edge single-scan mode 00011 external-trigger falling-edge single-scan mode 00100 interval timer single-scan mode: time = qclk period 2 7 00101 interval timer single-scan mode: time = qclk period 2 8 00110 interval timer single-scan mode: time = qclk period 2 9 00111 interval timer single-scan mode: time = qclk period 2 10 01000 interval timer single-scan mode: time = qclk period 2 11 01001 interval timer single-scan mode: time = qclk period 2 12 01010 interval timer single-scan mode: time = qclk period 2 13 01011 interval timer single-scan mode: time = qclk period 2 14 01100 interval timer single-scan mode: time = qclk period 2 15 01101 interval timer single-scan mode: time = qclk period 2 16 01110 interval timer single-scan mode: time = qclk period 2 17 01111 externally gat ed single-scan mode (started with sse1) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) 28-14 freescale semiconductor 28.6.5.3 qadc control register 2 (qacr2) qacr2 is the mode control register for queue 2. this register govern s queue operating mode and the use of completion and/or pause interrupts. typically, these bits are wr itten once when the qadc is initialized and not changed thereafter. qacr2 also includes a resume featur e that selects the resumption point for queue 2 after its operation is suspended by a queue 1 trigger event. the primary reason for selecting re-execution of the entire queue or subqueue is to guarantee that all samples are taken consecutively in one scan (coherency). when subqueues are not use d, queue 2 execution restarts after suspension with th e first ccw in queue 2. when a pause has previously occurr ed in queue 2 execution, queue execu tion restarts afte r suspension with the first ccw in the current subqueue. a subqueue is considered to be a stand-alone sequence of conversi ons. once a pause fl ag has been set to report subqueue completion, that subqueue is not re peated until all ccws in queue 2 are executed. for example, the resume bit can be used when th e frequency of queue 1 tri gger events prohibit queue 2 completion. if the rate of queue 1 execution is too high, it is best fo r queue 2 execution to continue with the ccw that was being converted when queue 2 was suspended. this allows queue 2 to eventually complete execution. the beginning of queue 2 is define d by programming the bq2 field in qacr2. bq2 is us ually set before or at the same time as the queue operating mode for queue 2 is selected. if bq2[6:0] 64, queue 2 has no entries, the entire ccw table is dedicated to queue 1, and ccw63 is the end-of-que ue 1. if bq2[6:0] is 0, the entire ccw table is dedicated to queue 2. a special case occurs when an operating mode is selected 10000 reserved mode 10001 software-triggered continuous-scan mode 10010 external-trigger rising-edge continuous-scan mode 10011 external-trigger falling-edge continuous-scan mode 10100 periodic timer continuous-scan mode: time = qclk period 2 7 10101 periodic timer continuous-scan mode: time = qclk period 2 8 10110 periodic timer continuous-scan mode: time = qclk period 2 9 10111 periodic timer continuous-scan mode: time = qclk period 2 10 11000 periodic timer continuous-scan mode: time = qclk period 2 11 11001 periodic timer continuous-scan mode: time = qclk period 2 12 11010 periodic timer continuous-scan mode: time = qclk period 2 13 11011 periodic timer continuous-scan mode: time = qclk period 2 14 11100 periodic timer continuous-scan mode: time = qclk period 2 15 11101 periodic timer continuous-scan mode: time = qclk period 2 16 11110 periodic timer continuous-scan mode: time = qclk period 2 17 11111 externally gated continuous-scan mode table 28-7. queue 1 operating modes (continued) mq1[12:8] operating mode mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) freescale semiconductor 28-15 for queue 1 and a trigger event occurs for queue 1 with bq2 set to 0. qu eue 1 execution starts momentarily, but is terminated after ccw0 is read. no conversions occur. the bq2[6:0] pointer may be changed dynamically to alternate between queue 2 scan sequences. a change in bq2 after queue 2 has be gun or when queue 2 has a trigger pending does not aff ect queue 2 until it is started again. for example, tw o scan sequences could be defined as follows: the first sequence starts at ccw10, with a pause after ccw11 and an end of queue (eoq) programme d in ccw15; the second sequence starts at ccw16, with a pause af ter ccw17 and an eoq programmed in ccw39. with bq2[6:0] set to ccw10 and the continuous-scan mode selected, queue execution begins. when the pause is encountered in ccw11, an interrupt service routine can reta rget bq2[6:0] to ccw16. when the end-of-queue is recognized in ccw 15, an internal retrigger event is generated and execution restarts at ccw16. when the pause software inte rrupt occurs again, bq2 can be changed back to ccw10. after the end-of-queue is recognized in ccw39, an internal retrigger event is created and execution now restarts at ccw10. if bq2[6:0] is changed while queue 1 is active, the effect of bq2[6:0] as an end- of-queue indication for queue 1 is immediate. however, bewa re of the risk of losing the end- of-queue 1 when changing bq2[6:0]. using eoq (channel 63) to end queue 1 is recommended. note if bq2[6:0] was assigned to the ccw that queue 1 is currently working on, then that conversion is completed be fore the change to bq2[6:0] takes effect. each time a ccw is read for queue 1, the ccw location is compared with the current value of the bq2[6:0] pointer to detect a possi ble end-of-queue condition. for example, if bq2[6:0] is changed to ccw3 while queue 1 is co nverting ccw2, queue 1 is terminated after the conversion is completed. however, if bq2[6:0] is cha nged to ccw1 while queue 1 is converting ccw2, the qadc would not recognize a bq2[6:0] end-of-queue condition until queue 1 executi on reached ccw1 again, presumably on the next pass through the queue. stop mode resets this register (0x007f) 15 14 13 12 11 10 9 8 field cie2 pie2 sse2 mq212 mq211 mq210 mq29 mq28 reset 0000_0000 r/w: r/w 7 6 5 4 3210 field resume bq26 bq25 bq24 bq23 bq22 bq21 bq20 reset 0111_1111 r/w: r/w address ipsbar + 0x19_000e, 0x19_000f figure 28-10. qadc control register 2 (qacr2) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) 28-16 freescale semiconductor table 28-8. qacr2 field descriptions bit(s) name description 15 cie2 queue 2 completion software interrupt enable. enables an interrupt request upon completion of queue 2. the interrupt reques t is initiated when the conversion is complete for the last ccw in queue 2. 1 enable queue 2 completion interrupt. 0 disable queue 2 completion interrupt. 14 pie2 queue 2 pause interrupt enable. enables an interrupt request when queue 2 enters the pause state. the interrupt request is in itiated when conversion is complete for a ccw that has the pause bit set. 1 enable the queue 2 pause interrupt. 0 disable the queue 2 pause interrupt. 13 sse2 queue 2 single-scan enable. enables a single-scan of queue 2 after a trigger event occurs. sse2 may be set during the same wr ite cycle that sets th e mq2 bits for one of the single-scan queue operating modes. t he single-scan enable bit can be written to 1 or 0, but is always read as a 0, unle ss the qadc is in test mode. the qadc clears sse2 when the single-scan is complete. 1 allow a trigger event to start queue 2 in a single-scan mode. 0 trigger events are ignored for queue 2 single-scan modes. 12?8 mq2 selects the operating mode for queue 2. table 28-9 shows the bits in the mq1 field which enable different queue 2 operating modes. 7 resume selects the resumption point for queue 2 after its operation is suspended due to a queue 1 trigger event. if resume is changed during the execution of queue 2, the change is not recognized until an end-of- queue condition is reached or the operating mode of queue 2 is changed. 1 after suspension, begin execution with the aborted ccw in queue 2. 0 after suspension, begin execution with the first ccw of queue 2 or the current subqueue of queue 2. 6?0 bq2 beginning of queue 2. denotes the ccw lo cation where queue 2 begins. this allows the length of queue 1 and queue 2 to va ry. the bq2 field also serves as an end-of-queue condition for queue 1. table 28-9. queue 2 operating modes mq2[12:8] operating modes 00000 disabled mode, conversions do not occur 00001 software triggered single -scan mode (started with sse2) 00010 externally triggered rising edge single-scan mode 00011 externally triggered falling edge single-scan mode 00100 interval timer single-scan mode: time = qclk period x 2 7 00101 interval timer single-scan mode: time = qclk period x 2 8 00110 interval timer single-scan mode: time = qclk period x 2 9 00111 interval timer single-scan mode: time = qclk period x 2 10 01000 interval timer single-scan mode: time = qclk period x 2 11 01001 interval timer single-scan mode: time = qclk period x 2 12 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) freescale semiconductor 28-17 28.6.6 status registers this subsection describes th e qadc status registers. 28.6.6.1 qadc status register 0 (qasr0) qasr0 contains information about the state of each queue and the cu rrent a/d conversion. the bits in this register are read anytime. fo r flag bits (cf1, pf1, cf2, pf2, tor 1, tor2), writing a 1 has no effect; writing a 0 clears the bit. for qs[9:6] and cwp, write s have no effect. stop mode resets this register. the end of a queue is identified in the following cases: ? when execution is complete on the ccw in the location prior to the one pointed to by bq2 ? when the current ccw contains the end-of-queue code (channel 63) instead of a valid channel number 01010 interval timer single-scan mode: time = qclk period x 2 13 01011 interval timer single-scan mode: time = qclk period x 2 14 01100 interval timer single-scan mode: time = qclk period x 2 15 01101 interval timer single-scan mode: time = qclk period x 2 16 01110 interval timer single-scan mode: time = qclk period x 2 17 01111 reserved mode 10000 reserved mode 10001 software triggered continuous-scan mode 10010 externally triggered rising edge continuous-scan mode 10011 externally triggered falling edge continuous-scan mode 10100 periodic timer continuous-scan mode: time = qclk period x 2 7 10101 periodic timer continuous-scan mode: time = qclk period x 2 8 10110 periodic timer continuous-scan mode: time = qclk period x 2 9 10111 periodic timer continuous-scan mode: time = qclk period x 2 10 11000 periodic timer continuous-scan mode: time = qclk period x 2 11 11001 periodic timer continuous-scan mode: time = qclk period x 2 12 11010 periodic timer continuous-scan mode: time = qclk period x 2 13 11011 periodic timer continuous-scan mode: time = qclk period x 2 14 11100 periodic timer continuous-scan mode: time = qclk period x 2 15 11101 periodic timer continuous-scan mode: time = qclk period x 2 16 11110 periodic timer continuous-scan mode: time = qclk period x 2 17 11111 reserved mode table 28-9. queue 2 operating modes (continued) mq2[12:8] operating modes mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) 28-18 freescale semiconductor ? when the currently completed ccw is in the last location of the ccw ram. once pf n is set, the queue enters the paused state and waits for a trigger event to allow queue execution to continue. however, a sp ecial case occurs when the ccw with th e pause bit set is the last ccw in a queue; queue execution is complete. the queue status becomes idle, not pause d, and both the pause and completion flags are set. another special case occurs when the queue is operating in so ftware-initiated single-scan or continuous-scan mode and a ccw paus e bit is set. the qadc will set pf n and will also automatically generate a retrigger event that restarts execution after two qclk cycles. pause mode is never entered. in externally gated single-scan and c ontinuous-scan mode, the behavior of pf n has been redefined. when the gate closes before the en d of the queue is reached, pfn is set to indicate that an incomplete scan has occurred. in single-scan mode , a resultant interrupt can be used to determine if the queue should be enabled again. in either external ly gated mode, setting pf n indicates that the results for the queue have not been collected during one scan (coherently). note: if a set ccw pause bit is encountered in either externally gated mode, the pause flag will not set, and execution continues without pausing. this has allowed for the modified behavior of pf1 in the externally gated modes. pfn is maintained by the qadc rega rdless of whethe r the corresponding interrupt is enabled. pf n may be polled to determine if the qadc has reached a pause in scanning a queue. a trigger event generated by a transi tion on the external trigger signal or by the periodic/interval timer may be captured as a trigger overrun. tor n cannot be set when the software-i nitiated single-s can mode or the software-initiated continuo us-scan mode is selected. tor n is set when a trigger event is r eceived while a queue is executing and before the scan has completed or paused. tor n has no effect on queue execution. after a trigger event has occurred for queue 1, and before the scan ha s completed or paused, additional queue 1 trigger events are not retained. such trigge r events are considered une xpected, and the qadc sets the tor n error status bit. an unexpected trigger event may denote a system overrun situation. in externally gated continuous-s can mode, the behavior of tor n has been redefined. in the case that the queue reaches an end-of-queue condition fo r the second time during an open gate, tor n is set. this is considered an overrun condition. in this case, cf1 has been set for the first end-of-queue condition and tor n sets for the second end-of-queue condition. for tor1 to set, cf2 must not be cleared before the second end-of-queue. the qs field indicates the status of queue 1 and que ue 2. following are the five queue status conditions: ? idle ?acti ve ?paused ? suspended ? trigger pending the idle state occurs when a queue is disabled, when a queue is in a reserved mo de, or when a queue is in a valid queue operating mode awaiting a trigger event to initiate queue execution. one or both queues may be in the idle state. when a queue is idle, ccws ar e not being executed for that queue, the queue is not in the pause state, and no trigger is pending. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) freescale semiconductor 28-19 a queue is in the active state when a valid queue ope rating mode is selected, wh en the selected trigger event has occurred, or when the qadc is performing a co nversion specified by a ccw from that queue. only one queue can be active at a time. one or both queues can be in the pa used state. a queue is paused wh en the previous ccw executed from that queue had the pause bit set. the qadc does not execute any ccws from the paused queue until a trigger event occurs. consequently, the qadc can service queue 2 while queue 1 is paused. only queue 2 can be in the suspended state. when a trigger event occurs on queue 1 while queue 2 is executing, the current queue 2 conversion is aborted and th e queue 2 status is repo rted as suspended. queue 2 transitions back to the active state when queue 1 becomes idle or paused. a trigger pending state is required because both queues cannot be act ive at the same time. the status of queue 2 is changed to trigger pending when a trigger event occurs for queue 2 while queue 1 is active. in the opposite case, when a trigger event occurs for queue 1 while queue 2 is active, queue 2 is aborted and the status is reported as queue 1 active, queue 2 suspende d. so due to the priority scheme, only queue 2 can be in the trigger pending state. two transition cases cause the queue 2 status to be tr igger pending before queue 2 is shown to be in the active state. when queue 1 is active and there is a trigger pend ing on queue 2, after queue 1 completes or pauses, queue 2 continues to be in the trigger pending state for a fe w clock cycles. the fleeting status conditions are: ? queue 1 idle with queue 2 trigger pending ? queue 1 paused with queue 2 trigger pending figure 28-12 displays the status conditions of the qs fi eld as the qadc goes th rough the transition from queue 1 active to queue 2 active. when a queue enters the paused state, cwp points to the ccw with the pause bit set. while in pause, the cwp value is maintained until a trigger event occurs on either queue. usually, the cwp is updated a few clock cycles before the queue status field shows that the que ue has become active. for example, a read of cwp may point to a ccw in queue 2, while the queue status fiel d shows queue 1 paused and queue 2 trigger pending. when the qadc finishes a queue scan, the cwp points to the ccw where th e end-of-queue condition was detected. therefore, when the end-of-queue c ondition is a ccw with the eoq code (channel 63), the cwp points to the ccw containing the eoq. when the last ccw in a queue is the last ccw ta ble location (ccw63), and it does not contain the eoq code, the end-of-queue is detected when the foll owing ccw is read, so the cwp points to word ccw0. finally, when queue 1 operation is terminated after a ccw is read th at is pointed to by bq2, the cwp points to the same ccw as bq2. 15 14 13 12 11 10 9 8 field cf1 pf1 cf2 pf2 tor1 tor2 qs9 qs8 reset 0000_0000 r/w: r/w r mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) 28-20 freescale semiconductor 7 6 5 4 3210 field qs7 qs6 cwp5 cwp4 cwp3 cwp2 cwp1 cwp0 reset 0000_0000 r/w: r address ipsbar + 0x19_0010, 0x19_0011 figure 28-11. qadc status register 0 (qasr0) table 28-10. qasr0 field descriptions bit(s) name description 15, 13 cf n queue completion flag. indicates that a queue scan has been completed. cf[1:2] is set by the qadc when the input channel sa mple requested by the last ccw in the queue is converted, and the result is stored in the result table. when cf n is set and queue completion interrupts are enabled (qacr n [cie n ] = 1), the qadc requests an interrupt. the interrup t request is cleared when a 0 is written to the cf1 bit after it has been read as a 1. once set, cf1 can be cleared only by a reset or by writing a 0 to it. cf[1:2] is updated by the qadc regardless of whether the corresponding interrupt is enabled. this allows polled recognition of the queue scan completion. 14, 12 pf n queue pause flag. indicates that a queue scan has reached a pause. pf[1:2] is set by the qadc when the current queue 1 ccw has the pause bit set, the selected input channel has been converted, and the result has been stored in the result table. when pf n is set and interrupts are enabled (qacr n [pie n ] = 1), the qadc requests an interrupt. the interrupt request is cleared when a 0 is written to pf n , after it has been read as a 1. once set, pf n can be cleared only by reset or by writing a 0 to it. pf1: 1 queue 1 has reached a pause or gate clos ed before end-of-queue in gated mode. 0 queue 1 has not reached a pause or gate has not closed before end-of-queue in gated mode. pf2: 1 queue 2 has reached a pause. 0 queue 2 has not reached a pause. see table 28-11 for a summary of ccw pause bit response in all scan modes. 11?10 tor n queue trigger overrun flag. indicates that an unexpected trigger event has occurred for queue 1. tor[1:2] can be set only while the queue is in the active state. once set, tor[1:2] is cleared only by a reset or by writing a 0 to it. 1 at least one unexpected queue 1 trigger event has occurred or queue 1 reaches an end-of-queue condition for the second ti me in externally gated continuous scan. 0 no unexpected queue 1 trigger events have occurred. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) freescale semiconductor 28-21 9?6 qs queue status. indicates the current cond ition of queue 1 and queue 2. the two most significant bits are associated primarily with queue 1, and the remaining two bits are associated with queue 2. because the pr iority scheme between the two queues causes the status to be interlinked, the st atus bits must be considered as one 4-bit field. table 28-12 shows the bits in the qs field and how they denote the status of queue 1 and queue 2. the queue status field is affected by qadc stop mode. because all of the analog logic and control registers are reset, the queue st atus field is reset to queue 1 idle, queue 2 idle. during debug mode, the queue status field is not modified. the queue status field retains the status it held prior to freezing. as a result, the queue status can show queue 1 active, queue 2 idle, even though neither queue is being executed during freeze. 5?0 cwp command word pointer. denotes which ccw is executing at present or was last completed. cwp is a read-only field with a va lid range of 0 to 63; write operations have no effect. during stop mode, cwp is reset to 0 bec ause the control registers and the analog logic are reset. when debug mode is entered, cw p is not changed; it points to the last executed ccw. table 28-11. ccw pause bit response scan mode queue operation pf asserts? externally triggered single-scan pauses yes externally triggered continuous-scan pauses yes interval timer trigger single-scan pauses yes interval timer continuous-scan pauses yes software-initiated single-scan continues yes software-initiated continuous-scan continues yes externally gated single-scan continues no externally gated continuous-scan continues no table 28-12. queue status qs[9:6] queue 1/queue 2 states 0000 queue 1 idle, queue 2 idle 0001 queue 1 idle, queue 2 paused 0010 queue 1 idle, queue 2 active 0011 queue 1 idle, queue 2 trigger pending 0100 queue 1 paused, queue 2 idle 0101 queue 1 paused, queue 2 paused 0110 queue 1 paused, queue 2 active table 28-10. qasr0 field descriptions (continued) bit(s) name description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) 28-22 freescale semiconductor 0111 queue 1 paused, queue 2 trigger pending 1000 queue 1 active, queue 2 idle 1001 queue 1 active, queue 2 paused 1010 queue 1 active, queue 2 suspended 1011 queue 1 active, queue 2 trigger pending 1100 reserved 1101 reserved 1110 reserved 1111 reserved table 28-12. queue status (continued) qs[9:6] queue 1/queue 2 states mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) freescale semiconductor 28-23 figure 28-12. queue status transition 28.6.6.2 qadc status register 1 (qasr1) stop mode resets this register . 15 14 13 12 11 10 9 8 field ? cwpq15 cwpq14 cwpq13 cwpq12 cwpq11 cwpq10 reset 0011_1111 r/w: r q1 idle/ q2 active q1 idle/ q2 idle q1 active/ q2 idle q1 paused/ q2 idle q1 active/ q2 suspended q1 active/ q2 paused q1 paused/ q2 active q1 idle/ q2 paused q1 paused/ q2 paused q1 active/ q2 trigger pending q1 paused/ q2 trigger pending (temporary) q2 complete delayed transition q1 pause bit set q2 trigger event q1 trigger event q1 pause bit set q1 complete q1 trigger event q1 complete delayed transition q1 complete q1 pause bit set q1 trigger event q2 complete q2 pause bit set q2 trigger event q1 trigger event q1 complete q1 trigger event q1 pause bit set q2 pause bit set q2 trigger event q1 idle/ q2 trigger pending (temporary) q1 trigger event q2 trigger event mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) 28-24 freescale semiconductor 28.6.7 conversion command word table (ccw) the ccw table is 64 half-w ord (128 byte) long ram with 10 bits of each entry implemented. the ccw table is written by the user and is not modified by the qadc. each ccw requests the conversion of one analog channel to a digital result. the ccw specifies the analog channe l number, the input sample time, and whether the queue is to pause after the current ccw. the bits in this register are read anytime (except during stop mode), write anytime (except during stop mode). 7 6 5 4 3210 field ? cwpq25 cwpq24 cwpq23 cwpq22 cwpq21 cwpq20 reset 0011_1111 r/w: r address ipsbar + 0x19_0012, 0x19_0013 figure 28-13. qadc status register 1 (qasr1) table 28-13. qasr1 field descriptions bit(s) name description 15?14 ? reserved, should be cleared. 13?8 cwpq1 queue 1 command word pointer. points to the last queue 1 ccw executed. this is a read-only field with a valid range of 0 to 63; writes have no effect. cwpq1 always points to the last executed ccw in queue 1, regardless of which queue is active. in contrast to cwp, cpwq1 is updated when a conversion result is written. when the qadc finishes a conversion in queue 1, both the result register is written and cwpq1 is updated. when queue 1 operation is terminated after a ccw is read that is pointed to by bq2, cwp points to bq2 while cwpq1 points to the last queue 1 ccw. during stop mode, cwpq1 is reset to 63, because the control registers and the analog logic are reset. when debug mode is entered, cwpq1 is not changed; it points to the last executed ccw in queue 1. 7?6 ? reserved, should be cleared. 5?0 cwpq queue 2 command word pointer. points to the last queue 2 ccw executed. this is a read-only field with a valid range of 0 to 63; writes have no effect. cwpq2 always points to the last executed ccw in que ue 2, regardless which queue is active. in contrast to cwp, cpwq2 is updated when a conversion result is written. when the qadc finishes a conversion in queue 2, both the result register is written and cwpq2 is updated. during stop mode, cwpq2 is reset to 63 be cause the control registers and the analog logic are reset. when debug mode is entere d, cwpq2 is not chan ged; it points to the last executed ccw in queue 2. 15 10 9 8 field ? p byp reset 0000_00 unaffected r/w: r r/w mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) freescale semiconductor 28-25 7 6 5 4 3210 field ist1 ist0 chan5 chan4 chan3 chan2 chan1 chan0 reset undefined r/w: r address ipsbar + 0x19_0200, 0x19_027e figure 28-14. conversion command word table (ccw) table 28-14. ccw field descriptions bit(s) name description 15?10 ? reserved, should be cleared. 9 p pause. allows subqueues to be created within queue 1 and queue 2. the qadc performs the conversion specified by the ccw with the pause bit set and then the queue enters the pause state. another trigger event causes execution to continue from the pause to the next ccw. 1 enter pause state after execution of current ccw. 0 do not enter pause state after execution of current ccw. note: the p bit does not cause the queue to pause in software-initiated modes or externally gated modes. 8 byp sample amplifier bypass. enables the amplifier bypass mode for a conversion and subsequently changes the timing. the initial sample time is eliminated, reducing the potential conversion time by two qclks. however, due to internal rc effects, a minimum final sample time of four qclks must be allowed. when using this mode, the external circuit should be of low source impedance. loading effects of the external circuitry need to be considered because the benefits of the sample amplifier are not present. 1 amplifier bypass mode enabled 0 amplifier bypass mode disabled note: byp is maintained for software compatibility but has no functional benefit on this version of the qadc. 7?6 ist input sample time. specifies the length of the sample window. the input sample time can be varied, under software control, to accommodate various input channel source impedances. longer sample times permit more accurate a/d conversions of signals with higher source impedances. table 28-15 shows the four selectable input sample times. the programmable sample time can also be used to adjust queue execution time or sampling rate by increasing the time interval between conversions. 5?0 chan selects the input channel number. the ccw channel field is programmed with the channel number corresponding to the analog input signal to be sampled and converted. the analog input signal chan nel number assignments and the signal definitions vary depending on whether the qadc multiplexed or non-multiplexed mode is used by the application. as fa r as queue scanning operations are concerned, there is no distinction between an internally or externally multiplexed analog input. table 28-16 shows the channel number assignments for non-multiplexed mode. table 28-17 shows the channel number assignments for multiplexed mode. programming the channel field to channel 63 denotes the end of the queue. channels 60 to 62 are special internal channels. when one of the special channels is selected, the sampling amplifier is not used. the value of v rl , v rh , or (v rh ?v rl )/2 is converted directly. programming any input sample time other than two has no benefit for the special internal channels except to lengthen the overall conversion time. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) 28-26 freescale semiconductor table 28-15. input sample times ist[1:0] input sample times 00 input sample time = qclk period 2 01 input sample time = qclk period 4 10 input sample time = qclk period 8 11 input sample time = qclk period 16 table 28-16. non-multiplexed channel assignments and signal designations non-multiplexed input signals channel number 1 in ccw chan field 1 all channels not listed are reserved or un implemented and return undefined results. port signal name analog signal name other functions signal type binary decimal pqb0 pqb1 pqb2 pqb3 an0 an1 an2 an3 ? ? ? ? input input input input 000000 000001 000010 000011 0 1 2 3 pqa0 pqa1 an52 an53 ? ? input/output input/output 110100 110101 52 53 pqa3 pqa4 an55 an56 etrig1 etrig2 input/output input/output 110111 111000 55 56 v rl v rh ? low reference high reference ? ? ? (v rh ?v rl )/2 input input ? 111100 111101 111110 60 61 62 ? ? end-of-queue code ? 111111 63 table 28-17. multiplexed channel assignments and signal designations multiplexed input signals channel number 1 in ccw chan field port signal name analog signal name other functions signal type binary decimal pqb0 pqb1 pqb2 pqb3 anw anx any anz ? ? ? ? input input input input 000xx0 000xx1 010xx0 010xx1 0, 2, 4, 6 1, 3, 5, 7 16, 18, 20, 22 17, 19, 21, 23 pqa0 pqa1 ? ? ma0 ma1 output output ?5 2 53 pqa3 pqa4 an55 an56 etrig1 etrig2 input/output input/output 110111 111000 55 56 v rl v rh ? low reference high reference ? ? ? (v rh ?v rl )/2 input input ? 111100 111101 111110 60 61 62 ? ? end-of-queue code ? 111111 63 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) freescale semiconductor 28-27 28.6.8 result registers the result word table is a 64 half -word (128 byte) long by 10-bit wide ram. an entry is written by the qadc after completing an analog conversion speci fied by the corresponding ccw table entry. 28.6.8.1 right-justified unsigned result register (rjurr) 28.6.8.2 left-justified signed result register (ljsrr) 1 all channels not listed are reserved or un implemented and return undefined results. 15 10 9 8 field ? result reset 0000_00 undefined r/w: r r/w 7 0 field result reset undefined r/w: r/w address ipsbar + 0x19_0280, 0x19_02fe figure 28-15. right-justified unsigned result register (rjurr) table 28-18. rjurr field descriptions bit(s) name description 15?10 ? reserved, should be cleared. 9?0 result the conversion result is unsigned, right-justified data. 15 14 8 field s result reset undefined r/w: r/w 7 0 field result reset undefined r/w: r/w address ipsbar + 0x19_0300, 0x19_037e figure 28-16. left-justified signed result register (ljsrr) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) 28-28 freescale semiconductor 28.6.8.3 left-justified unsigne d result register (ljurr) 28.7 functional description this subsection provides a functional description of the qadc. 28.7.1 result coherency the qadc supports byte and half-word reads and writes across a 16-bit data bus interface. all conversion results are stored in half-w ord registers, and the qadc does not allow more than one result register to be read at a time. for this reason, the qadc does not guarantee read coherency. table 28-19. ljsrr field descriptions bit(s) name description 15 s the left justified, signed format corresponds to a half-scale, offset binary, two?s complement data format. conversion values corresponding to 1/2 full scale, 0x0200, or higher are interpreted as positive values and have a sign bit of 0. an unsigned, right justified conversion of 0x0200 would be represented as 0x0000 in this signed register, where the sign = 0 and the result = 0. for an unsigned, right justified conversion of 0x3ff (full range or v rh ), the signed equivalent in this register would be 0x7fc0, sign = 0 and result = 0x1ff. for an unsigned, right justified conversion of 0x0000 (v rl ), the signed equivalent in this register would be 0x8000, sign = 1 and result = 0x000, a two?s complement value representing ?512. 14?6 result the conversion result is signed, left-justified data. 5?0 ? reserved, should be cleared. 15 8 field result reset undefined r/w: r/w 765 0 field result ? reset undefined r/w: r/w r address ipsbar + 0x19_0380, 0x19_03fe figure 28-17. left-justified unsigned result register (ljurr) table 28-20. ljurr field descriptions bit(s) name description 15?6 result the conversion result is unsigned, left-justified data. 5?0 ? reserved, should be cleared. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) freescale semiconductor 28-29 specifically, this means that while the qadc is operati ng, the data in the result registers can change from one read to the next. simply initia ting a read of one result register will not prevent another from being updated with a new conversion result. thus, to read any given number of result registers coherently, the que ue or queues capable of modifying these registers must be inactive. this can be gua ranteed by system operating conditions (such as, known completion of a softwa re-initiated queue single-scan or no possibility of an externally triggered/gated queue scan) or by simply disabling the queues (writing mq1 and/or mq2 to 0). 28.7.2 external multiplexing external multiplexer chips concentr ate a number of analog signals onto a few qadc inputs. this is useful for applications that need to convert more analog signals than the qadc converter can normally support. external multiplexing also puts the multiplexed chip closer to the signal so urce. this minimizes the number of analog signals that need to be shielded due to the proximity of noisy high speed digital signals at the microcontroller chip. for example, four 4-input multiple xer chips can be put at the connect or where the anal og signals first arrive on the printed circu it board. as a result, only f our analog signals need to be shielded from noise as they approach the microcontroller chip, rather than having to protect 16 analog signals. however, external multiplexer chips may introduce addi tional noise and errors if not pr operly utilized. therefore, it is necessary to maintain low ?on? resistance (the im pedance of an analog swit ch when active within a multiplexed chip) and insert a low pass filter (r/c) on the input side of the multiplexed chip. 28.7.2.1 external multiplexing operation the qadc can use from one to f our external multiplexer chips to expand the number of analog signals that may be converted. up to 16 analog channels can be converted through external multiplexer selection. the externally multiplexed channels are automatically selected from the channel field of the ccw, the same as internally multiplexed channels. the qadc is configured for the externally multiplexed mode by setting the mux bit in control register 0 (qacr0). figure 28-18 shows the maximum configuration of four external multiplexer chips connected to the qadc. the external multiplexer chip s select one of four analog inputs and connect it to one analog output, which becomes an input to the qadc. the qadc provides two multiple xed address signals, ma[1:0], to select one of four inputs. these i nputs are connected to al l four external multiplexer chips. the analog output of the four multiplexer chip s are each connected to separate qadc inputs (anw, anx, any, and anz) as shown in figure 28-18 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) 28-30 freescale semiconductor figure 28-18. external multiplexing configuration when externally multiplexed mode is selected, the qadc automatically driv es the ma output signals from the channel number in each cc w. the qadc also converts the proper input channel (anw, anx, any, and anz) by interpreting the ccw channel numbe r. as a result, up to 16 externally multiplexed channels appear to the conversion queues as directly connected signals . user software simply puts the channel number of externally mu ltiplexed channels into ccws. an52/ma0/pqa0 an53/ma1/pqa1 an55/etrig1pqa3 an56/etrig2/pqa4 an0/anw/pqb0 an1/anx/pqb1 an2/any/pqb2 an3/anz/pqb3 port qb port qa an0 an2 an4 an6 an1 an3 an5 an7 an16 an18 an20 an22 an17 an19 an21 an23 mux mux mux mux mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) freescale semiconductor 28-31 figure 28-18 shows that the two ma signals may also be analog input signals. when external multiplexing is selected, none of the ma signals can be used for analog or di gital inputs. they become multiplexed address outputs and are unaffected by ddrqa[1:0]. 28.7.2.2 module version options the number of available analog ch annels varies, depending on whether external multiplexing is used. a maximum of eight analog channels are supported by the internal multiplexing circuitry of the converter. table 28-21 shows the total number of analog input channe ls supported with 0 to 4 external multiplexer chips. 28.7.3 analog subsystem this section describes the qadc analog subsystem, which includes th e front-end analog multiplexer and analog-to-digital converter. 28.7.3.1 analog-to-digital converter operation the analog subsystem consists of th e path from the input signals to the a/d converter block. signals from the queue control logic are fed to the multiplexer and state machine. the end-of-conversion (eoc) signal and the successive approximati on register (sar) reflect th e result of the conversion. figure 28-19 shows a block diagram of the qadc analog subsystem. table 28-21. analog input channels number of analog inpu t channels available directly connected + external multiplexed = total channels 1 , 2 1 the external trigger inputs are not shared with two analog input signals. 2 when external multiplexing is used, two input channels are configured as multiplexed address outputs, and for each external multiplexer chip, one input channel is a multiplexed analog input. no external mux one external mux two external muxes three external muxes four external muxes 8 5 + 4 = 9 4 + 8 = 12 3 + 12 = 15 2 + 16 = 18 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) 28-32 freescale semiconductor figure 28-19. qadc analog subsystem block diagram 28.7.3.2 conversion cycle times total conversion time is made up of initial sample time, final sample time, and resolution time. initial sample time refers to the time during which the select ed input channel is coupled through the sample buffer amplifier to the sample capacitor. the sample buffer is used to quick ly reproduce its input signal on the sample capacitor and minimize char ge sharing errors. during the fina l sampling period the amplifier is bypassed, and the multiplexer input ch arges the sample capacitor array directly for improved accuracy. during the resolution period, the voltage in the sample capacitor is converted to a digital value and stored in the sar as shown in figure 28-20. initial sample time is fixed at tw o qclk cycles. final sample time can be 2, 4, 8, or 16 qclk cycles, depending on the value of the ist field in th e ccw. resolution time is 10 qclk cycles. a conversion requires a minimum of 14 qclk cycles (7 s with a 2.0-mhz qclk). if the maximum final sample time period of 16 qclks is selected, the total conversion time is 28 qclks or 14 s (with a 2.0-mhz qclk). pqa4 pqa0 pqb3 pqb0 v dda v ssa v rh v rl qclk start conv end of conv rst stop sar[9:0] 10-bit a/d converter input analog power 2 ist sample compar- successive ator bias circuit approximation register buffer 10 10 chan[5:0] csamp 10 chan. decode & mux 16:1 signals from/to queue control logic 16 state machine & logic power- down internal channel decode sar timing 4 6 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) freescale semiconductor 28-33 figure 28-20. conversion timing if the amplifier bypass mode is en abled for a conversion by setting the amplifier bypass (byp) field in the ccw, the timing changes to that shown in figure 28-21 . see section 28.6.7, ?conversion command word table (ccw) for more information on the byp field. the initial sample time is eliminated, reducing the potential conversion time by two qclks. when using the bypass mode, the extern al circuit should be of low source impedance (typi cally less than 10 k ). also, the loading effects on the external circuitry of the qadc need to be considered, because the benef its of the sample amplifier are not present. note because of internal rc time constant s, use of a two qclk sample time in bypass mode will cause serious errors when operating the qadc at high frequencies. figure 28-21. bypass mode conversion timing 28.7.3.3 channel decode and multiplexer the internal multiplexer selects one of the eight analog input signals fo r conversion. the selected input is connected to the sample buffer amplif ier or to the sample capacitor. th e multiplexer also includes positive and negative stress pr otection circuitry, which prevents deselect ed channels from affecting the selected channel when current is injected into the deselected channels. 28.7.3.4 sample buffer the sample buffer is used to raise the effective i nput impedance of the a/d c onverter, so that external factors (higher bandwidth or higher im pedance) are less critical to accu racy. the input voltage is buffered onto the sample capacitor to re duce crosstalk between channels. 28.7.3.5 comparator the comparator output feeds into the sar, which accumulates the a/d conversi on result sequentially, beginning with the msb. sample time successive approximation resolution sequence qclk buffer sample time: 2 cycles final sample time: n cycles (2,4,8,16) resolution time: 10 cycles sample time successive approximation resolution sequence qclk sample time: n cycles (2,4,8,16) resolution time: 10 cycles mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) 28-34 freescale semiconductor 28.7.3.6 bias the bias circuit is controlled by the stop signal to power-up and power-down al l the analog circuits. 28.7.3.7 successive approximation register (sar) the input of the sar is connected to the comparator output. the sar sequentially receives the conversion value one bit at a time, starting with the msb. after accumulating the 10 bits of the conversion result, the sar data is transferred to the appropriate result location, where it may be read by user software. 28.7.3.8 state machine the state machine generates all timing to perform an a/d conversion. an intern al start-conversion signal indicates to the a/d convert er that the desired channe l has been sent to the mux. ccw[ist[1:0]] denotes the desired sample time. ccw[byp] determines whether to bypass the sample amplifier. once the end of conversion has been reached a signal is sent to the queue control logic indicating that a result is available for storage in the result ram. 28.8 digital control subsystem the digital control subsystem incl udes the control logic to sequence the conversion activity, the system clock and periodic/interval timer, control and status registers, the conversion command word table ram, and the result word table ram. the central element for control of qadc conversions is the 64-entr y conversion command word (ccw) table. each ccw specifies the conversion of one i nput channel. depending on th e application, one or two queues can be established in the cc w table. a queue is a scan sequence of one or more input channels. by using a pause mechanism, subque ues can be created in the two que ues. each queue can be operated using one of several different sc an modes. the scan modes for queue 1 and queue 2 are programmed in control registers qacr1 and qacr2. once a queue has been started by a trigge r event (any of the ways to cause the qadc to begin executing the ccws in a queue or subqueue), the qadc performs a sequence of conversions and places the results in the result word table. 28.8.1 queue priority timing examples this subsection describes the qadc priority sche me when trigger events on two queues overlap or conflict. 28.8.1.1 queue priority queue 1 has priority over queue 2 execution. these cases show the condi tions under which queue 1 asserts its priority: ? when a queue is not active, a tr igger event for queue 1 or queue 2 causes the corresponding queue execution to begin. ? when queue 1 is active and a tr igger event occurs for queue 2, que ue 2 cannot begin execution until queue 1 reaches completion or the paused state. the status register records the trigger event by reporting the queue 2 stat us as trigger pending. additional tri gger events for queue 2, which occur before execution can begin, are flagged as trigger overruns. ? when queue 2 is active and a trigger event occu rs for queue 1, the curren t queue 2 conversion is aborted. the status register repor ts the queue 2 status as suspe nded. any trigger events occurring for queue 2 while it is suspended are flagge d as trigger overruns. once queue 1 reaches the mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) freescale semiconductor 28-35 completion or the paused state, queue 2 begins executing again. the pr ogramming of the resume bit in qacr2 determines which ccw is executed in queue 2. ? when simultaneous trigger events occur for queue 1 and queue 2, queue 1 begins execution and the queue 2 status is ch anged to trigger pending. ? when subqueues are paused the pause feature can be used to divide queue 1 and/or queue 2 into mult iple subqueues. a subqueue is defined by setting the pause bit in the last ccw of the subqueue. figure 28-22 shows the ccw format and an example of using pause to create subqueues. queue 1 is shown with four ccws in each subqueue a nd queue 2 has two ccws in each subqueue. the operating mode selected for queue 1 determines what type of tri gger event causes the execution of each of the subqueues within queue 1. similarly, th e operating mode for queue 2 determines the type of trigger event required to execute e ach of the subqueues within queue 2. for example, when the external trigger rising edge c ontinuous-scan mode is select ed for queue 1, and there are six subqueues within queue 1, a se parate rising edge is required on the external trigger signal after every pause to begin the executi on of each subqueue (refer to figure 28-22 ). the choice of single-scan or continuous-scan applies to the full queue , and is not applied to each subqueue. once a subqueue is initiated, each ccw is executed sequentially until the last ccw in the subqueue is executed and the pause state is en tered. execution can only continue with the next ccw, which is the beginning of the next subqueue. a subqueue cannot be executed a sec ond time before the overall queue execution has been completed. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) 28-36 freescale semiconductor figure 28-22. qadc queue operation with pause trigger events which occur during th e execution of a subqueue are ignored, but the trigger overrun flag is set. when a continuous-scan mode is selected, a trigger event occurri ng after the comple tion of the last subqueue (after the queue co mpletion flag is set) , causes the execution to cont inue with the first subqueue, starting with the first ccw in the queue. when the qadc encounters a ccw with the pause bit set, the que ue enters the paused state after completing the conversi on specified in the ccw with the pause b it. the pause flag is set in qasr0, and a pause interrupt may be requested. the status of the queue is shown to be paused, indicating completion of a subqueue. the qadc then wait s for another trigger event to again begin execution of the next subqueue. 28.8.1.2 queue priority schemes because there are two c onversion command queues and only one a/d converter, a priority scheme determines which conversion occurs. each queue has a va riety of trigger events th at are intended to initiate conversions, and they can occur asynchronously in relation to each other and other conversions in progress. for example, a queue can be idle awaiting a trigger event; a trigger ev ent can have occurred, but the first conversion has not started; a conversion can be in progres s; a pause condition can exist awaiting another trigger event to c ontinue the queue; and so on. beginning of queue 1 00 channel select, sample, hold, a/d conversion conversion command result word table 0 pause word (ccw) table 0 0 1 0 0 0 1 0 pause 00 p 0 pause 0 0 1 0 1 0 1 0 pause p end of queue 1 beginning of queue 2 bq2 pause pause end of queue 2 p 1 0 63 63 ? ? ? ? ? ? ? ? ? ? ? ? mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) freescale semiconductor 28-37 the following paragraphs and figures outline the prioritizing criteria us ed to determine which conversion occurs in each overlap situation. note each situation in figure 28-23 through figure 28-33 is labeled s1 through s19. in each diagram, time is shown increasing from left to right. the execution of queue 1 and queue 2 (q 1 and q2) is shown as a string of rectangles representing the executio n time of each ccw in the queue. in most of the situations, th ere are four ccws (labeled c1 to c4) in both queue 1 and queue 2. in some of the situati ons, ccw c2 is presumed to have the pause bit set, to show the similari ties of pause and end-of-queue as terminations of queue execution. trigger events are described in table 28-22 . when a trigger event causes a ccw execution in progress to be aborte d, the aborted conversion is shown as a ragged end of a shortened ccw rectangle. the situation diagrams also show when key status bits are set. table 28-23 describes the status bits. below the queue execution flows are th ree sets of blocks that show th e status information that is made available to the user. the first two rows of status blocks show the condition of each queue as: ? idle ?active ?pause ? suspended (queue 2 only) ? trigger pending the third row of status bloc ks shows the 4-bit qs status register field that enc odes the condition of the two queues. two transition status cases, qs = 0011 and qs = 0111, are not shown b ecause they exist only very briefly between stable status conditions. table 28-22. trigger events trigger events t1 events that trigger queue 1 execution (external trigger, software-initiated single-scan enable bit, or completion of the previous continuous loop) t2 events that trigger queue 2 execution (external trigger, software-initiated single-scan enable bit, timer period/interval expired, or completion of the previous continuous loop) table 28-23. status bits bit function cf flag set when the end of the queue is reached pf flag set when a queue completes execution up through a pause bit trigger overrun error (tor) set when a new trigger event occurs before the queue is finished servicing the previous trigger event mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) 28-38 freescale semiconductor the first three examples in figure 28-23 through figure 28-25 (s1, s2, and s3) show what happens when a new trigger event is recognized be fore the queue has completed servic ing the previous trigger event on the same queue. in situation s1 ( figure 28-23 ), one trigger event is being recognized on each queue while that queue is still working on the previously recognized trigger event. the trigger overrun er ror status bit is set, and the premature trigger event is otherwise ignored. a trigger event that occurs before the servicing of the previous trigger event is through does not disturb the queue execution in progress. figure 28-23. ccw priority situation 1 in situation s2 ( figure 28-24 ), more than one trigger event is recognized before servicing of a previous trigger event is complete. the trigge r overrun bit is again set, but the a dditional trigger events are otherwise ignored. after the queue is complete, the first newly detected trigger even t causes queue execution to begin again. when the trigger even t rate is high, a new trigger event ca n be seen very soon after completion of the previous queue, leaving little time to retrieve th e previous results. also, when trigger events are occurring at a high rate for queue 1, the lower priori ty queue 2 channels may not get serviced at all. figure 28-24. ccw priority situation 2 situation s3 ( figure 28-25 ) shows that when the pause feature is used, the trigge r overrun error status bit is set the same way and that queue execution continues unchanged. q1: q2: qs: idle idle active idle 0000 1000 0000 0010 0000 tor1 t1 t1 q1: c1 c2 c3 c4 cf1 c1 c2 c3 c4 tor2 t2 t2 q2: cf2 idle active t1 active idle q1: q2: qs: idle active idle active idle 1000 1000 0000 0010 0000 c1 c2 c3 c4 tor2 t2 t2 q2: cf2 idle c1 c2 c3 c4 t1 cf1 c1 c2 c3 c4 tor1 t1 q1: cf1 tor1 t1 tor1 t1 tor2 t2 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) freescale semiconductor 28-39 figure 28-25. ccw priority situation 3 the next two situations consider trigger events that occur for the lower priority queue 2, while queue 1 is actively being serviced. situation s4 ( figure 28-26 ) shows that a queue 2 trigger event is recognized while queue 1 is active is saved, and as soon as queue 1 is fi nished, queue 2 servicing begins. figure 28-26. ccw priority situation 4 situation s5 ( figure 28-27 ) shows that when multiple queue 2 trigger events ar e detected while queue 1 is busy, the trigger overrun erro r bit is set, but queue 1 execution is not disturbed. situation s5 also shows that the effect of queue 2 trigger events during queue 1 execution is the same when the pause feature is used for either queue. pause q1: q2: qs: idle active idle active idle 1000 0110 0001 0010 active 0000 idle c1 c2 t1 t1 q1: tor1 pf1 c1 c2 0000 q2: 0100 tor2 pf2 t2 t2 0101 c3 c4 t1 t1 tor1 cf1 active pause 1001 c3 c4 cf2 t2 t2 tor2 q1: q2: qs: idle idle active idle 0000 1000 0010 active 0000 c1 c2 c3 c4 t1 q1: cf1 q2: c1 c2 c3 c4 t2 cf2 idle 1011 triggered mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) 28-40 freescale semiconductor figure 28-27. ccw priority situation 5 the remaining situations, s6 through s11, show the impact of a queue 1 trigger event occurring during queue 2 execution. because queue 1 ha s higher priority, the conversion ta king place in queue 2 is aborted so that there is no variable latency time in responding to queue 1 trigger events. in situation 6 ( figure 28-28 ), the conversion initiated by the second ccw in queue 2 is aborted just before the conversion is complete, so that queue 1 execution can begin. queue 2 is considered suspended. after queue 1 is finished, queue 2 starts over with the first ccw, when the resume control bit is set to 0. situation s7 ( figure 28-29 ) shows that when pause operation is not used with queue 2, queue 2 suspension works the same way. figure 28-28. ccw priority situation 6 q1: q2: qs: idle idle idle 0000 1000 0010 active 0000 c1 c2 t1 q1: c1 c2 pf2 c3 c4 c3 c4 cf2 idle 1011 trig q2: t2 t2 pf1 pau s e active pau s e tor2 t2 t2 cf1 tor2 t1 active trig 0110 active active 0101 1001 1011 idle q1: q2: qs idle idle 0000 1000 active c1 c2 t1 q1: c1 c3 c4 idle q2: pf1 pau s e active cf1 t1 active suspend 0100 active active 0110 1010 c1 c2 c3 c4 cf2 t2 0010 0000 resume = 0 c2 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) freescale semiconductor 28-41 . figure 28-29. ccw priority situation 7 situations s8 and s9 ( figure 28-30 and figure 28-31 ) repeat the same two situations with the resume bit set to a 1. when the resume bi t is set, following suspension, que ue 2 resumes execution with the aborted ccw, not the fi rst ccw, in the queue. figure 28-30. ccw priority situation 8 t1 pau s e q1: q2: qs: idle active idle active idle 0010 0110 1010 0010 active 0000 idle q1: pf1 c1 c2 0000 1010 active 0110 c1 q2: t2 c1 pf2 t1 c3 c4 cf1 c3 cf2 suspend pause suspend t2 c1 c3 c2 active act 0101 c4 idle q1: q2: qs: idle idle 0000 1000 0010 active c1 c2 t1 q1: c1 c3 c4 idle q2: pf1 pau s e active cf1 t1 active suspend 0100 active active 0110 1010 c2 c3 c4 cf2 t2 0000 resume=1 c2 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) 28-42 freescale semiconductor figure 28-31. ccw priority situation 9 situations s10 and s11 ( figure 28-32 and figure 28-33 ) show that when an a dditional trigger event is detected for queue 2 while the queue is suspended, the trigger overrun error bit is set, the same as if queue 2 were being executed when a new trigger event occurs. trigger overru n on queue 2 thus allows the user to know that queue 1 is taking up so much qadc time that queue 2 trigger events are being lost. figure 28-32. ccw priority situation 10 t1 pau s e q1: q2: qs: idle active idle act idle 0010 0110 1010 0010 active 0000 idle q1: pf1 c1 c2 0000 1010 0101 active pause 0110 c1 q2: t2 c2 pf2 t1 c3 c4 cf1 c4 cf2 suspend act active suspend t2 c3 c1 resume=1 c2 c4 t1 t1 pause q1: q2: qs: idle active idle active idle 0010 0110 1010 0010 active 0000 idle q1: pf1 c1 c2 0000 1010 0101 active pause 0110 q2: t2 pf2 c1 c2 c3 c4 cf1 c3 c4 cf2 t2 c3 suspend active c1 act suspend t2 tor2 t2 tor2 resume = 0 c2 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) freescale semiconductor 28-43 figure 28-33. ccw priority situation 11 the previous situations c over normal overlap conditions that arise with asynchronous trigger events on the two queues. an additional c onflict to consider is that the freeze condition can arise while the qadc is actively executing ccws. the c onventional use for the debug mode is for software/hardware debugging. when the cpu enters background debug mode, peri pheral modules can cease operation. when freeze is detected, the qadc comple tes the conversion in progr ess, unlike the abort that occurs when queue 1 suspends queue 2. after the freeze condition is removed, the qadc cont inues queue execution with the next ccw in sequence. trigger events that occur during fr eeze are not captured. when a trigge r event is pending for queue 2 before freeze begins, that tr igger event is remembered when the freeze is passed. similarly, when freeze occurs while queue 2 is suspended, after freeze, queue 2 re sumes execution as soon as queue 1 is finished. situations 12 through 19 ( figure 28-34 to figure 28-41 ) show examples of all of the freeze situations. figure 28-34. ccw freeze situation 12 t1 t1 c3 c4 cf1 pause q1: q2: qs: idle active idle act idle 0010 0110 1010 0010 active 0000 idle q1: pf1 c1 c2 0000 1010 0101 active pause 0110 q2: t2 suspend act c1 active suspend t2 tor2 t2 tor2 c2 pf2 c4 cf2 t2 c3 c2 c4 resume = 1 c3 c4 cf1 c1 c2 t1 q1: freeze mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) 28-44 freescale semiconductor figure 28-35. ccw freeze situation 13 figure 28-36. ccw freeze situation 14 figure 28-37. . ccw freeze situation 15 figure 28-38. ccw freeze situation 16 c1 c2 t2 q2: cf2 c3 c4 freeze c1 c2 t1 q1: cf1 c3 c4 freeze t1 t1 t2 t2 triggers ignored c1 c2 t2 q2: cf2 c3 c4 freeze t2 t2 t1 t1 triggers ignored c1 c2 t1 q1: cf1 c3 c4 freeze t1 t1 pf1 triggers ignored mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) freescale semiconductor 28-45 figure 28-39. ccw freeze situation 17 figure 28-40. ccw freeze situation 18 figure 28-41. ccw freeze situation 19 28.8.2 boundary conditions the queue operation boundary conditions are: ? the first ccw in a queue speci fies channel 63, the end-of-queue (eoq) code. th e queue becomes active and the first ccw is rea d. the end-of-queue is recognized, the completion flag is set, and the queue becomes idle. a conversion is not performed. ? bq2 (beginning of queue 2) is set at the end of the ccw table (63) and a trigger event occurs on queue 2. the end-of-queue condition is recognized, a conversion is performed, the completion flag is set, and the queue becomes idle. ? bq2 is set to ccw0 and a trigger event occurs on queue 1. after readi ng ccw0, the end-of-queue condition is recognized, the completi on flag is set, and the queue b ecomes idle. a conversion is not performed. c1 c2 t2 q2: cf2 c3 c4 freeze t2 t2 pf2 triggers ignored c1 c2 t1 q1: cf1 c3 c4 freeze t2 c1 c2 q2: c3 cf2 c4 trigger captured, response delayed after freeze c1 c2 t1 q1: cf1 c4 freeze cf2 c4 c1 c2 t2 q2: c3 c3 c4 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) 28-46 freescale semiconductor ? bq2 (beginning of queue 2) is set beyond the end of the ccw ta ble (64?127) and a trigger event occurs on queue 2. the end-of-que ue condition is recognized immedi ately, the completion flag is set, and the queue b ecomes idle. a conversi on is not performed. note multiple end-of-queue conditions ma y be recognized simultaneously, although there is no change in qadc behavior. for example, if bq2 is set to ccw0, ccw0 contains the eoq c ode, and a trigger event occurs on queue 1, the qadc reads ccw0 and dete cts both end-of-queue conditions. the completion flag is set and queue 1 becomes idle. boundary conditions also exist for co mbinations of pause and end-of-que ue. one case is when a pause bit is in one ccw and an end-of-que ue condition is in the next ccw. the conversion specified by the ccw with the pause bit set completes normally. the paus e flag is set. however, because the end-of-queue condition is recognized, the completion flag is also set and the que ue status becomes idle, not paused. examples of this situation include: ? the pause bit is set in ccw5 and the channel 63 (eoq) code is in ccw6. ? the pause is in ccw63. ? during queue 1 operation, the pause bit is set in ccw20 and bq2 points to ccw21. another pause and end-of -queue boundary condition occurs when the pause and an end-of-queue condition occur in the same ccw. both the pa use and end-of-queue c onditions are recognized simultaneously. the end-of-queue condition has precedence so a conversion is not performed for the ccw and the pause flag is not set. the qadc sets the completion flag and the queue status becomes idle. examples of this situation are: ? the pause bit is set in ccw10 and eoq is programmed into ccw10. ? during queue 1 operation, the pause bit set in ccw32, which is also bq2. 28.8.3 scan modes the qadc queuing mechanism allows application software to util ize different requirements for automatically scanning input channels. in single-scan mode, a single pass through a sequence of conversions defined by a queue is performed. in continuous-scan mode, multiple passes through a sequenc e of conversions de fined by a queue are executed. the possible modes are: ? disabled mode and reserved mode ? software-initiated single-scan mode ? externally triggered single-scan mode ? externally gated single-scan mode ? interval timer single-scan mode ? software-initiated continuous-scan mode ? externally triggered continuous-scan mode ? externally gated continuous-scan mode ? periodic timer continuous-scan mode the following paragraphs describe single-scan and continuous-scan operations. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) freescale semiconductor 28-47 28.8.4 disabled mode when disabled mode is selected, the queue is not act ive. trigger events cannot initiate queue execution. when both queue 1 and queue 2 are di sabled, there is no possibility of encountering wait states when accessing ccw table and result ram. when both queues are disabled, it is safe to change the qclk prescaler values. 28.8.5 reserved mode reserved mode is available for futu re mode definitions. when reserved mode is selected, the queue is not active. the behavior is the same as disabled mode. 28.8.6 single-scan modes a single-scan queue operating mode is used to execute a single pa ss through a sequence of conversions defined by a queue. by programming the mq1 field in qacr1 or the mq2 field in qacr2, these modes can be selected: ? software-initiated single-scan mode ? externally triggered single-scan mode ? externally gated single-scan mode ? interval timer single-scan mode note queue 2 cannot be programmed for ex ternally gated single-scan mode. in all single-scan que ue operating modes, qu eue execution is enabled by writi ng the single-scan enable bit to a 1 in the queue?s control regi ster. the single-scan enable bits , sse1 and sse2, are provided for queue 1 and queue 2, respectively. until a queue?s single-scan enable bit is set, any tr igger events for that queue are ignored. the single-scan enable bit may be set to a 1 during the same write cycle that selects the single-scan queue operating mode. the single-scan enable bit can be written only to 1, but will always read 0. once set, writing the single-scan enable bit to 0 has no effect. only the qadc can clear th e single-scan enable bit. the completion flag, completion interrupt, or queue status is used to determine when the queue has completed. after the single-scan enable bit is set, a trigger event caus es the qadc to begin execution with the first ccw in the queue. the single-scan enable bit remains set until the queue is completed. after the queue reaches completion, the qadc resets the single-scan enable bit to 0. wr iting the single-scan enable bit to a 1 or a 0 before the queue scan is complete has no effect; however, if the queue operating mode is changed, the new queue operating mode and the value of the single-scan enable bi t are recognized immediately. the conversion in progress is aborted, and th e new queue operating mode takes effect. in software-initiated single-scan mode, writing a 1 to the single-s can enable bit causes the qadc to generate a trigger event internally , and queue execution begi ns immediately. in th e other single-scan queue operating modes, once the single-scan enable bit is written, the selected trigger event must occur before the queue can start. the single-scan enable bit allo ws the entire queue to be scanned once. a trigger overrun is captured if a tr igger event occurs during queue execution in an edge-sensitive external trigger mode or a periodic/interval timer mode. in the interval timer single-scan m ode, the next expiration of the timer is the trigger event for the queue. after queue execution is complete, th e queue status is shown as idle. th e queue can be restarted by setting the single-scan enable bit to 1. queue execu tion begins with the fi rst ccw in the queue. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) 28-48 freescale semiconductor 28.8.6.1 software-initia ted single-scan mode software can initiate the execution of a scan se quence for queue 1 or 2 by se lecting software-initiated single-scan mode and writing the single-scan enable bit in qacr1 or qacr2. a trigger event is generated internally and the qadc immediately begins execution of the first ccw in the queue. if a pause occurs, another trigger event is generated internally , and then execution continues without pausing. the qadc automatically performs the conversions in the queue unt il an end-of-queue condition is encountered. the queue remains idle until the single -scan enable bit is again set. while the time to internally generate and act on a trigger event is very short, the queue stat us field can be read as momentarily indicating that the queue is paused. the trigger ove rrun flag is never set while in software-initiated single-scan mode. the software-initiated single- scan mode is useful when: ? complete control of que ue execution is required ? there is a need to easily alternate between several queue sequences 28.8.6.2 externally triggered single-scan mode the externally triggered single-scan mode is availabl e on both queue 1 and queue 2. both rising and falling edge triggered modes are av ailable. a scan must be enabled by se tting the single-scan enable bit for the queue. the first external trigger edge ca uses the queue to be executed one time. each ccw is read and the indicated conversions are performe d until an end-of-queue condition is encountered. after the queue is completed, the qadc clears the single-scan enable bit. the single-scan enable bit can be written again to allow another scan of the queue to be in itiated by the next ex ternal trigger edge. the externally triggered single-scan mode is useful when the input trigger rate can exceed the queue execution rate. analog samp les can be taken in sync with an external even t, even though application software does not require data ta ken from every edge. externally triggered single-s can mode can be enabled to get one set of data and, at a later time, be enabled again for the next set of samples. when a pause bit is encountered during externally triggered single-scan mode , another trigger event is required for queue execution to cont inue. software involvement is not required for queue execution to continue from the paused state. 28.8.6.3 externally gated single-scan mode the qadc provides external gating fo r queue 1 only. when externally ga ted single-scan m ode is selected, the input level on the associated exte rnal trigger signal enables and disa bles queue execution. the polarity of the external gate signal is fixed so that only a high level opens th e gate and a low level closes the gate. once the gate is open, each ccw is read and the indicated conversions are performed until the gate is closed. queue scan must be enabled by setting the single-scan enable bit fo r queue 1. if a pause is encountered, the pause flag does not set, and execution continues without pausing. while the gate is open, queue 1 executes one time. each ccw is read and the indicated conversions are performed until an end-of-queue c ondition is encountered. when queue 1 completes, the qadc sets the completion flag (cf1) and clears the si ngle-scan enable bit. set the single-scan enable bit again to allow another scan of queue 1 to be in itiated during the next open gate. if the gate closes before queue 1 completes execu tion, the current ccw comple tes, execution of queue 1 stops, the single-scan enable bit is cleared, and the pf1 bit is set. the cwpq1 field can be read to determine the last valid conversion in the queue. the single-scan enable bit must be set again and the pf1 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) freescale semiconductor 28-49 bit should be cleared before another scan of queue 1 is initiated during the next open gate. the start of queue 1 is always the first ccw in the ccw table. because the gate level is only sampled after each conversion duri ng queue execution, closing the gate for a period less than a conversion time interval does not guarantee the closure will be captured. 28.8.6.4 interval timer single-scan mode both queues can use the periodic/inte rval timer in a single-scan queue operating mode. th e timer interval can range from 2 7 to 2 17 qclk cycles in binary multiples. when the interval timer single-scan mode is selected and the single-scan enable bit is set in qacr1 or qacr2, th e timer begins counting. when the time interval elapses, an internal trigger event is generated to start the queue and the qadc begins execution with the first ccw. the qadc automatically performs the conversions in the queue until a pa use or an end-of-queue condition is encountered. when a pa use occurs, queue execution stops until the timer interval elapses again, and queue execution continues. when queue execution reaches an end- of-queue situation, the single-scan enable bit is cleared. se t the single-scan enable bit again to allow another scan of the queue to be initiated by the interval timer. the interval timer generates a tri gger event whenever the time interv al elapses. the trigger event may cause queue execution to continue following a pause or may be cons idered a trigger overrun. once queue execution is completed, the single-scan enable bit must be set again to allow the timer to count again. normally, only one queue is enabled for interval time r single-scan mode, and the timer will reset at the end-of-queue. however, if both queue s are enabled for either single-sc an or continuous interval timer mode, the end-of-queue cond ition will not reset the timer while the ot her queue is active. in this case, the timer will reset when both queues have reached end-of-queue. see section 28.8.9, ?periodic/interval timer for a definition of interv al timer reset conditions. the interval timer single-scan mode can be used in a pplications that need cohe rent results. for example: ? when it is necessary that all samp les are guaranteed to be taken during the same scan of the analog signals ? when the interrupt rate in the periodic ti mer continuous-scan mode would be too high ? in sensitive battery applications, where the interv al timer single-scan mode uses less power than the software-initiated continuous-scan mode 28.8.7 continuous-scan modes a continuous-scan queue operating mode is used to execute mult iple passes through a sequence of conversions defined by a queue. by programming the mq1 field in qac r1 or the mq2 field in qacr2, these modes can be selected: ? software-initiated continuous-scan mode ? externally triggered continuous-scan mode ? externally gated continuous-scan mode ? periodic timer continuous-scan mode note queue 2 cannot be programmed for exte rnally gated continuous-scan mode. when a queue is programmed for a c ontinuous-scan mode, the single-scan enable bit in the queue control register does not have any meaning or effect. as soon as the queue operati ng mode is programmed, the selected trigger event can initiate queue execution. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) 28-50 freescale semiconductor in the case of software-initiated continuous-scan mode , the trigger event is gene rated internally and queue execution begins immediately. in th e other continuous-scan queue operat ing modes, the selected trigger event must occur before the queue can start. a trigge r overrun is captured if a trigger event occurs during queue execution in the externally triggered continuous-scan mode or the periodic timer continuous-scan mode. after queue execution is complete, the queue status is shown as id le. because the c ontinuous-scan queue operating modes allow the entire queue to be scanned multiple times, software involvement is not needed for queue execution to continue from the idle stat e. the next trigger event cau ses queue execution to begin again, starting with the first ccw in the queue. note in continuous-scan modes, all samples are guaranteed to be taken during one pass through the queue (coherently ), except when a queue 1 trigger event halts queue 2 exec ution. the time between consecutive conversions has been designed to be consistent. however, for queues that end with a ccw containing the eoq code (channel 63), the time between the last queue conversion and the first queue conversion require s one additional ccw fetch cycle. continuous samples are not coherent at this boundary. in addition, the time from trigger to first conversion cannot be guaranteed, because it is a function of clock synchronization, programmable trigger events, queue priorities, and so on. 28.8.7.1 software-initiate d continuous-scan mode when software-initiated c ontinuous-scan mode is select ed, the trigger event is generated automatically by the qadc. queue execution begins immediately. if a pause is encountered, another trigger event is generated internally, and execution continues without pausing. when the end-of-queue is reached, another internal trigger event is generated and queue execution restarts at the beginning of the queue. while the time to internally generate and act on a trigger even t is very short, the que ue status field can be read as momentarily indi cating that the queue is idle. the trig ger overrun flag is never set while in software-initiated co ntinuous-scan mode. the software-initiated cont inuous-scan mode keeps the result registers updated mo re frequently than any of the other queue operating modes. the result table can always be read to get the latest converted value for each channel. the channels sc anned are kept up to date by the q adc without software involvement. the software-initiated continuous-sca n mode may be chosen for either queue, but is normally used only with queue 2. when software-initiat ed continuous-scan mode is chosen for queue 1, that queue operates continuously and queue 2, be ing lower in priority, never gets execu ted. the short interval of time between a queue 1 completion and the subsequent trigger event is not sufficient to allow queue 2 execution to begin. the software-initiated continuous-scan mode is a useful choi ce with queue 2 for converting channels that do not need to be synchronized to anything or for slow-to-change analog channe ls. interrupts are normally not used with the software-initiated continuous-scan mode. ra ther, the latest conver sion results can be read from the result table at any time. once initiated, software action is not needed to su stain conversions of channel. 28.8.7.2 externally triggered continuous-scan mode the qadc provides external trigger signals for both queues. when externally triggered continuous-scan mode is selected, a transition on the associated external trigger signal initiates queue execution. the mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) freescale semiconductor 28-51 polarity of the external trigger si gnal is programmable, so that a mode which be gins queue execution on the rising or falling edge ca n be selected. each ccw is read and the indicated conversions are performed until an end-of-queue condi tion is encountered. when the next external trigger edge is detected, queue execution begins again automatically . software involvement is not needed between trigger events. when a pause bit is enco untered in externally triggered conti nuous-scan mode, another trigger event is required for queue execution to cont inue. software involvement is not needed for queue execution to continue from the paused state. some applications need to synchronize the sampling of analog channels to external events. there are cases when it is not possible to use soft ware initiation of the queue scan sequence, because interrupt response times vary. externally triggered continuous -scan mode is useful in these cases. 28.8.7.3 externally gated continuous-scan mode the qadc provides external gating for queue 1 only. when external ly gated continuous-scan mode is selected, the input level on the asso ciated external trigger signal enab les and disables queue execution. the polarity of the external gate signal is fixed so that a high level opens the gate and a low level closes the gate. once the gate is open, each ccw is read and the i ndicated conversions are performed until the gate is closed. when the gate opens agai n, queue execution automatically rest arts at the beginning of the queue. software involvement is not needed between trigger events. if a pause in a ccw is encountered, the pause flag does not set, and execut ion continues without pausing. the purpose of externally gated con tinuous-scan mode is to continuously collect di gitized samples while the gate is open and to have the mo st recent samples availa ble. it is up to the programmer to ensure that the gate is not opened so long th at an end-of-queue is reached. in the event that the queue completes before the gate closes, the cf1 flag will set, and the queue will roll over to the beginning and continue c onversions until the gate closes. if the gate remains open and the cf1 flag is not cleared, when the queue completes a second time the tor1 flag will set and the queue will roll-over again. the queue will continue to execute until the gate cl oses or the mode is disabled. if the gate closes before queue 1 completes execution, the qadc stops and sets the pf1 bit to indicate an incomplete queue. the cwpq1 field ca n be read to determine the last valid conversion in the queue. if the gate opens again, execution of queue 1 restarts. the start of queue 1 is always the first ccw in the ccw table. the condition of the gate is only sampled after each conversion during queue execution, so closing the gate for a period less than a conversion time interv al does not guarantee the cl osure will be captured. 28.8.7.4 periodic time r continuous-scan mode the qadc includes a dedicated peri odic timer for initiati ng a scan sequence on que ue 1 and/or queue 2. a programmable timer in terval ranging from 2 7 to 2 17 times the qclk period in binary multiples can be selected. the qclk period is pr escaled down from the mcu clock. when a periodic timer continuous-scan mode is selected, the timer be gins counting. after the programmed interval elapses, the timer generated trigger event starts the appropriate queue. the qadc automatically performs the conversions in the queue until an end-of-queue condition or a pause is encountered. when a pause occurs, the qadc waits for the periodic interval to expire again, then continues with the queue. once eoq has been detected, the ne xt trigger event causes queue execu tion to restart with the first ccw in the queue. the periodic timer generates a trigge r event whenever the time interval elapses. the trigger event may cause queue execution to continue following a pause or queue completi on or may be cons idered a trigger overrun. as with all continuous-sca n queue operating modes, software action is not needed between mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) 28-52 freescale semiconductor trigger events. because both queues may be tr iggered by the periodic/interval timer, see section 28.8.9, ?periodic/interval timer for a summary of periodic/in terval timer re set conditions. 28.8.8 qadc clock (qclk) generation figure 28-42 is a block diagram of the qclk subsystem. the qclk provides the timing for the a/d converter state machine which controls the timing of the conversion. the qclk is also the input to a 17-stage binary divider which impl ements the periodic/interval timer . to retain the specified analog conversion accuracy, th e qclk frequency (f qclk ) must be within the tolerance specified in chapter 33, ?electrical characteristics ?. before using the qadc, the prescaler must be initialized with values that put the qclk within the specified range. though most appli cations initialize the prescaler once and do not change it, write operations to the prescaler fields are permitted. figure 28-42. qadc clock subsystem functions caution a change in the prescaler value while a conversion is in pr ogress is likely to corrupt the result. therefore, any pr escaler write oper ation should be done only when both queues are in the disabled modes. to accommodate the wide range of the system clock frequency, qclk is generated by a programmable prescaler which divides the system clock. to allow the a/d conversion time to be maximized across the spectrum of system clock frequencie s, the qadc prescaler permits th e qclk frequency to be software selectable. the frequency of qclk is set with the qpr field in qacr0. 28.8.9 periodic/interval timer the qadc periodic/interval timer can be used to ge nerate trigger events at a programmable interval, initiating execution of queue 1 and/or queue 2. the periodic/interval timer stays reset under these conditions: atd converter state machine 2 7 2 8 2 9 2 10 2 11 2 12 2 13 2 14 2 15 2 16 2 17 periodic timer/interval timer select binary counter queue 1 and queue 2 timer mode rate selection input sample time from ccw sar sar control periodic/interval trigger event for q1 and q2 prescaler system clock 2 8 10 2 qpr[6:0] divide by 2 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) freescale semiconductor 28-53 ? both queue 1 and queue 2 are programmed to any mode which does not use the periodic/interval timer. ? system reset is asserted. ? stop mode is enabled. ? debug mode is enabled. note interval timer single-scan mode does not start the periodic/interval timer until the single-scan enable bit is set. these conditions will cause a pulsed reset of the periodic/interval timer during use: ? a queue 1 operating mode change to a mode which uses the periodic/interval timer, even if queue 2 is already using the timer ? a queue 2 operating mode change to a mode whic h uses the periodic/interv al timer, provided queue 1 is not in a mode which uses the periodic/interval timer ? roll over of the timer during stop mode, the periodic/interval timer is held in reset. because stop mode causes qacr1 and qacr2 to be reset to 0, a valid periodic or interval ti mer mode must be written after leaving stop mode to release the timer from reset. when qadc debug mode is entered and a periodic or interval timer mode is selected, the timer counter is reset after the conversion in pr ogress completes. when the periodic or interval timer mode has been enabled (the timer is counting), but a trigger event has not been issued, debug mode takes effect immediately, and the time r is held in reset. removal of the qadc debug condition re starts the counter from the beginning. refer to section 28.3.1, ?debug mode for more information. 28.8.10 conversion command word table the conversion command word (ccw ) table is 64 half-word (128 byte ) long ram with 10 bits of each entry implemented. the ccw table is written by the user and is not modified by the qadc. each ccw requests the conversion of one analog channel to a di gital result. the ccw specifies the analog channel number, the input sample time, an d whether the queue is to pause after the current ccw. the 10 implemented bits of the ccw can be read and written. the remaining six bits are unimple mented and read as 0s; write operations have no effect. each location in the ccw table corresponds to a location in the result word table. when a conversion is completed fo r a ccw entry, the 10-bit re sult is written in the corresponding result word entry. the beginning of queue 1 is the firs t location in the ccw table. the first location of queue 2 is specified by the beginning of queue 2 pointer field (bq2) in qa cr2. to dedicate the enti re ccw table to queue 1, place queue 2 in disabled mode and write bq2 to 64 or grea ter. to dedicate the en tire ccw table to queue 2, place queue 1 in disabled mode and set bq2 to the first location in the ccw table (ccw0). figure 28-43 illustrates the operation of the queue structure. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) 28-54 freescale semiconductor figure 28-43. qadc conversion queue operation to prepare the qadc for a scan sequence, write to the ccw table to spec ify the desired channel conversions. the criteria for queue execution is established by sel ecting the queue ope rating mode. the queue operating mode determines what type of trigger event starts que ue execution. a trigger event refers to any of the ways that cause the qadc to begin ex ecuting the ccws in a queue or subqueue. an external trigger is only one of the possible trigger events. a scan sequence may be initiated by: ? a software command ? expiration of the peri odic/interval timer ? an external trigger signal ? an external gated signal (queue 1 only) the queue can be scanned in single pass or continuous fashi on. when a single-scan mode is selected, the scan must be engaged by setting the single-scan enable bit. when a continuous-scan mode is selected, the queue remains active in the sel ected queue operating mode after the qadc completes each queue scan sequence. during queue execution, the qadc reads each ccw from the active que ue and executes conversions in three stages: ? initial sample ? final sample beginning of queue 1 00 channel select, sample, hold, a/d conversion conversion command result word table word (ccw) table 00 end of queue 1 beginning of queue 2 end of queue 2 63 63 ? ? ? ? ? ? ? ? ? ? ? ? byp p ist chan 8 9 [7:6] [5:0] p ? pause after conversion until next trigger byp ? bypass buffer amplifier ist ? input sample time chan ? channel number and end-of-queue code 10-bit conversion command word format 0 result [9:0] 10-bit result, readable in three 16-bit formats 0 0 0 0 0 15 14 13 12 11 10 0 result 0 0 0 0 0 right-justified, unsigned result left-justified, unsigned result left-justified, signed result 0 result 0 0 0 0 0 s [5:0] [5:0] [15:6] [15:6] mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) freescale semiconductor 28-55 ? resolution during initial sample, a buffered versi on of the selected input channel is connected to the sample capacitor at the input of the sample buffer amplifier. during the final sample period, the sample buffer ampl ifier is bypassed, and the multiplexer input charges the sample capacitor directly. each ccw specifies a final input sample time of 2, 4, 8, or 16 qclk cycles. when an analog-to-digital conversion is complete, th e result is written to the corresponding location in the result word table. the qadc continues to sequentia lly execute each ccw in the queue until the end of the queue is detected or a pause bit is found in a ccw. when the pause bit is set in the current ccw, the qa dc stops execution of the queue until a new trigger event occurs. the pause status flag b it is set, and an interrupt may opti onally be requested. after the trigger event occurs, the paused state ends, and the qadc continues to execute each ccw in the queue until another pause is encountered or the end of the queue is detected. an end-of-queue condition occurs when: ? the ccw channel field is programmed with 63 to specify the end of the queue. ? the end-of-queue 1 is implied by the beginning of queue 2, which is specified by the bq2 field in qacr2. ? the physical end of the queue ram sp ace defines the end of either queue. when any of the end-of-queue condi tions is recognized, a queue completi on flag is set, and if enabled, an interrupt is requested. these situations prematurely terminate queue execution: ? queue 1 is higher in priority than queue 2. when a trigger even t occurs on queue 1 during queue 2 execution, the execution of queue 2 is suspended by aborting the ex ecution of the ccw in progress, and queue 1 execution begins. when queue 1 execu tion is complete, queue 2 conversions restart with the first ccw entry in queue 2 or the firs t ccw of the queue 2 subqueue being executed when queue 2 was suspended. alternately, conversions can restart with the aborted queue 2 ccw entry. the resume bit in qacr2 selects where queue 2 begins after suspension. by choosing to re-execute all of the suspended queue 2 ccws (resume = 0), all of th e samples are guaranteed to have been taken during the same scan pass. however, a high tr igger event rate for queue 1 can prevent completion of queue 2. if this occurs, ex ecution of queue 2 can begin with the aborted ccw entry (resume = 1). ? any conversion in progress for a queue is aborted when that queue?s operating mode is changed to disabled. putting a queue into the disabl ed mode does not power down the converter. ? changing a queue?s operating mode to another vali d mode aborts any conve rsion in progress. the queue restarts at its be ginning once an appropriate trigger event occurs. ? for low-power operation, the stop bi t can be set to prepare the module for a loss of clocks. the qadc aborts any conversion in progr ess when stop mode is entered. ? when the qadc debug bit is se t and the cpu enters backgro und debug mode, the qadc freezes at the end of the conversion in progress. af ter leaving debug mode, the qadc resumes queue execution beginning with the next ccw entry. refer to section 28.3.1, ?debug mode ? for more information. 28.8.11 result word table the result word table is a 64 half -word (128 byte) long by 10-bit wide ram. an entry is written by the qadc after completing an analog c onversion specified by the correspondi ng ccw table entry. the result word table can be read or writte n, but in normal operation is only read to obtain analog conversions from the qadc. unimplemented bits read as 0s and writes have no effect. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) 28-56 freescale semiconductor note although the result ram can be written, some write opera tions, like bit manipulation, may not operate as e xpected because the hardware cannot access a true 16-bit value. while there is only one result word ta ble, the half-word (16-bi t) data can be accessed in three different data formats: ? right justified wi th 0s in the higher order unused bits ? left justified with the most significant bit inverted to form a sign bit, and 0s in the unused lower order bits ? left justified with 0s in the lower order unused bits the left justified, signed format corr esponds to a half-scale, offset bina ry, two?s complement data format. the address used to read the result table determines the data alignment format. all write operations to the result word table are right justified. 28.9 signal connecti on considerations the qadc requires accurate, noise-f ree input signals for proper operation. this section discusses the design of external circuitry to maximize qadc performance. 28.9.1 analog reference signals no a/d converter can be more accurate than its analog reference. any noi se in the reference can result in at least that much error in a conversion. the reference for the qadc, supplied by signals v rh and v rl , should be low-pass filtered from its source to obtain a noise-free, clean signal. in many cases, simple capacitive bypassing may suffice. in extreme cases, induc tors or ferrite beads may be necessary if noise or rf energy is present. external resistance may intr oduce error in this architect ure under certain conditions. any series devices in the filter network shoul d contain a minimum amount of dc resistance. for accurate conversion results, th e analog reference voltages must be within the limits defined by v dda and v ssa , as explained in this subsection. 28.9.2 analog power signals the analog supply signals (v dda and v ssa ) define the limits of the analog reference voltages (v rh and v rl ) and of the analog multiplexer inputs. figure 28-44 is a diagram of the analog input circuitry. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) freescale semiconductor 28-57 figure 28-44. equivalent analog input circuitry because the sample ampl ifier is powered by v dda and v ssa , it can accurately transfer input signal levels up to but not exceeding v dda and down to but not below v ssa. if the input signal is outside of this range, the output from the sample amplifier is clipped. in addition, v rh and v rl must be within the range defined by v dda and v ssa . as long as v rh is less than or equal to v dda , and v rl is greater than or equal to v ssa , and the sample amplifier has accurately transferred the input signal, resolution is ratiometric within the limits defined by v rl and v rh . if v rh is greater than v dda , the sample amplifier can never transfer a full-scale value. if v rl is less than v ssa , the sample amplifier can never transfer a 0 value. figure 28-45 shows the results of reference volta ges outside the ra nge defined by v dda and v ssa . at the top of the input signal range, v dda is 10 mv lower than v rh . this results in a ma ximum obtainable 10-bit conversion value 0x03fe. at the bottom of the signal range, v ssa is 15 mv higher than v rl , resulting in a minimum obtainable 10-bi t conversion value of 0x0003. sample amp 16 channels total v rl v dda v rh s/h comparator c v ssa mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) 28-58 freescale semiconductor figure 28-45. errors resulting from clipping 28.9.3 conversion timing schemes this section contains some conversion timing examples. figure 28-46 shows the timing for basic conversions where it is assumed that: ? q1 begins with ccw0 and ends with ccw3. ? ccw0 has pause bit set. ? ccw1 does not have pause bit set. ? external trigger rising edge for q1 ? ccw4 = bq2 and q2 is disabled. ? q1 res shows relative result register updates. recall that when qs = 0, both queue s are disabled; when qs = 8, queue 1 is active and queue 2 is idle; and when qs = 4; queue 1 is paused and queue 2 is disabled. 0 .020 5.100 5.110 1 2 3 4 5 6 7 8 3fa 3fb 3fc 3fd 3fe 3ff .010 .030 5.120 5.130 10-bit result (hexadecimal) inputs in volts (v rh = 5.120 v, v rl = 0 v) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) freescale semiconductor 28-59 figure 28-46. external positive ed ge trigger mode timing with pause a time separator is provided between the triggers and the end of c onversion (eoc). the relationship to qclk displayed is not guaranteed. cwpq1 and cwpq2 typically lag cwp and only match cwp when the associated queue is inactive. another way to view cwpq1 and cwpq2 is that thes e registers update when eoc triggers the write to the result register. for the ccw with the pause bit se t (ccw0), cwp does not increment until triggered. for the ccw with the pause bit clear (ccw1), the cwp increments with the eoc. the conversion results q1 resx show the result associ ated with ccwx, such that r0 represents the result associated with ccw0. figure 28-47 shows the timing for conversions in externally gate d single-scan with same assumptions in example 1 except: ? no pause bits set in any ccw ? externally gated single scan mode for q1 ? single scan enable bit (sse1) is set. when the gate closes and opens again, the conversions start with the first ccw in q1. when the gate closes, the active conversi on completes before the queue goes idle. when q1 completes, both the cf1 bit sets and the sse bit clears. in this mode, the pf1 bit sets to reflect that a gate closing occu rred before the queue completed. figure 28-48 shows the timing for conversions in externally gated conti nuous scan mode with the same assumptions as in figure 28-47 . r1 last r0 ccw0 ccw1 ccw2 ccw1 conversion time time between qclk trig1 eoc qs cwp cwpq1 q1 res 0 last 8 4 8 ccw0 triggers = 14 qclks conversion time = 14 qclks mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) 28-60 freescale semiconductor at the end of q1,the completion flag cf1 sets and the queue restarts. if the queue starts a second time and completes, the trigger overrun flag tor1 sets. figure 28-47. gated mode, single scan timing figure 28-48. gated mode, continuous scan timing 08 0 8 0 ccw3 ccw2 ccw1 ccw0 last ccw0 ccw1 r3 r2 r1 r0 last r0 r1 trig1 (gate) eoc qs cwp cwpq1 q1 res sse cf1 pf1 last ccw0 ccw1 ccw1 ccw0 ccw2 ccw3 eoc qs cwp cspq1 q1 res cf1 ccw0 ccw3 ccw0 ccw3 ccw2 ccw1 ccw0 last last ccw0 ccw1 ccw2 ccw3 last r0 r1 r2 r3 r2 ccw2 xx 08 queue restart queue restart tor1 ccw3 r3 trig1 (gate) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) freescale semiconductor 28-61 28.9.4 analog supply filtering and grounding two important factors influencing performance in an alog integrated circuits are supply filtering and grounding. generally, digital circuits use bypass capaci tors on every v dd /v ss signal pair. this applies to analog subsystems and subm odules also. equally important as bypass ing is the distribution of power and ground. analog supplies should be isolated fro m digital supplies as much as pos sible. this necessity stems from the higher performance requirements of ten associated with analog circuits . therefore, deriving an analog supply from a local digital supply is not recommended. however, if fo r cost reasons digital and analog power are derived from a co mmon regulator, filtering of the analog power is recommended in addition to the bypassing of the supplies already mentioned. for example, an rc lo w pass filter c ould be used to isolate the digital and analog suppl ies when generated by a common regul ator. if multiple high precision analog circuits are locally employed (for exam ple, two a/d converters), the analog supplies should be isolated from each other as sharing supplies introduc es the potential for interference between analog circuits. grounding is the most important fact or influencing analog circuit perfo rmance in mixed signal systems (or in standalone analog systems). clos e attention must be paid not to introduce additional sources of noise into the analog circuitry. comm on sources of noise include ground loops, inductive coupling, and combining digital and analog gr ounds together inappropriately. the problem of how and when to combine digital and analog grounds arises from the large transients which the digital ground must handle. if the digital ground is not able to handle th e large transients, the associated current can return to ground through the analog ground. it is this excess current overflowing into the analog ground which causes performance de gradation by developing a differential voltage between the true analog ground and the microcontroller?s ground pins. th e end result is that the ground observed by the analog circuit is no longer true ground and thus skews converter performance. two similar approaches to impr oving or eliminating the problems as sociated with grounding excess transient currents involve star-point ground systems. one approach is to star-point the different grounds at the power supply origin, thus keep ing the ground isolated. refer to figure 28-49 . another approach is to star-point the differ ent grounds near the an alog ground signal on the microcontroller by using small traces for connect ing the non-analog grounds to the analog ground. the small traces are mean t only to accommodate dc differences, not ac transients. note this star-point scheme still requi res adequate grounding for digital and analog subsystems in additi on to the star-point ground. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) 28-62 freescale semiconductor figure 28-49. star-ground at the point of power supply origin other suggestions for pcb layout in which the qadc is employed include: ? analog ground must be low impedance to all analog ground points in the circuit. ? bypass capacitors should be as close to the power pins as possible. ? the analog ground should be isolated from the digital ground. this can be done by cutting a separate ground plane for the analog ground. ? non-minimum traces should be utilized for conn ecting bypass capacitors and filters to their corresponding ground/power points. ? minimum distance for trace runs when possible. 28.9.5 accommodating positive/ negative stress conditions positive or negative stress refers to conditions which exceed nominal ly defined operating limits. examples include applying a voltage ex ceeding the normal limit on an input (for example, voltages outside of the suggested supply/reference ra nges) or causing currents into or out of the pin which exceed normal limits. qadc specific considerations are voltages greater than v dda or less than v ssa applied to an analog input which cause excessive cu rrents into or out of the input. refer to chapter 33, ?electrical characteristics ? for more information on exact magnitudes. either stress conditions can potentia lly disrupt conversion re sults on neighboring inputs. parasitic devices, associated with cmos processes, can cause an immediate disruptive influence on neighboring pins. common examples of parasitic devices are diodes to substrate and bipolar devices with the base terminal tied to substrate (v ss /v ssa ground). under stress conditions, current injected on an ad jacent signal can cause errors on the selected ch annel by developing a voltage drop across the selected channel?s impedances. qadc v rh v rl v ssa v dda v dd v ss analog power supply +5 v +5 v agnd digital power supply +5 v pgnd pcb mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) freescale semiconductor 28-63 figure 28-50 shows an active parasitic bipolar npn transistor when an input signal is subjected to negative stress conditions. figure 28-51 shows positive stress conditions can activate a similar pnp transistor. figure 28-50. input signal subj ected to negative stress figure 28-51. input signal subj ected to positive stress the current into the signal (i injn or i injp ) under negative or positive stress is determined by these equations: eqn. 28-1 eqn. 28-2 where: v stress = adjustable voltage source v eb = parasitic pnp emitter/base voltage v be = parasitic npn base/emitter voltage r stress = source impedance (10 k resistor in figure 28-50 and figure 28-51 on stressed channel) r selected = source impedance on channel selected for conversion the current into (i in ) the neighboring pin is determined by the k n (current coupling rati o) of the parasitic bipolar transistor (k n ?? 1). the i in can be expressed by this equation: i in = ? k n * i inj where: i inj is either i injn or i injp . a method for minimizing the impact of stress conditions on the qadc is to stra tegically allocate qadc inputs so that the lower accuracy inputs are adjacent to the inputs most likely to see stress conditions. also, suitable source impedances s hould be selected to meet design goals and minimize the effect of stress conditions. r stress r selected adjacent 10 k signal under parasitic i injn i in + stress v stress device signal v in an n an n+1 r stress r selected adjacent 10 k signal under parasitic i injp i in + stress v stress device signal v in v dda an n an n+1 i injn v stress v be ? () ? r stress ----------------------------------------------- = i injp v stress v eb ? v dda ? r stress -------------------------------------------------------------- - = mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) 28-64 freescale semiconductor 28.9.6 analog input considerations the source impedance of the anal og signal to be measured and any intermediate filtering should be considered whether external multiplexing is used or not. figure 28-52 shows the connection of eight typical analog signal sources to one qadc analog i nput signal through a separate multiplexer chip. also, an example of an analog signal source connected directly to a qadc analog input channel is displayed. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) freescale semiconductor 28-65 figure 28-52. external multiplexing of analog signal sources c p c samp c p c samp c in = c p + c samp r muxout r source 2 analog signal source filtering and interconnect typical mux chip interconnect qadc ~ c filter c source r filter 2 c muxin 0.01 f 1 c muxout (mc54hc4051, mc74hc4051, mc54hc4052, mc74hc4052, mc54hc4053, etc.) r source2 c filter c source r filter 2 c muxin 0.01 f 1 r source 2 c filter c source r filter 2 c muxin 0.01 f 1 r source 2 c filter c source r filter 2 c muxin 0.01 f 1 r source 2 c filter c source r filter 2 c muxin 0.01 f 1 r source 2 c filter c source r filter 2 c muxin 0.01 f 1 r source 2 c filter c source r filter 2 c muxin 0.01 f 1 r source 2 c filter c source r filter 2 c muxin 0.01 f 1 c filter r filter 2 0.01 f 1 1. typical value 2. r filter , typically 10 k ?20 k notes: r source 2 c source c pcb c pcb ~ ~ ~ ~ ~ ~ ~ ~ mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) 28-66 freescale semiconductor 28.9.7 analog input pins analog inputs should have low ac impedance at the pi ns. low ac impedance can be realized by placing a capacitor with good high frequency characteristics at the input signal of the device. ideally , that capacitor should be as large as possible (wit hin the practical range of capacitors that stil l have good high-frequency characteristics). this cap acitor has two effects: ? it helps attenuate any noise that may exist on the input. ? it sources charge during the sample period when the analog signal source is a high-impedance source. series resistance can be used with the capacitor on an input signal to implement a simple rc filter. the maximum level of filtering at th e input pins is application depe ndent and is based on the bandpass characteristics required to accurately track the dynamic characteristics of an input. simple rc filtering at the pin may be limited by the source impedance of the tran sducer or circuit suppl ying the analog signal to be measured. (see section 28.9.7.2, ?error re sulting from leakage .?) in some cases, the size of the capacitor at the pin may be very small. figure 28-53 is a simplified model of an input channel. refer to this m odel in the following discussion of the interaction between the external circ uitry and the circuitr y inside the qadc. figure 28-53. electrical model of an a/d input signal in figure 28-53 , r f , r src , and c f comprise the external filter circuit. c p is the internal parasitic capacitor. c samp is the capacitor array used to sample and hold th e input voltage. v i is an internal voltage source used to provide charge to c samp during sample phase. the following paragraphs pr ovide a simplified description of the interaction between the qadc and the user's external circuitry. this circ uitry is assumed to be a simple rc low-pass filt er passing a signal from a source to the qadc input signal. these paragraphs make the following assumptions: ? the external capacitor is perfect (no leakage, no significant dielectric ab sorption characteristics, etc.). ? all parasitic capacitance associated with the input signal is in cluded in the value of the external capacitor. ? inductance is ignored. ? the ?on? resistance of the in ternal switches is 0 ohms and th e ?off? resistance is infinite. s1 amp r f s3 c samp v i c p c f v src internal circuit model external filter v src = source voltage = internal parasitic capacitance r f c f c p c samp = sample capacitor v i = filter impedance = filter capacitor = internal voltage source during sample and hold source r src r src = source impedance s2 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) freescale semiconductor 28-67 28.9.7.1 settling time fo r the external circuit the values for r src , r f , and c f in the user's external circuitry de termine the length of time required to charge c f to the source voltage level (v src ). at time t = 0, v src changes in figure 28-53 while s1 is open, disconnecting the internal circuitry from the extern al circuitry. assume that the initial voltage across c f is 0. as c f charges, the voltage across it is determined by the equation, wh ere t is the total charge time: as t approaches infinity, v cf will equal v src . (this assumes no internal leakage.) with 10-bit resolution, 1/2 of a count is equal to 1/2048 full-scale value. assuming worst case (v src = full scale), table 28-24 shows the require d time for c f to charge to within 1/2 of a count of the actual source voltage during 10-bit conversions. table 28-24 is based on the rc network in figure 28-53 . note the following times are completely independent of the a/d converter architecture (assuming the qadc is not affecting the charging). the external circuit described in table 28-24 is a low-pass filter. measur ements of an ac component of the external signal must take the characteristics of this filter into account. 28.9.7.2 error resulting from leakage a series resistor limits the current to a signal; therefore, input leakage acting through a large source impedance can degrade a/d accuracy. the maxi mum input leakage current is specified in chapter 33, ?electrical characteristics ?. input leakage is greater at higher operating temperatures. in the temperature range from 125c to 50c, the leakage current is halved for every 8c to 12c reduction in temperature. assuming v rh ?v rl = 5.12 v, 1 count (with 10-bit resolution) corresponds to 5 mv of input voltage. a typical input leakage of 200 na acting through 10 k of external series resistance results in an error of 0.4 count (2.0 mv). if the s ource impedance is 100 k and a typical leakage of 100 na is present, an error of 2 counts (10 mv) is introduced. in addition to internal junction leak age, external leakage (for example, if external clamping diodes are used) and charge sharing effects with internal capacitors also contri bute to the total leakage current. table 28-25 illustrates the effect of diff erent levels of tota l leakage on accuracy fo r different values of source impedance. the error is li sted in terms of 10-bit counts. table 28-24. external circuit settling time to 1/2 lsb filter capacitor (cf) source resistance (r f + r src ) 100 1 k 10 k 100 k 1 f7 6 0 s 7.6 ms 76 ms 760 ms 0.1 f 76 s 760 s 7.6 ms 76 ms 0.01 f7 . 6 s76 s 760 s 7.6 ms 0.001 f 760 ns 7.6 s76 s 760 s 100 pf 76 ns 760 ns 7.6 s76 s vcf = vsrc (1 ?e?t/(rf + rsrc) cf) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) 28-68 freescale semiconductor caution leakage below 200 na is obtainable only within a limited temperature range. 28.10 interrupts the four interrupt lines are outputs of the module and have no priority or arbitration within the module. 28.10.1 interrupt operation qadc inputs can be monitored by polling or by usi ng interrupts. when interrupts are not needed, the completion flag and the pause flag for each queue can be monitored in the status register ( qasr0). in other words, flag bits can be polled to de termine when new results are available. table 28-26 shows the status flag and interrupt enable bits which correspond to queue 1 and queue 2 activity. if interrupts are enabled for an event, the qadc re quests interrupt service when the event occurs. using interrupts does not require continuously polling the status flags to see if an event has taken place; however, status flags must be cleared after an interrupt is serviced, in order to remove the interrupt request in both polled and interrupt-d riven operating modes, status flags must be re-enabled after an event occurs. flags are re-enabled by clearing the appropriate qasr0 bits in a particular se quence. qasr0 must first be read, then 0s must be written to the flags that are to be cleared. if a new event occurs between the time that the register is read and the time that it is written, the associated flag is not cleared. 28.10.2 interrupt sources the qadc includes four sources of in terrupt requests, each of which is separately enabled. each time the result is written for the last c onversion command word (ccw) in a qu eue, the completion flag for the corresponding queue is set, and when enabled, an interrupt is reques ted. in the same way, each time the table 28-25. error resulting from input leakage (i off ) source impedance leakage value (10-bit conversions) 100 na 200 na 500 na 1000 na 1 k ? ? 0.1 counts 0.2 counts 10 k 0.2 counts 0.4 counts 1 counts 2 counts 100 k 2 counts 4 count 10 counts 20 counts table 28-26. qadc status flags and interrupt sources queue queue activity status flag interrupt enable bit queue 1 result written for last ccw in queue 1 cf1 cie1 result written for a ccw with pause bit set in queue 1 pf1 pie1 queue 2 result written for last ccw in queue 2 cf2 cie2 result written for a ccw with pause bit set in queue 2 pf2 pie2 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) freescale semiconductor 28-69 result is written for a ccw with the pause bit set, the queue pause flag is set, and when enabled, an interrupt is requested. refer to table 28-26 . the pause and complete interrupts fo r queue 1 and queue 2 have separate interrupt vector levels, so that each source can be separately serviced. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 queued analog-to-digital converter (qadc) 28-70 freescale semiconductor mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor 29-1 chapter 29 reset controller module the reset controller is provided to determine the cause of reset, assert the appropr iate reset signals to the system, and then to keep a history of what caused the reset. th e low voltage detec tion module, which generates low-voltage detect (lvd ) interrupts and resets, is implem ented within the reset controller module. 29.1 features module features include: ? seven sources of reset: ? external ? power-on reset (por) ? watchdog timer ? phase locked-loop (pll) loss of lock ? pll loss of clock ? software ? lvd reset ? software-assertable rsto pin independent of chip reset state ? software-readable status flags indi cating the cause of the last reset ? lvd control and status bits for setup and use of lvd reset or interrupt 29.2 block diagram figure 29-1 illustrates the reset controller and is explained in the following sections. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 reset controller module 29-2 freescale semiconductor figure 29-1. reset controller block diagram 29.3 signals table 29-1 provides a summary of the reset controller signal properties. th e signals are described in the following paragraphs. 29.3.1 rsti asserting the external rsti for at least four rising clkout edges ca uses the external reset request to be recognized and latched. 29.3.2 rsto this active-low output signal is driven low when the in ternal reset controller module resets the chip. when rsto is active, the user can drive override options on the data bus. 29.4 memory map and registers the reset controller programming m odel consists of these registers: ? reset control register (rcr), whic h selects reset controller functions ? reset status register (rsr), which refl ects the state of the last reset source see table 29-2 for the memory map and the following para graphs for a description of the registers. table 29-1. reset controller signal properties name direction input hysteresis input synchronization rsti iy y 1 1 rsti is always synchronized except when in low-power stop mode. rsto o? ? power-on reset watchdog timer timeout pll loss of clock pll loss of lock software reset lv d detect rsti pin reset controller rsto pin to internal resets mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 reset controller module freescale semiconductor 29-3 29.4.1 reset control register (rcr) the rcr allows software control fo r requesting a reset, for independe ntly asserting the external rsto pin, and for controlling low-voltage detect (lvd) functions. table 29-2. reset controller memory map ipsbar offset bits 7:0 access 1 1 s/u = supervisor or user mode access. 0x11_0000 rcr s/u 0x11_0001 rsr s/u 0x11_0002 reserved 2 ? 0x11_0003 reserved 2 2 writes to reserved address locations have no effect and reads return 0s. ? 7654 0 field softrst frcrstout ? lvdf lvdie lvdre ? lvde reset 0000_0101 r/w r/w address ipsbar + 0x11_0000 figure 29-2. reset control register (rcr) table 29-3. rcr field descriptions bit(s) name description 7 softrst allows software to request a reset. the reset caused by setting this bit clears this bit. 1 software reset request 0 no software reset request 6 frcrstout allows software to assert or negate the external rsto pin. 1 assert rsto pin 0 negate rsto pin caution: external logic driving reset configuration data during reset needs to be considered when asserting the rsto pin when setting frcrstout. 5 ? reserved, should be cleared. 4 lvdf lvd flag. indicates the low-voltage detect st atus if lvde is set. write a 1 to clear the lvdf bit. 1 low voltage has been detected 0 low voltage has not been detected note: the setting of this flag causes an lv d interrupt if lvde and lvdie bits are set and lvdre is cleared when the supply voltage v dd drops below v dd (minimum). the vector for this interrupt is shared with int0 of the eport module. interrupt arbitration in the interrupt service routine is necessary if both of these interrupts are enabled. also, lvdf is not cleared at reset, however it will always initialize to a zero since the part will not come out of reset while in a low-power state (lvde/lvdre bits are enabled out of reset). mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 reset controller module 29-4 freescale semiconductor 29.4.2 reset status register (rsr) the rsr contains a status bit for every reset source. when reset is entered, the cause of the reset condition is latched along with a value of 0 fo r the other reset sources that were not pending at the time of the reset condition. these values are then reflected in rsr. one or more status bits may be set at the same time. the cause of any subsequent reset is also recorded in the register, overwr iting status from the previous reset condition. rsr can be read at any time. writing to rsr has no effect. 3 lvdie lvd interrupt enable. controls the lvd interrupt if lvde is set. this bit has no effect if the lvde bit is a logic 0. 1 lvd interrupt enabled 0 lvd interrupt disabled 2 lvdre lvd reset enable. controls the lvd reset if lvde is set. this bit has no effect if the lvde bit is a logic 0. lvd reset has priority over lvd interrupt, if both are enabled. 1 lvd reset enabled 0 lvd reset disabled 1 ? reserved, should be cleared. 0 lvde controls whether the lvd is enabled. 1 lvd is enabled 0lvd is disabled 76543210 field ? lvd soft wdr por ext loc lol reset reset dependent r/w r address ipsbar + 0x11_0001 figure 29-3. reset status register (rsr) table 29-4. rsr field descriptions bit(s) name description 7 ? reserved, should be cleared. 6 lvd low voltage detect. indicates that the last reset state was caused by an lvd reset. 1 last reset state was caused by an lvd reset 0 last reset state was not caused by an lvd reset 5 soft software reset flag. indicates that the last reset was c aused by software. 1 last reset caused by software 0 last reset not caused by software 4 wdr watchdog timer reset flag. indicates that the last reset was caused by a watchdog timer timeout. 1 last reset caused by watchdog timer timeout 0 last reset not caused by watchdog timer timeout table 29-3. rcr field descriptions (continued) bit(s) name description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 reset controller module freescale semiconductor 29-5 29.5 functional description 29.5.1 reset sources table 29-5 defines the sources of reset and the signals driven by the reset controller. to protect data integrity, a sync hronous reset source is not acted upon by the reset control logic until the end of the current bus cycle. reset is then asserted on the next rising edge of the system clock after the cycle is terminated. whenever the reset control logi c must synchronize reset to the end of the bus cycle, the internal bus monitor is automatically enabled regard less of the bme bit state in the chip configuration register (ccr). then, if the current bus cycle is not terminated normally the bus monitor terminates the cycle based on the length of time programmed in the bmt field of the ccr. internal byte, word, or longword writes are guaranteed to complete without data corruption when a synchronous reset occurs. ex ternal writes, including longword writes to 16-bit ports, are also guaranteed to complete. 3 por power-on reset flag. indicates that the last reset was caused by a power-on reset. 1 last reset caused by power-on reset 0 last reset not caused by power-on reset 2 ext external reset flag. indica tes that the last reset was c aused by an external device asserting the external rsti pin. 1 last reset state caused by external reset 0 last reset not caused by external reset 1 loc loss-of-clock reset flag. in dicates that the last reset state was caused by a pll loss of clock. 1 last reset caused by loss of clock 0 last reset not caused by loss of clock 0 lol loss-of-lock reset flag. indicates that the last reset state was caused by a pll loss of lock. 1 last reset caused by a loss of lock 0 last reset not caused by loss of lock table 29-5. reset source summary source type power on asynchronous external rsti pin (not stop mode) synchronous external rsti pin (during stop mode) asynchronous watchdog timer synchronous loss of clock asynchronous loss of lock asynchronous software synchronous lvd reset asynchronous table 29-4. rsr field descriptions (continued) bit(s) name description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 reset controller module 29-6 freescale semiconductor asynchronous reset sources usually indicate a catastrophic failure. ther efore, the reset control logic does not wait for the current bus cycle to complete. reset is asserted immediately to the system. 29.5.1.1 power-on reset at power up, the reset c ontroller asserts rsto . rsto continues to be asserted until v dd has reached a minimum acceptable level a nd, if pll clock mode is selected, unt il the pll achieves phase lock. then after approximately an other 512 cycles, rsto is negated and the part begins operation. 29.5.1.2 external reset asserting the external rsti for at least four rising clkout edges ca uses the external reset request to be recognized and latched. the bus monitor is enabled and the current bus cycle is completed. the reset controller asserts rsto for approximately 512 cycles after rsti is negated and the pll has acquired lock. the part then exits reset and begins operation. in low-power stop mode, the system clocks are stopped. a sserting the external rsti in stop mode causes an external reset to be recognized. 29.5.1.3 watchdog timer reset a watchdog timer timeout causes timer reset request to be recognized and latched. the bus monitor is enabled and the current bus cy cle is completed. if the rsti is negated and the pll has acquired lock, the reset controller asserts rsto for approximately 512 cycles. then the part exits reset and begins operation. 29.5.1.4 loss-of-clock reset this reset condition occurs in pll clock mode when the locre bit in the sync r is set and either the pll reference or the pll itself fail s. the reset controller asserts rsto for approximately 512 cycles after the pll has acquired lock. the part th en exits reset and begins operation. 29.5.1.5 loss-of-lock reset this reset condition occurs in pll clock mode when the lolre bit in the s yncr is set and the pll loses lock. the reset controller asserts rsto for approximately 512 cycles after the pll has acquired lock. the part then exits reset and resumes operation. 29.5.1.6 software reset a software reset occurs when the softrst bit is set. if the rsti is negated and the pll has acquired lock, the reset controller asserts rsto for approximately 512 cycles. then the part exits reset and resumes operation. 29.5.1.7 lvd reset the lvd reset will occur when the supply input voltage, v dd, drops below v lvd (minimum). mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 reset controller module freescale semiconductor 29-7 29.5.2 reset control flow the reset logic control flow is shown in figure 29-4 . in this figure, the c ontrol state boxes have been numbered, and these numbers ar e referred to (within parent heses) in the flow descri ption that follows. all cycle counts given are approximate. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 reset controller module 29-8 freescale semiconductor figure 29-4. reset control flow rsti pin or wd timeout or sw reset? loss of clock? loss of lock? rsti negated? pll mode? bus cycle complete? rcon asserted? pll locked? enable bus monitor assert rsto and latch reset status wait 512 clkout cycles latch configuration negate rsto por or lvd assert rsto and latch reset status n n n y y y 1 2 3 n n n 0 5 6 7 8 9 10 11 y y n n y y 12 4 9a 11a y mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 reset controller module freescale semiconductor 29-9 29.5.2.1 synchronou s reset requests in this discussion, the refe rence in parentheses refer to the state numbers in figure 29-4 . all cycle counts given are approximate. if the external rsti signal is asserted by an external device fo r at least four rising clkout edges (3), if the watchdog timer times out, or if software requests a reset, the rese t control logic latches the reset request internally and enables the bus monitor (5). when the current bus cycle is completed (6), rsto is asserted (7). the reset control l ogic waits unt il the rsti signal is negated (8) and for the pll to attain lock (9, 9a) before waiting 512 clkout cycles (1). the reset control logic may la tch the configuration according to the rcon signal level (11, 11a) before negating rsto (12). if the external rsti signal is asserted by an exte rnal device for at least f our rising clkout edges during the 512 count (10) or during the wait for pll lock (9a), the reset flow switches to (8) and waits for the rsti signal to be negated before continuing. 29.5.2.2 internal reset request if reset is asserted by an asynchronous internal reset source, such as loss of clock (1) or loss of lock (2), the reset control logic asserts rsto (4). the reset control logic waits for the pll to attain lock (9, 9a) before waiting 512 clkout cycles (1). then the reset control logic may latch the configuration according to the rcon pin level (11, 11a) before negating rsto (12). if loss of lock occurs during the 512 count (10) , the reset flow switches to (9a) and waits for the pll to lock before continuing. 29.5.2.3 power-on reset/low-voltage detect reset when the reset sequence is initiated by power-on reset (0), the same rese t sequence is followed as for the other asynchronous reset sources. 29.5.3 concurrent resets this section describes the concurrent resets. as in the previous disc ussion references in parentheses refer to the state numbers in figure 29-4 . 29.5.3.1 reset flow if a power-on reset or low-voltage detect condition is detected during any re set sequence, the reset sequence starts immediately (0). if the external rsti pin is asserted for at l east four rising clkout edges while waiti ng for pll lock or the 512 cycles, the external reset is recognized. reset proces sing switches to wait for the external rsti pin to negate (8). if a loss-of-clock or loss-of-lock condition is detected while waiting fo r the current bus cycle to complete (5, 6) for an external reset request, the cycle is terminated. the reset status bits ar e latched (7) and reset processing waits for the external rsti pin to negate (8). if a loss-of-clock or loss-of-loc k condition is det ected during the 512 cycle wait, the reset sequence continues after a pll lock (9, 9a). mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 reset controller module 29-10 freescale semiconductor 29.5.3.2 reset status flags for a por reset, the por and lvd bits in the rsr are set, and the soft, wdr, ext, loc, and lol bits are cleared even if another t ype of reset condition is detected during the reset sequence for the por. if a loss-of-clock or loss-of-lock condition is detected while waiting fo r the current bus cycle to complete (5, 6) for an external reset reque st, the ext, soft, and/or wdr bits along with the loc and/or lol bits are set. if the rsr bits are latched (7) during the ext, soft, and/or wdr reset sequence with no other reset conditions detected, only the ext, soft, and/or wdr bits are set. if the rsr bits are latched (4) during th e internal reset sequence with the rsti pin not asserted and no soft or wdr event, then the loc a nd/or lol bits are the only bits set. for a lvd reset, the lvd bit in the rsr is set, and the soft, wdr, ex t, loc, and lol bits are cleared to 0 even if another type of reset condition is detected during the reset sequence for lvd. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor 30-1 chapter 30 debug support this chapter describes the revisi on a enhanced hardware debug support. 30.1 overview the debug module is shown in figure 30-1 . figure 30-1. processor/debug module interface debug support is divided into three areas: ? real-time trace support?the ability to dete rmine the dynamic execution path through an application is fundamental for debugging. the coldfire solution im plements an 8-bit parallel output bus that reports processor execution status and data to an external emulator system. see section 30.3, ?real-time trace support .? ? background debug mode (bdm)?provides low-le vel debugging in the coldfire processor complex. in bdm, the processor complex is halted and a variety of commands can be sent to the processor to access memory and registers. the external emulator uses a three-pin, serial, full-duplex channel. see section 30.5, ?background debug mode (bdm) ,? and section 30.4, ?programming model .? ? real-time debug support?bdm requi res the processor to be ha lted, which many real-time embedded applications cannot do. debug interrupts let real-time sy stems execute a unique service routine that can quickly save the contents of key registers and variables a nd return the system to normal operation. external development systems can access saved data because the hardware supports concurrent operati on of the processor and bd m-initiated commands. see section 30.6, ?real-time debug support .? note enabling flash security di sables bdm communications. coldfire cpu core debug module high-speed communication port dsclk, dsi, dso control bkpt local bus trace port pst[3:0], ddata[3:0] clkout mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 debug support 30-2 freescale semiconductor 30.2 signal description table 30-1 describes debug module si gnals. all coldfire debug signals ar e unidirectional and related to a rising edge of the processor?s clock signal. the standard 26-pi n debug connector is shown in section 30.8, ?freescale-recommended bdm pinout .? figure 30-2 shows clkout timing with respect to pst and ddata. figure 30-2. clkout timing 30.3 real-time trace support real-time trace, which de fines the dynamic execution path, is a fundamental debug function. the coldfire solution is to include a parallel output port providing encoded processo r status and data to an external development system. this port is pa rtitioned into two 4-bit nibbles: one nibble allows the processor to transmit processor status , (pst), and the other allows opera nd data to be displayed (debug data , ddata). the processor status may not be related to the current bus transfer. external development systems can us e pst outputs with an external im age of the program to completely track the dynamic executi on path. this tracking is complicated by any change in flow, especially when table 30-1. debug module signals signal description development serial clock (dsclk) internally synchronized input. (the logic level on dsclk is validated if it has the same value on two consecutive rising clkout edges.) clocks the serial communication port to the debug module during packet transfers. maximum frequency is 1/5 the processor status clock (clkout) speed. at the synchronized rising edge of dscl k, the data input on dsi is sampled and dso changes state. development serial input (dsi) internally synchronized input that provides data input for the serial communication port to the debug module. development serial output (dso) provides serial output communication for debug m odule responses. dso is registered internally. breakpoint (bkpt ) input used to request a manual breakpoint. assertion of bkpt puts the processor into a halted state after the current instruction completes. halt status is reflected on processor status signals (pst[3:0]) as the value 0xf. clkout see figure 30-2 . clkout indicates when the develo pment system should sample pst and ddata values. debug data (ddata[3:0]) these output signals display the register breakpoi nt status as a default, or optionally, captured address and operand values. the capturing of data values is controlled by the setting of the csr. additionally, execution of the wddata instruction by the processor captures operands which are displayed on ddata. these signals are updated each processor cycle. processor status (pst[3:0]) these output signals report the processor status. table 30-2 shows the encoding of these signals. these outputs indicate the current status of the processor pipeline and, as a result, are not related to the current bus transfer. the pst value is updated each processor cycle. clkout pst or ddata mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 debug support freescale semiconductor 30-3 branch target address calculation is based on the contents of a program-visible register (variant addressing). ddata outputs can be c onfigured to display the target address of such instructions in sequential nibble increments ac ross multiple processor cloc k cycles, as described in section 30.3.1, ?begin execution of taken branch (pst = 0x5) .? two 32-bit storage elem ents form a fifo buffer connecting the processor?s high-speed local bus to the external deve lopment system through pst[3:0] and ddata[3:0]. the buffer captures branch target addresse s and certain data values for eventual display on the ddata port, one nibble at a time star ting with the least si gnificant bit (lsb). execution speed is affected only when both storage elements contain valid data to be dumped to the ddata port. the core stalls until one fifo entry is available. table 30-2 shows the encoding of these signals. table 30-2. processor status encoding pst[3:0] definition hex binary 0x0 0000 continue execution. many instru ctions execute in one processor cycle. if an instructi on requires more processor clock cycles, subsequent clock cycles are indicated by driving pst outputs with this encoding. 0x1 0001 begin execution of one instructi on. for most instructions, this encodi ng signals the first processor clock cycle of an instruction?s execution. certain change-of-flow opcodes, plus the pulse and wddata instructions, generate different encodings. 0x2 0010 reserved 0x3 0011 entry into user-mode. signaled after execution of the instruction that caused the coldfire processor to enter user mode. 0x4 0100 begin execution of pulse and wddata instructions. pulse defines logic analyzer triggers for debug and/or performance analysis. wddata lets the core wr ite any operand (byte, word, or longword) directly to the ddata port, independent of debug module conf iguration. when wddata is executed, a value of 0x4 is signaled on the pst port, followed by the appr opriate marker, and then the data transfer on the ddata port. transfer length depends on the wddata operand size. 0x5 0101 begin execution of taken branch. for some opcodes, a branch target address may be displayed on ddata depending on the csr settings. csr also controls the number of address bytes displayed, indicated by the pst marker value preceding the ddata nibble that begins the data output. see section 30.3.1, ?begin execution of taken branch (pst = 0x5) .? 0x6 0110 reserved 0x7 0111 begin execution of return from exception (rte) instruction. 0x8? 0xb 1000? 1011 indicates the number of bytes to be displayed on the ddata port on subsequent processor clock cycles. the value is driven onto the pst port one clkout cycle before th e data is displayed on ddata. 0x8 begin 1-byte transfer on ddata. 0x9 begin 2-byte transfer on ddata. 0xa begin 3-byte transfer on ddata. 0xb begin 4-byte transfer on ddata. 0xc 1100 exception processing. exceptions that enter emulation mode (debug interrupt or optionally trace) generate a different encoding, as described below. because the 0xc encoding defines a multiple-cycle mode, pst outputs are driven with 0xc until exception processing completes. 0xd 1101 entry into emulator mode. displayed during emulation mode (debug interrupt or optionally trace). because this encoding defi nes a multiple-cycle mode, pst outputs are driven with 0x d until exception processing completes. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 debug support 30-4 freescale semiconductor 30.3.1 begin execution of taken branch (pst = 0x5) pst is 0x5 when a taken branch is executed. for some opcodes, a branch target address may be displayed on ddata depending on the csr settings. csr also c ontrols the number of address bytes displayed, which is indicated by the pst marker value immediat ely preceding the ddata ni bble that begins the data output. bytes are displayed in least-to-mos t-significant order. the processor cap tures only those target addresses associated with taken branches which use a variant addressing mode, that is, rte and rts instructions, jmp and jsr instructions using addr ess register indirect or indexed addressing modes, and all exception vectors. the simplest example of a branch in struction using a variant address is the compiled code for a c language case statement. typically, the evaluation of this statem ent uses the variable of an expression as an index into a table of offsets, where eac h offset points to a unique case within the structure. for such change-of-flow operations, the pro cessor uses the debug pins to output the following sequence of information on successive processor clock cycles: 1. use pst (0x5) to identify that a taken branch was executed. 2. using the pst pins, optionally signal the target address to be displayed sequentially on the ddata pins. encodings 0x9?0xb identify the number of bytes displayed . 3. the new target address is optionally available on subsequent cycles using the ddata port. the number of bytes of the target a ddress displayed on this port is configurable (2, 3, or 4 bytes). another example of a variant branch inst ruction would be a jmp (a0) instruction. figure 30-3 shows the pst and ddata outputs that indi cate a jmp (a0) execution (assu ming the csr was programmed to display the lower 2 bytes of an address). figure 30-3. example jmp instruction output on pst/ddata pst 0x5 indicates a taken branch and the marker value 0x9 indicates a 2-byte address. thus, the subsequent 4 nibbles of ddat a display the lower 2 bytes of address register a0 in least-to-most-significant nibble orde r. the pst output after the jmp instruction completes depends on the 0xe 1110 processor is stopped. appears in multiple-c ycle format when the processor executes a stop instruction. the coldfire processor remains stopped until an interrupt occurs, thus pst outputs display 0xe until the stopped mode is exited . 0xf 1111 processor is halted. because th is encoding defines a multiple-cycl e mode, the pst outputs display 0xf until the processor is rest arted or reset. (see section 30.5.1, ?cpu halt ?) table 30-2. processor status encoding (continued) pst[3:0] definition hex binary ddata clkout 0x0 0x0 a[3:0] 0x5 0x9 default pst a[7:4] a[11:8] a[15:12] default default default mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 debug support freescale semiconductor 30-5 target instruction. the pst can cont inue with the next instruction before the addres s has completely displayed on ddata because of the ddata fifo. if the fifo is full and the next instruction has captured values to display on ddata, the pipeline stalls (pst = 0x0) until space is available in the fifo. 30.4 programming model in addition to the existin g bdm commands that provi de access to the processor?s registers and the memory subsystem, the debug module contains 19 registers to support the re quired functionality. these registers are also accessible from the processor?s supervisor program ming model by executing the wdebug instruction (write only). thus, the breakpoint hardware in the debug m odule can be written by the external development system using the debug serial interface or by the operating system running on the processor core. software is responsible for gua ranteeing that accesses to these res ources are serialized and logically consistent. hardware provides a lock ing mechanism in the csr to allo w the external development system to disable any attempted writes by the processor to the breakpoint registers (setting csr[ipw]). bdm commands must not be issued if the device is using the wdebug instruction to access debug module registers or the resultin g behavior is undefined. these registers, shown in figure 30-4 , are treated as 32-b it quantities, regardless of the number of implemented bits. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 debug support 30-6 freescale semiconductor figure 30-4. debug programming model these registers are ac cessed through the bdm port by the commands, wdmreg and rdmreg , described in section 30.5.3.3, ?command set descriptions .? these commands contain a 5-bit field, drc, that specifies the register, as shown in table 30-3 . pc breakpoint mask register pc breakpoint register data breakpoint register data breakpoint mask register trigger definition register configuration/st atus register note: each debug register is accessed as a 32-bit regist er; shaded fields above are not used (don?t care). all debug control registers are writable from the exte rnal development system or the cpu via the wdebug instruction. csr is write-only from the programming model. it can be r ead or written through the bdm port using the rdmreg and wdmreg commands . address attribute trigger register address low breakpoint register address high breakpoint register 31 15 7 0 31 15 0 31 15 0 31 15 0 31 15 0 31 15 0 aatr ablr abhr csr dbr dbmr pbr pbmr tdr pc breakpoint mask register pc breakpoint register data breakpoint register data breakpoint mask register trigger definition register configuration/st atus register bdm address attribute register note: each debug register is accessed as a 32-bit regist er; shaded fields above are not used (don?t care). all debug control registers are writable from the exte rnal development system or the cpu via the wdebug instruction. csr is write-only from t he programming model. it can be read or written through the bdm port using the rdmreg and wdmreg commands . address attribute trigger register address low breakpoint register address high breakpoint register 31 15 7 0 31 15 7 0 31 15 0 31 15 0 31 15 0 31 15 0 31 15 0 31 15 0 aatr ablr abhr baar csr dbr dbmr pbr pbmr tdr mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 debug support freescale semiconductor 30-7 note debug control registers can be writte n by the external development system or the cpu through the wdebug instruction. csr is write-only from the programming model. it can be read or written through the bdm port using the rdmreg and wdmreg commands. 30.4.1 revision a shared debug resources in the revision a implementation of the debug module, certain hardware structures are shared between bdm and breakpoint functionality as shown in table 30-4 . thus, loading a register to perform a specific function that shares hardwa re resources is de structive to the shared function. for example, a bdm command to access memory ove rwrites an addr ess breakpoint in abhr. a bdm write command overwrites the data breakpoint in dbr. 30.4.2 address attribute trigger register (aatr) the aatr, shown in figure 30-5 , defines address attributes and a mask to be matc hed in the trigger. the register value is compared with address attribute signals from the processor?s local high-speed bus, as defined by the setting of the tr igger definition register (tdr). table 30-3. bdm/breakpoint registers drc[4?0] register name abbreviation initial state page 0x00 configuration/status r egister csr 0x00010_0000 p. 30-10 0x01?0x05 reserved ? ? ? 0x06 address attribute trigger register aatr 0x0000_0005 p. 30-7 0x07 trigger definition register tdr 0x0000_0000 p. 30-14 0x08 program counter breakpoint register pbr ? p. 30-13 0x09 program counter breakpoint mask register pbmr ? p. 30-13 0x0a?0x0b reserved ? ? ? 0x0c address breakpoint high register abhr ? p. 30-9 0x0d address breakpoint low register ablr ? p. 30-9 0x0e data breakpoint register dbr ? p. 30-12 0x0f data breakpoint mask register dbmr ? p. 30-12 table 30-4. rev. a shared bdm/breakpoint hardware register bdm function breakpoint function aatr bus attributes for all memory commands attributes for address breakpoint abhr address for all memory commands address for address breakpoint dbr data for all bdm write commands data for data breakpoint mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 debug support 30-8 freescale semiconductor table 30-5 describes aatr fields. 151413121110 8765432 0 field rm szm ttm tmm r sz tt tm reset 0000_0000_0000_0101 r/w write only. aatr is accessible in supervisor mode as debug control register 0x06 using the wdebug instruction and through the bdm port using the wdmreg command. drc[4?0] 0x06 (aatr) figure 30-5. address attribute trigger register (aatr) table 30-5. aatr field descriptions bits name description 15 rm read/write mask. setting rm masks r in address comparisons. 14?13 szm size mask. setting an szm bit masks the corresponding sz bit in address comparisons. 12?11 ttm transfer type mask. setting a ttm bit masks the corresponding tt bit in address comparisons. 10?8 tmm transfer modifier mask. setting a tmm bit masks the corresponding tm bit in address comparisons. 7 r read/write. r is compared with the r/w signal of the processor?s local bus. 6?5 sz size. compared to the processor?s local bus size signals. 00 longword 01 byte 10 word 11 reserved 4?3 tt transfer type. compared with the local bus transfer type signals. 00 normal processor access 01 reserved 10 emulator mode access 11 acknowledge/cpu space access these bits also define the tt encoding for bdm memory commands. in this case, the 01 encoding indicates an external or dma access (for backward compatibility). these bits affect the tm bits. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 debug support freescale semiconductor 30-9 30.4.3 address breakpoint registers (ablr, abhr) the ablr and abhr, shown in figure 30-6 , define regions in the processo r?s data address space that can be used as part of the trigger. these register values are compared with the address for each transfer on the processor?s high-speed local bus. the tr igger definition register (tdr) identifies the trigger as one of three cases: 1. identical to the value in ablr 2. inside the range bound by ablr and abhr inclusive 3. outside that same range 2?0 tm transfer modifier. compared with the local bus transfer modifier signals, which give supplemental information for each transfer type. tt = 00 (normal mode): 000 explicit cache line push 001 user data access 010 user code access 011 reserved 100 reserved 101 supervisor data access 110 supervisor code access 111 reserved tt = 10 (emulator mode): 0xx?100 reserved 101 emulator mode data access 110 emulator mode code access 111 reserved tt = 11 (acknowledge/cpu space transfers): 000 cpu space access 001?111 interrupt acknowledge levels 1?7 these bits also define the tm encoding for bdm memory commands (for backward compatibility). 31 0 field address reset ? r/w write only. abhr is accessible in supervisor mo de as debug control register 0x0c using the wdebug instruction and via the bdm port using the rdmreg and wdmreg commands. ablr is accessible in supervisor mode as debug co ntrol register 0x0d using the wdebug instruction and via the bdm port using the wdmreg command. drc[4?0] 0x0d (ablr); 0x0c (abhr) figure 30-6. address breakpoi nt registers (ablr, abhr) table 30-5. aatr field descriptions (continued) bits name description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 debug support 30-10 freescale semiconductor table 30-6 describes ablr fields. table 30-7 describes abhr fields . 30.4.4 configuration/st atus register (csr) the csr defines the debug configurat ion for the processor and memory subsystem and contains status information from the breakpoint logi c. csr is write-only from the pr ogramming model. it can be read from and written to through the bdm port. csr is acces sible in supervisor mode as debug control register 0x00 using the wdebug instruction a nd through the bd m port using the rdmreg and wdmreg commands. table 30-6. ablr field description bits name description 31?0 address low address. holds the 32-bit address markin g the lower bound of the address breakpoint range. breakpoints for specific addresses are programmed into ablr. table 30-7. abhr field description bits name description 31?0 address high address. holds the 32-bit address mark ing the upper bound of the address breakpoint range. 31 28 27 26 25 24 23 20 19 17 16 field bstat fof trg halt bkpt hrl ? ipw reset 0000_0000_0000_0000 r/w 1 r? r / w 1514131211109 8 76543 0 field map trc emu ddc uhe btb ? npl ipi ssm ? reset 0000_0000_0000_0000 r/w r/w r/w r/w r/w r/w r/w r r/w r/w r/w ? drc[4?0] 0000_0000_0000_0000 figure 30-7. configuration/status register (csr) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 debug support freescale semiconductor 30-11 table 30-8 describes csr fields. table 30-8. csr field descriptions bit name description 31?28 bstat breakpoint status. provides read-only status information concerning hardware breakpoints. bstat is cleared by a tdr write or by a csr read when eith er a level-2 breakpoint is triggered or a level-1 breakpoint is triggered and the level-2 breakpoint is disabled. 0000 no breakpoints enabled 0001 waiting for level-1 breakpoint 0010 level-1 breakpoint triggered 0101 waiting for level-2 breakpoint 0110 level-2 breakpoint triggered 27 fof fault-on-fault. if fof is set, a catastrophic halt occurred and forc ed entry into bdm. fof is cleared whenever csr is read. 26 trg hardware breakpoint trigger. if trg is set, a hardware breakpoint halted the processor core and forced entry into bdm. reset, the debug go command, or reading csr will clear trg. 25 halt processor halt. if halt is set, the processor exec uted a halt and forced entry into bdm. reset, the debug go command, or reading csr will clear halt. 24 bkpt breakpoint assert. if bkpt is set, bkpt was asserted, forcing the pr ocessor into bd m. reset, the debug go command, or reading csr will clear bkpt. 23?20 hrl hardware revision level. indicates the level of debug module functionality. an emulator could use this information to identify the leve l of functionality supported. 0000 initial debug functionality (revision a) (this is the only valid value for this device.) 19?17 ? reserved, should be cleared. 16 ipw inhibit processor writes. setting ipw inhibits processor-initiated writes to the debug module?s programming model registers. ipw can be modified only by commands from the external development system. 15 map force processor references in emulator mode. 0 all emulator-mode references are mapped in to supervisor code and data spaces. 1 the processor maps all references while in emulator mode to a special address space, tt = 10, tm = 101 or 110. 14 trc force emulation mode on trace exception. if trc = 1, the processor enters emulator mode when a trace exception occurs. if trc=0, the processor enters supervisor mode. 13 emu force emulation mode. if emu = 1, the proc essor begins executing in emulator mode. see section 30.6.1.1, ?emulator mode .? 12?11 ddc debug data control. controls operand data capture for ddata, which displays the number of bytes defined by the operand reference size before the actual data; byte displays 8 bits, word displays 16 bits, and long displays 32 bits (one nibble at a time across multiple pstclk cycles). see ta b l e 3 0 - 2 . 00 no operand data is displayed. 01 capture all write data. 10 capture all read data. 11 capture all read and write data. 10 uhe user halt enable. selects the cpu privilege level required to execute the halt instruction. 0 halt is a supervisor-only instruction. 1 halt is a supervisor/user instruction. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 debug support 30-12 freescale semiconductor 30.4.5 data breakpoint/mask registers (dbr, dbmr) the dbr, shown in figure 30-8 , specifies data patterns used as pa rt of the trigger into debug mode. dbr bits are masked by setting correspond ing dbmr bits, as defined in tdr. 9?8 btb branch target bytes. defines the number of bytes of branch target address ddata displays. 00 0 bytes 01 lower 2 bytes of the target address 10 lower 3 bytes of the target address 11 entire 4-byte target address see section 30.3.1, ?begin execution of taken branch (pst = 0x5) .? 7 ? reserved, should be cleared. 6 npl non-pipelined mode. determines whether th e core operates in pipelined or mode or not. 0 pipelined mode 1 nonpipelined mode. the processor effectively executes one instruction at a time with no overlap. this adds at least 5 cycles to th e execution time of each instruct ion. given an average execution latency of 1.6 cycles/instruction , throughput in non-pipeline mo de would be 6.6 cycles/instruction, approximately 25% or less of pipelined performance. regardless of the npl state, a triggered pc breakpoint is always reported before the triggering instruction executes. in normal pipeline oper ation, the occurrence of an address and/or data breakpoint trigger is imprecise. in non-pipeline mode, triggers are always reported before the next instruction begins execution and trigger reporting can be considered precise. 5 ipi ignore pending interrupts. 1 core ignores any pending interrupt requests signalled while in single-instruction-step mode. 0 core services any pending interrupt requests that were signalled while in single-step mode. 4 ssm single-step mode. setting ssm puts the processor in single-step mode. 0 normal mode. 1 single-step mode. the processor halts after exec ution of each instruction. while halted, any bdm command can be executed. on receipt of the go command, the processor executes the next instruction and halts again. this process continues until ssm is cleared. 3?0 ? reserved, should be cleared. 31 0 field data (dbr); mask (dbmr) reset uninitialized r/w dbr is accessible in supervisor mode as debug control register 0x0e, using the wdebug instruction and through the bdm port using the rdmreg and wdmreg commands. dbmr is accessible in supervisor mo de as debug control register 0x0f ,using the wdebug instruction and via the bdm port using the wdmreg command. drc[4?0] 0x0e (dbr), 0x0f (dbmr) figure 30-8. data breakpoint/mask registers (dbr/dbmr) table 30-8. csr field descriptions (continued) bit name description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 debug support freescale semiconductor 30-13 table 30-9 describes dbr fields. table 30-10 describes dbmr fields. the dbr supports both aligned and misaligned references. table 30-11 shows relationships between processor address, access size, and location within the 32-bit data bus. 30.4.6 program counter breakpoi nt/mask registers (pbr, pbmr) the pbr defines an instruction address for use as part of the trigger. this register?s contents are compared with the processor?s program counte r register when tdr is configured appropriately. pbr bits are masked by setting corresponding pbmr bits. re sults are compared with the proc essor?s program counter register, as defined in tdr. figure 30-9 shows the pc breakpoint register. table 30-9. dbr field descriptions bits name description 31?0 data data breakpoint value. contains the value to be compared with the data value from the processor?s local bus as a breakpoint trigger. table 30-10. dbmr field descriptions bits name description 31?0 mask data breakpoint mask. the 32-bit mask for the data breakpoint trigger. clearing a dbr bit allows the corresponding dbr bit to be compared to the appropriate bit of the processor?s local data bus. setting a dbmr bit causes that bit to be ignored. table 30-11. access size and operand data location a[1:0] access size operand location 00 byte d[31:24] 01 byte d[23:16] 10 byte d[15:8] 11 byte d[7:0] 0x word d[31:16] 1x word d[15:0] xx longword d[31:0] mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 debug support 30-14 freescale semiconductor table 30-12 describes pbr fields. figure 30-9 shows pbmr. table 30-13 describes pbmr fields. 30.4.7 trigger definition register (tdr) the tdr, shown in table 30-11 , configures the operation of th e hardware breakpoint logic that corresponds with the abhr/ablr/ aatr, pbr/pbmr, and dbr/dbmr registers within the debug module. the tdr controls the ac tions taken under the defined c onditions. breakpoint logic may be configured as a one- or two-level trigger. tdr[31?16] define the second- level trigger and bits 15?0 define the first-level trigger. 31 0 field program counter reset ? r/w write. pc breakpoint register is accessible in supe rvisor mode using the wdeb ug instruction and through the bdm port using the rdmreg and wdmreg commands using values shown in section 30.5.3.3, ?command set descriptions .? drc[4?0] 0x08 (pbr) figure 30-9. program counter breakpoint register (pbr) table 30-12. pbr field descriptions bits name description 31?0 address pc breakpoint address. the 32-bit address to be compared with the pc as a breakpoint trigger. 31 0 field mask reset ? r/w write. pbmr is accessible in supervisor mode as debug control register 0x09 using the wdebug instruction and via the bdm port using the wdmreg command. drc[4?0] 0x09 figure 30-10. program counter breakpoint mask register (pbmr) table 30-13. pbmr field descriptions bits name description 31?0 mask pc breakpoint mask. a zero in a bit position causes the corresponding pbr bit to be compared to the appropriate pc bit. set pbmr bits cause pbr bits to be ignored. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 debug support freescale semiconductor 30-15 note the debug module has no ha rdware interlocks, so to prevent spurious breakpoint triggers while the breakpoint registers ar e being loaded, disable tdr (by clearing tdr[29,13]) be fore defining triggers. a write to tdr clears the csr trigger status bits, csr[bstat]. table 30-14 describes tdr fields. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 field trc ebl edlw edwl edwu edll edlm edum eduu di eai ear eal epc pci reset 0000_0000_0000_0000 151413 12 11 10 9 8 7 6 543210 field lxt ebl edlw edwl edwu edll edlm edum eduu di eai ear eal epc pci reset 0000_0000_0000_0000 r/w write only. accessible in supervisor mode as debug control register 0x07 using the wdebug instruction and through the bdm port using the wdmreg command. drc[4?0] 0x07 figure 30-11. trigger definition register (tdr) table 30-14. tdr field descriptions bits name description 31?30 trc trigger response control. determines how the processor responds to a completed trigger condition. the trigger response is always displayed on ddata. 00 display on ddata only 01 processor halt 10 debug interrupt 11 reserved 15?14 lxt level-x trigger. this is a rev. b function only . the level-x trigger bit determines the logic operation for the trigger between the pc_condition and the (address_range & data_condition) where the inclusion of a data condition is optional. the cold fire debug architecture supports the creation of single or double-level triggers. tdr[15] 0 level-2 trigger = pc_condition & address_range & data_condition 1 level-2 trigger = pc_condition | (address_range & data_condition) tdr[14] 0 level-1 trigger = pc_condition & address_range & data_condition 1 level-1 trigger = pc_condition | (address_range & data_condition) 29/13 ebl enable breakpoint. global enable for the breakpo int trigger. setting tdr[ebl] enables a breakpoint trigger. clearing it disables all breakpoints at that level. second-level trigger first-level trigger mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 debug support 30-16 freescale semiconductor 30.5 background debug mode (bdm) the coldfire family implements a low-level system debugger in the mi croprocessor hardware. communication with the development system is handled through a dedicated, high-speed serial command interface. the coldfire architect ure implements the bdm controller in a dedicated hardware module. although some bdm operations, such as cpu register a ccesses, require the cpu to be halted, other bdm commands, such as memory accesses, can be executed while the processor is running. 30.5.1 cpu halt although most bdm operations can oc cur in parallel with cpu opera tions, unrestricted bdm operation requires the cpu to be halted. the s ources that can cause the cpu to halt are listed be low in order of priority: 28?22/ 12?6 ed x setting an ed x bit enables the corresponding data brea kpoint condition based on the size and placement on the processor?s local data bus. clearing all ed x bits disables data breakpoints. 28/12 edlw data longword. entire processor?s local data bus. 27/11 edwl lower data word. 26/10 edwu upper data word. 25/9 edll lower lower data byte. low-order byte of the low-order word. 24/8 edlm lower middle data byte. high-order byte of the low-order word. 23/7 edum upper middle data byte. low-order byte of the high-order word. 22/6 eduu upper upper data byte. high-order byte of the high-order word. 21/5 di data breakpoint invert. provides a way to invert the logical sense of all the data breakpoint comparators. this can develop a trigger based on the occurrence of a data value other than the dbr contents. 20?18/ 4?2 ea x enable address bits. setting an ea bit enables the corresponding address breakpoint. clearing all three bits disables the breakpoint. 20/4 eai enable address breakpoint inverted. breakpoint is based outside the range between ablr and abhr. 19/3 ear enable address breakpoint range. the breakpoint is based on the inclusive range defined by ablr and abhr. 18/2 eal enable address breakpoint low. the breakpoint is based on the address in the ablr. 17/1 epc enable pc breakpoint. if set, this bit enables the pc breakpoint. 16/0 pci breakpoint invert. if set, this bit allows execution outside a given region as defined by pbr and pbmr to enable a trigger. if cleared, the pc breakpoin t is defined within the region defined by pbr and pbmr. table 30-14. tdr field descriptions (continued) bits name description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 debug support freescale semiconductor 30-17 1. a catastrophic fault-on-fault condition automatically halts the processor. 2. a hardware breakpoint can be configured to generate a pending halt condition similar to the assertion of bkpt . this type of halt is always first made pending in the processor. next, the processor samples for pending halt and interrupt conditions once per instruction. when a pending condition is asserted, the processor halts execution at the next sample point. see section 30.6.1, ?theory of operation .? 3. the execution of a halt instruction immediately suspends execution. attempting to execute halt in user mode while csr[uhe] = 0 gene rates a privilege violation exception. if csr[uhe] = 1, halt can be executed in user mode. after halt executes , the processor can be restarted by serial shifting a go command into the debug module. execution continues at the instruction after halt. 4. the assertion of the bkpt input is treated as a pseudo-interrupt; that is, the halt condition is postponed until the processor core samples for halts/interrupts. the processor samples for these conditions once during the execution of each instruct ion. if there is a pending halt condition at the sample time, the processor suspends execution and enters the halted state. the assertion of bkpt should be considered in the following two special cases: ? after the system reset signal is negated, the proc essor waits for 16 processor clock cycles before beginning reset exception processing. if the bkpt input is asserted within eight cycles after rsti is negated, the processor enters th e halt state, signaling halt stat us (0xf) on the pst outputs. while the processor is in this state, all resources accessible through the debug m odule can be referenced. this is the only chance to force the processor into emulation mode through csr[emu]. after system initialization, th e processor?s response to the go command depends on the set of bdm commands performed while it is halted for a breakpoint. specific ally, if the pc register was loaded, the go command causes the processo r to exit halted state and pa ss control to the instruction address in the pc, bypassing normal reset excepti on processing. if the pc was not loaded, the go command causes the processor to exit halted state and continue reset exception processing. ? the coldfire architecture also handles a special case of bkpt being asserted while the processor is stopped by execution of the st op instruction. for this case, the processor exits the stopped mode and enters the halted st ate, at which point, all bdm commands may be ex ercised. when restarted, the processor continues by executing the next se quential instruction, that is, the instruction following the stop opcode. csr[27?24] indicates the halt source, showing the highest priority sour ce for multiple halt conditions. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 debug support 30-18 freescale semiconductor 30.5.2 bdm serial interface when the cpu is halted and pst reflects the halt status, the development system can send unrestricted commands to the debug module. the debug module implements a synchr onous protocol using two inputs (dsclk and dsi) and one output (dso), where dso is specified as a dela y relative to the rising edge of the processor clock. see table 30-1 . the development system serves as the serial communication channel master and must generate dsclk. the serial channel operates at a frequency from dc to 1/5 of the clkout fr equency. the channel uses full-duplex mode, where data is se nt and received simultan eously by both master and slave devices. the transmission consists of 17-bit pack ets composed of a status/control bi t and a 16-bit data word. as shown in figure 30-12 , all state transitions are en abled on a rising edge of clk out when dsclk is high; that is, dsi is sampled and dso is driven. figure 30-12. bdm serial interface timing dsclk and dsi are synchronized inpu ts. dsclk acts as a pseudo cloc k enable and is sampled on the rising edge of the processor clock as well as the dsi. dso is delaye d from the dsclk- enabled clk rising edge (registered after a bdm state machine state change). all events in the debug module?s serial state machine are based on the processor clock rising edge. dscl k must also be sampled low (on a positive edge of clk) between each bit exchange. the msb is transferred first. because dso changes state based on an internally-recognized rising edge of dsclk, dsdo cannot be used to indicate the start of a serial transfer. the development system must count clock cycles in a given transfer. c1?c4 are described as follows: ? c1?first synchronization cycl e for dsi (dsclk is high). ? c2?second synchronization cycl e for dsi (dsclk is high). ? c3?bdm state machine changes state depending upon dsi and whether the entire input data transfer has been transmitted. ? c4?dso changes to next value. note a not-ready response can be ignored except during a memory-referencing cycle. otherwise, the debug module can accept a new serial transfer after 32 processor clock periods. 30.5.2.1 receive packet format the basic receive packet, figure 30-13 , consists of 16 data bits and 1 status bit clkout dsclk next state bdm state machine dso dsi current state current next past current c1 c2 c3 c4 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 debug support freescale semiconductor 30-19 . table 30-15 describes receive bdm packet fields. 30.5.2.2 transmit packet format the basic transmit packet, figure 30-14 , consists of 16 data bits and 1 control bit. table 30-16 describes transmit bdm packet fields. 30.5.3 bdm command set table 30-17 summarizes the bdm command se t. subsequent paragraphs cont ain detailed descriptions of each command. issuing a bdm command when the pr ocessor is accessing debug module registers using the wdebug instruction causes undefined behavior. 16 15 0 s data field [15:0] figure 30-13. receive bdm packet table 30-15. receive bdm packet field description bits name description 16 s status. indicates the status of cpu-generated messages listed below. the not-ready response can be ignored unless a memory-referencing cycle is in progress. otherwise, the debug module can accept a new serial transfer after 32 processor clock periods. s data message 0 xxxxvalid data transfer 0 0xffffstatus ok 1 0x0000not ready with response; come again 1 0x0001error?terminated bus cycle; data invalid 1 0xffffillegal command 15?0 d data. contains the message to be sent from the debug modul e to the development system. the response message is always a single word, with the data field encoded as shown above. 16 15 0 cd figure 30-14. transmit bdm packet table 30-16. transmit bdm packet field description bits name description 16 c control. this bit is reserved. command and data tr ansfers initiated by the development system should clear c. 15?0 d data bits 15?0. contains the data to be sent from the developm ent system to the debug module. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 debug support 30-20 freescale semiconductor unassigned command opcodes are re served by freescale. all unused command formats within any revision level perform a nop and return the illegal command response . 30.5.3.1 coldfire bdm command format all coldfire family bdm commands include a 16-bit operation word followed by an optional set of one or more extension words, as shown in figure 30-15 . table 30-17. bdm command summary command mnemonic description cpu state 1 1 general command effect and/or requirements on cpu operation: - halted. the cpu must be ha lted to perform this command. - steal. command generates bus cycles t hat can be interleaved with bus accesses. - parallel. command is executed in parallel with cpu activity. section command (hex) read a/d register rareg / rdreg read the selected address or data register and return the results through the serial interface. halted 30.5.3.3.1 0x218 {a/d, reg[2:0]} write a/d register wareg / wdreg write the data operand to the specified address or data register. halted 30.5.3.3.2 0x208 {a/d, reg[2:0]} read memory location read read the data at the memory location specified by the longword address. steal 30.5.3.3.3 0x1900?byte 0x1940?word 0x1980?longword write memory location write write the operand data to the memory location specified by the longword address. steal 30.5.3.3.4 0x1800?byte 0x1840?word 0x1880?longword dump memory block dump used with read to dump large blocks of memory. an initial read is executed to set up the starting address of the block and to retrieve the first result. a dump command retrieves subsequent operands. steal 30.5.3.3.5 0x1d00?byte 0x1d40?word 0x1d80?longword fill memory block fill used with write to fill large blocks of memory. an initial write is executed to set up the starting address of the block and to supply the first operand. a fill command writes subsequent operands. steal 30.5.3.3.6 0x1c00?byte 0x1c40?word 0x1c80?longword resume execution go the pipeline is flushed and refilled before resuming instruction execution at the current pc. halted 30.5.3.3.7 0x0c00 no operation nop perform no operation; may be used as a null command. parallel 30.5.3.3.8 0x0000 read control register rcreg read the system control register. halted 30.5.3.3.9 0x2980 write control register wcreg write the operand data to the system control register. halted 30.5.3.3.10 0x2880 read debug module register rdmreg read the debug module register. p arallel 30.5.3.3.11 0x2d {0x4 2 drc[4:0]} 2 0x4 is a three-bit field. write debug module register wdmreg write the operand data to the debug module register. parallel 30.5.3.3.12 0x2c {0x4 2 drc[4:0]} mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 debug support freescale semiconductor 30-21 table 30-18 describes bdm fields. 30.5.3.1.1 extension words as required some commands require extension words for addresses and/or immedi ate data. addresses require two extension words because only absolute long addres sing is permitted. longw ord accesses are forcibly longword-aligned and word accesses ar e forcibly word-aligned. immediat e data can be 1 or 2 words long. byte and word data each re quires a single extension word and longwor d data requires two extension words. operands and addresses are transferre d most-significant word first. in the following descriptions of the bdm command set, the optional set of extension word s is defined as address, data, or operand data. 30.5.3.2 command sequence diagrams the command sequence diagram in figure 30-16 shows serial bus traffi c for commands. each bubble represents a 17-bit bus transfer. the top half of each bubble indicates the data the development system sends to the debug module; the bo ttom half indicates the debug m odule?s response to the previous development system commands. command and resu lt transactions overlap to minimize latency. 15 1098765432 0 operation 0 r/w op size 0 0 a/d register extension word(s) figure 30-15. bdm command format table 30-18. bdm field descriptions bit name description 15?10 operation specifies the command. these values are listed in table 30-17 . 9 0 reserved, should be cleared. 8 r/w direction of operand transfer. 0 data is written to the cpu or to memory from the development system. 1 the transfer is from the cpu to the development system. 7?6 op size operand data size for sized operations. addr esses are expressed as 32-bit absolute values. note that a command performing a byte-sized memory read leaves the upper 8 bits of the response data undefined. referenced data is returned in the lower 8 bits of the response. operand size bit values 00 byte 8 bits 01 word 16 bits 10 longword 32 bits 11 reserved ? 5?4 00 reserved, should be cleared. 3 a/d address/data. determines whether the regist er field specifies a data or address register. 0 indicates a data register. 1 indicates an address register. 2?0 register contains the register number in commands that operate on processor registers. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 debug support 30-22 freescale semiconductor figure 30-16. command sequence diagram the sequence is as follows: ? in cycle 1, the development system command is issued ( read in this example). the debug module responds with either the low-orde r results of the prev ious command or a comm and complete status of the previous command, if no results are required. ? in cycle 2, the development system supplies the high-order 16 address bits. the debug module returns a not-ready response unless the received command is dec oded as unimplemented, which is indicated by the illegal command encoding. if this occurs, the development system should retransmit the command. note a not-ready response can be ignored except during a memory-referencing cycle. otherwise, the debug module can accept a new serial transfer after 32 processor clock periods. ? in cycle 3, the development system supplies the low-order 16 address bits. the debug module always returns a not-ready response. ? at the completion of cycle 3, the debug module initiates a memory read operation. any serial transfers that begin during a memory access return a not-ready response. ? results are returned in the two serial transfer cycles after the memory access completes. for any command performing a byte-sized memory read opera tion, the upper 8 bits of the response data are undefined and the referenced data is returned in the lower 8 bits. the ne xt command?s opcode is sent to the debug module during the fi nal transfer. if a memory or regi ster access is terminated with a bus error, the error status (s = 1, data = 0x0001) is returned instead of result data. 30.5.3.3 command set descriptions the following sections describe the commands summarized in table 30-17 . xxx ?not ready? read (long) ??? ms addr ?not ready? ls addr ?not ready? next cmd ?not ready? next cmd ?not ready? next cmd ls result commands transmitted to the debug module command code transmitted during this cycle high-order 16 bits of memory address low-order 16 bits of memory address non-serial-related next command code sequence taken if operation has not completed activity read memory location xxx berr xxx ms result xxx ?illegal? responses from the debug module results from previous command sequence taken if illegal command is received by debug module data used from this transfer sequence taken if bus error occurs on memory access high- and low-order 16 bits of result mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 debug support freescale semiconductor 30-23 note the bdm status bit (s) is 0 for normally completed commands; s = 1 for illegal commands, not-ready responses , and transfers with bus-errors. section 30.5.2, ?bdm serial interface ,? describes the receive packet format. freescale reserves unassigned command opcodes for future e xpansion. unused command formats in any revision level perform a nop and return an illegal command response. 30.5.3.3.1 read a/d register ( rareg / rdreg ) read the selected address or data register and return the 32-bit result. a bus error response is returned if the cpu core is not halted. command/result formats: command sequence: figure 30-18. rareg / rdreg command sequence operand data: none result data: the contents of the selected register are returned as a longword value, most-significant word first. 30.5.3.3.2 write a/d register ( wareg / wdreg ) the operand longword data is written to the specified address or data regi ster. a write alte rs all 32 register bits. a bus error response is returned if the cpu core is not halted. command format: 15 1211 87 432 0 command 0x2 0x1 0x8 a/d register result d[31:16] d[15:0] figure 30-17. rareg / rdreg command format 15 12 11 8 7 4 3 2 0 0x2 0x0 0x8 a/d register d[31:16] d[15:0] figure 30-19. wareg / wdreg command format rareg/rdreg ??? next cmd ls result next cmd ?not ready? xxx berr xxx ms result mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 debug support 30-24 freescale semiconductor command sequence figure 30-20. wareg / wdreg command sequence operand data longword data is wri tten into the specified address or data register. the data is supplied most-significant word first. result data command complete status is i ndicated by returning 0xffff (with s cleared) when the register write is complete. 30.5.3.3.3 read memory location ( read ) read data at the longword addr ess. address space is defined by baar[tt,tm]. hardware forces low-order address bits to zeros for word and longword accesse s to ensure that word addresses are word-aligned and longword addr esses are longword-aligned. wareg/wdreg ??? ls data ?not ready? next cmd ?not ready? xxx berr ms data ?not ready? next cmd ?cmd complete? mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 debug support freescale semiconductor 30-25 command/result formats: command sequence: figure 30-22. read command sequence operand data the only operand is the longw ord address of the requested location. result data word results return 16 bits of data; l ongword results return 32. bytes are returned in the lsb of a word result; the upper byte is undefined. 0x0001 (s = 1) is returned if a bus error occurs. 15 12 11 8 7 4 3 0 byte command 0x1 0x9 0x0 0x0 a[31:16] a[15:0] resultxxxxxxxx d[7:0] word command 0x1 0x9 0x4 0x0 a[31:16] a[15:0] result d[15:0] longword command 0x1 0x9 0x8 0x0 a[31:16] a[15:0] result d[31:16] d[15:0] figure 30-21. read command/result formats xxx ?not ready? read (long) ??? ms addr ?not ready? ls addr ?not ready? next cmd ?not ready? next cmd ls result read memory location xxx berr xxx ms result xxx ?not ready? read (b/w) ??? ms addr ?not ready? ls addr ?not ready? next cmd ?not ready? read memory location xxx berr next cmd result mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 debug support 30-26 freescale semiconductor 30.5.3.3.4 write memory location ( write ) write data to the memory location specified by the longword address. the addr ess space is defined by baar[tt,tm]. hardware forces low-order address bits to zeros for word and longword accesses to ensure that word addresses are word-aligned and longword addresses are longword-aligned. command formats: 15 12 11 8 7 4 3 1 byte 0x1 0x8 0x0 0x0 a[31:16] a[15:0] xxxxxxxx d[7:0] word 0x1 0x8 0x4 0x0 a[31:16] a[15:0] d[15:0] longword 0x1 0x8 0x8 0x0 a[31:16] a[15:0] d[31:16] d[15:0] figure 30-23. write command format mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 debug support freescale semiconductor 30-27 command sequence: figure 30-24. write command sequence operand data this two-operand instruction require s a longword absolute a ddress that specifies a location to which the data op erand is to be written. byte data is sent as a 16-bit word, justified in the lsb; 16- and 32-bit operands are sent as 16 and 32 bits, respectively result data command complete status is i ndicated by returning 0xffff (with s cleared) when the register wr ite is complete. a value of 0x0001 (with s set) is returned if a bus error occurs. 30.5.3.3.5 dump memory block ( dump ) dump is used with the read command to access large bloc ks of memory. an initial read is executed to set up the starting address of th e block and to retrieve the first result. if an initial read is not executed before the first dump , an illegal command resp onse is returned. the dump command retrieves subsequent operands. the initial addres s is incremented by the operand size (1, 2, or 4) and saved in a temporary register. subsequent dump commands use this address, perfor m the memory read, increment it by the current operand size, and store the update d address in the temporary register. xxx ?not ready? write (long) ??? ms addr ?not ready? ls addr ?not ready? write memory location next cmd ?cmd complete? ms data ?not ready? next cmd ?not ready? xxx berr xxx ?not ready? write (b/w) ??? ms addr ?not ready? ls addr ?not ready? write memory location next cmd ?cmd complete? data ?not ready? next cmd ?not ready? xxx berr ls data ?not ready? mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 debug support 30-28 freescale semiconductor note dump does not check for a valid address; it is a valid command only when preceded by nop , read , or another dump command. otherwis e, an illegal command response is returned. nop can be used for intercommand padding without corrupting the address pointer. the size field is examined each time a dump command is processed, allowing the operand size to be dynamically altered. command/result formats: 15 12 11 8 7 4 3 0 byte command 0x1 0xd 0x0 0x0 result xxxxxxxx d[7:0] word command 0x1 0xd 0x4 0x0 result d[15:0] longword command 0x1 0xd 0x8 0x0 result d[31:16] d[15:0] figure 30-25. dump command/result formats mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 debug support freescale semiconductor 30-29 command sequence: figure 30-26. dump command sequence operand data: none result data: requested data is re turned as either a word or longword. byte data is returned in the least-significant byte of a word result. word results return 16 bits of significant data; longword results return 32 bits. a valu e of 0x0001 (with s set) is returned if a bus error occurs. 30.5.3.3.6 fill memory block ( fill ) a fill command is used with the write command to access large bloc ks of memory. an initial write is executed to set up the starting address of the block and to supply the first operand. the fill command writes subsequent operands. the init ial address is incremented by the ope rand size (1, 2, or 4) and saved in a temporary register after the memory write. subsequent fill commands use this address, perform the write, increment it by the current operand size, and store the updated address in the temporary register. if an initial write is not executed preceding the first fill command, the illegal command response is returned. note the fill command does not check for a valid address? fill is a valid command only when preceded by another fill , a nop , or a write command. otherwise, an illegal comma nd response is returned. the nop command can be used for intercommand padding wit hout corrupting the address pointer. the size field is examined each time a fill command is processed, allowing the operand size to be altered dynamically. command formats: xxx ?not ready? dump (b/w) ??? xxx ?illegal? next cmd ?not ready? next cmd ?not ready? read memory location xxx berr next cmd result xxx ?not ready? dump (long) ??? xxx ?illegal? next cmd ?not ready? next cmd ?not ready? read memory location xxx berr next cmd ms result next cmd ls result mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 debug support 30-30 freescale semiconductor command sequence: figure 30-28. fill command sequence operand data: a single opera nd is data to be writte n to the memory location. byte data is sent as a 16-bit word, justified in the least-si gnificant byte; 16- and 32-bit operands are sent as 16 and 32 bits, respectively. result data: command complete status (0xffff) is returned when the register write is complete. a value of 0x0001 (with s set) is returned if a bus error occurs. 15 12 11 8 7 4 3 0 byte 0x1 0xc 0x0 0x0 xxxxxxxx d[7:0] word 0x1 0xc 0x4 0x0 d[15:0] longword 0x1 0xc 0x8 0x0 d[31:16] d[15:0] figure 30-27. fill command format xxx ?not ready? fill (b/w) ??? data ?not ready? next cmd ?not ready? write memory location xxx berr next cmd ?cmd complete? xxx ?illegal? next cmd ?not ready? xxx ?not ready? fill (long) ??? ms data ?not ready? ls data ?not ready? write memory location xxx berr next cmd ?cmd complete? xxx ?illegal? next cmd ?not ready? next cmd ?not ready? mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 debug support freescale semiconductor 30-31 30.5.3.3.7 resume execution ( go ) the pipeline is flushed a nd refilled before normal in struction execution resumes. prefetching begins at the current address in the pc and at the current privilege leve l. if any register (such as the pc or sr) is altered by a bdm command while the processo r is halted, the updated value is used when prefetching resumes. if a go command is issued and the cpu is not halted, the command is ignored. command sequence: figure 30-30. go command sequence operand data: none result data: the command-complete response ( 0xffff) is returned during the next shift operation. 30.5.3.3.8 no operation ( nop ) nop performs no operation and may be us ed as a null command where required. command formats: command sequence: figure 30-32. nop command sequence operand data: none result data: the command-complete response, 0xffff (with s cleared), is returned during the next shift operation. 30.5.3.3.9 read control register ( rcreg ) reads the selected control register and returns the 32- bit result. accesses to the processor/memory control registers are always 32 bits wide, regardless of register width. the se cond and third words of the command form a 32-bit address, which the debug module uses to generate a special bus cycle to access the specified control register. the 12-bit rc field is the same as that used by the movec instruction. 15 12 11 8 7 4 3 0 0x0 0xc 0x0 0x0 figure 30-29. go command format 15 12 11 8 7 4 3 0 0 x 00 x 00 x 00 x 0 figure 30-31. nop command format go ??? next cmd ?cmd complete? nop ??? next cmd ?cmd complete? mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 debug support 30-32 freescale semiconductor command/result formats: rc encoding: 15 12 11 8 7 4 3 0 command 0x2 0x9 0x8 0x0 0x0 0x0 0x0 0x0 0x0 rc result d[31:16] d[15:0] figure 30-33. rcreg command/result formats table 30-19. control register map rc register definition 0x002 cache control register (cacr) 0x004 access control register (acr0) 0x005 access control register (acr1) 0x800 other stack pointer (other_a7) 0x801 vector base register (vbr) 0x804 mac status register (macsr) 0x805 mac mask register (mask) 0x806 mac accumulator 0 (acc0) 0x807 mac accumulator 0,1 extension bytes (accext01) 0x808 mac accumulator 2,3 extension bytes (accext23) 0x809 mac accumulator 1 (acc1) 0x80a mac accumulator 2 (acc2) 0x80b mac accumulator 3 (acc3) 0x80e status register (sr) 0x80f program register (pc) 0xc04 flash base address register 0 (flashbar) (not on mcf5280) 0xc05 ram base address register (rambar) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 debug support freescale semiconductor 30-33 command sequence: figure 30-34. rcreg command sequence operand data: the only operand is the 32-bi t rc control register select field. result data: control regist er contents are returned as a l ongword, most-significant word first. the implemented portion of registers smaller than 32 bi ts is guaranteed correct; other bits are undefined. bdm accesses of the stack pointer registers (a7: ssp, usp) the processor?s version 2 coldfire core supports two unique stack pointer (a7) registers: the supervisor stack pointer (ssp) and th e user stack pointer (usp). the ha rdware implementation of these two programmable-visible 32-bit register s does not uniquely identify one as the ssp and the other as the usp. rather, the hardware uses one 32-bit register as the currentl y-active a7 and the ot her register is named simply the ?other_a7?. thus, the contents of the two hardware registers is a f unction of the operating mode of the processor: if sr[s] = 1 then a7 = supervisor stack pointer other_a7 = user stack pointer else a7 = user stack pointer other_a7 = supervisor stack pointer the bdm programming model supports re ads and writes to the a7 and ot her_a7 registers directly. it is the responsibility of the external development system to determin e the mapping of the two hardware registers (a7, other_a7) to the two program-visible definitions (supervis or and user stack pointers), based on the supervisor bit of the status register. bdm accesses of the emac registers the presence of rounding logic in th e output datapath of the emac re quires that special care be taken during any bdm-initiated reads and writ es of its programming mode l. in particular, it is necessary that any result rounding modes be disa bled during the read/write process so the exact bi t-wise contents of the emac registers are accessed. as an example, any bdm read of an accumulator register (accn) must be preceded by two commands accessing the mac status register. specifical ly, the following bdm sequence is required: bdmreadaccn ( rcreg macsr; // read macsr contents & save wcreg #0,macsr; // disable all rounding modes xxx ?not ready? rcreg ??? ms addr ?not ready? ms addr ?not ready? next cmd ?not ready? read control register xxx berr next cmd ms result next cmd ls result mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 debug support 30-34 freescale semiconductor rcreg accn; // read the desired accumulator wcreg #saved_data,macsr;// restore the original macsr ) likewise, the following bdm sequence is n eeded to write an accumulator register: bdmwriteaccn ( rcreg macsr; // read macsr contents & save wcreg #0,macsr; // disable all rounding modes wcreg #data,accn; // write the desired accumulator wcreg #saved_data,macsr;// restore the original macsr ) additionally, it is required that writ es to the accumulator extension registers be performed after the corresponding accumulators are updated. this is needed since a write to any accumulator alters the contents of the corres ponding extension register. for more information on saving and restoring the complete emac programming model, see section 3.3.1.2, ?saving and restori ng the emac programming model ?. 30.5.3.3.10 write control register ( wcreg ) the operand (longword) data is written to the specified c ontrol register. the write al ters all 32 register bits. command/result formats: 15 12 11 8 7 4 3 0 command 0x2 0x8 0x8 0x0 0x0 0x0 0x0 0x0 0x0 rc result d[31:16] d[15:0] figure 30-35. wcreg command/result formats mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 debug support freescale semiconductor 30-35 command sequence: figure 30-36. wcreg command sequence operand data: this instruction re quires two longword operands. the first selects the register to which the operand data is to be wri tten; the second contains the data. result data: successful write operations return 0xffff. bus errors on the write cycle are indicated by the setting of bit 16 in the status message and by a data pattern of 0x0001. 30.5.3.3.11 read debug module register ( rdmreg ) read the selected de bug module register a nd return the 32-bit result. the onl y valid register selection for the rdmreg command is csr (drc = 0x00). note that this re ad of the csr clears csr[fof, trg, halt, bkpt]; as well as the trigger stat us bits (csr[bstat]) if either a level-2 breakpoint has been triggered or a level-1 breakpoint has b een triggered and no level-2 breakpoint has been enabled. command/result formats: table 30-20 shows the definition of drc encoding. 15 12 11 8 7 5 4 0 command 0x2 0xd 100 drc result d[31:16] d[15:0] figure 30-37. rdmreg command/result formats table 30-20. definition of drc encoding?read drc[4:0] debug register defini tion mnemonic initial state page 0x00 configuration/status csr 0x0 p. 30-10 0x01?0x1f reserved ? ? ? xxx ?not ready? wcreg ??? ms addr ?not ready? ms addr ?not ready? write control register next cmd ?cmd complete? ms data ?not ready? next cmd ?not ready? xxx berr ls data ?not ready? mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 debug support 30-36 freescale semiconductor command sequence: figure 30-38. rdmreg command sequence operand data: none result data: the contents of th e selected debug register are retu rned as a longword value. the data is returned most-significant word first. 30.5.3.3.12 write debug module register ( wdmreg ) the operand (longword) data is writte n to the specified debug module regi ster. all 32 bits of the register are altered by the write. dsclk must be inactive while the debug module register writes from the cpu accesses are performed usi ng the wdebug instruction. command format: table 30-3 shows the definition of the drc write encoding. command sequence: figure 30-40. wdmreg command sequence operand data: longword data is written into the specified debug register. the data is supplied most-significant word first. result data: command complete st atus (0xffff) is returned when register write is complete. 15 12 11 8 7 5 4 0 0x2 0xc 100 drc d[31:16] d[15:0] figure 30-39. wdmreg bdm command format rdmreg ??? xxx ms result next cmd ls result xxx ?illegal? next cmd ?not ready? wdmreg ??? ms data ?not ready? ls data ?not ready? xxx ?illegal? next cmd ?not ready? next cmd ?cmd complete? mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 debug support freescale semiconductor 30-37 30.6 real-time debug support the coldfire family provides support debugging real-time applications . for these types of embedded systems, the processor must continue to operate during debug. the foundation of this area of debug support is that while the processor cannot be halted to allow debugging, the syst em can generally tolerate small intrusions into the real-time operation. the debug module provides three t ypes of breakpoints?pc with mas k, operand address range, and data with mask. these breakpoints can be configured into one- or two-level triggers with the exact trigger response also programmabl e. the debug module programming model can be written from either the external development system usi ng the debug serial interface or from the processor?s supervisor programming model using the wdeb ug instruction. only csr is readable using the external development system. 30.6.1 theory of operation breakpoint hardware can be configured to respond to triggers in several ways. the response desired is programmed into tdr. as shown in table 30-21 , when a breakpoint is triggered, an indication (csr[bstat]) is provided on the ddata output port when it is not disp laying captured processor status, operands, or branch addresses. the breakpoint status is also posted in the csr. note that csr[bstat] is cleared by a csr read when either a level-2 breakpoint is triggered or a level-1 breakpoint is triggered and a level-2 breakpoint is not enabled. status is also cleared by writing to tdr. bdm instructions use the appropriate registers to lo ad and configure breakpoints. as the system operates, a breakpoint trigger generates the response defined in tdr. pc breakpoints are treated in a precise manner?excep tion recognition and processi ng are initiated before the excepting instruction is executed. all other breakpoint events are re cognized on the processor?s local bus, but are made pending to the proc essor and sampled like other interr upt conditions. as a result, these interrupts are imprecise. in systems that tolerate the processor being halted, a bdm-en try can be used. with tdr[trc] = 01, a breakpoint trigger causes the core to halt (pst = 0xf). if the processor core cannot be halted, the debug interrupt can be used. with this configuration, tdr[trc] = 10, the breakpoint trigger becomes a debug interrupt to the pr ocessor, which is treated higher than the nonmaskable level-7 interr upt request. as with al l interrupts, it is made pending until the processor reaches a sample point, which occurs once per instruction. again, the hardware forces the pc breakpoint to occur before the target ed instruction executes. this is possible because th e pc breakpoint is table 30-21. ddata[3:0]/csr[bstat] breakpoint response ddata[3:0]/csr[bstat] 1 1 encodings not shown are reserved for future use. breakpoint status 0000/0000 no breakpoints enabled 0010/0001 waiting for level-1 breakpoint 0100/0010 level-1 breakpoint triggered 1010/0101 waiting for level-2 breakpoint 1100/0110 level-2 breakpoint triggered mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 debug support 30-38 freescale semiconductor enabled when interrupt sampling occurs. for addres s and data breakpoints, reporting is considered imprecise because several instructi ons may execute after the triggeri ng address or data is detected. as soon as the debug interrupt is recognized, the processor aborts execution and initiates exception processing. this event is signaled externally by the assertion of a unique pst value (pst = 0xd) for multiple cycles. the core enters emulator mode when exception processing begins. after the standard 8-byte exception stack is created, the processor fetches a unique ex ception vector, 12, from the vector table. execution continues at the instruct ion address in the vector correspondi ng to the breakpoint triggered. all interrupts are ignored while the pr ocessor is in emulator mode. th e debug interrupt handler can use supervisor instructions to save the necessary context such as the state of all pr ogram-visible registers into a reserved memory area. when debug interrupt operations comp lete, the rte instruction executes and the processor exits emulator mode. after the debug interrupt handl er completes execution, the extern al development system can use bdm commands to read the reserved memory locations. if a hardware breakpoint such as a pc trigger is left unmodified by the debug interrupt service routine, another debug interrupt is ge nerated after the completion of the rte instruction. 30.6.1.1 emulator mode emulator mode is used to facilitate non-intrusive emulator functionality. this mode can be entered in three different ways: ? setting csr[emu] forces the processor into emulator mode. emu is examined only if rsti is negated and the processor begins reset exception processing. it can be set while the processor is halted before reset exception processing begins. see section 30.5.1, ?cpu halt .? ? a debug interrupt always puts the processor in emulation mode when debug interrupt exception processing begins. ? setting csr[trc] forces the processor into emulation mode when trace exception processing begins. while operating in emulation mode, the processor exhibits the following properties: ? all interrupts are ignored, including level-7 interrupts. ? if csr[map] = 1, all caching of memory and the sram module are di sabled. all memory accesses are forced into a sp ecially mapped address space si gnaled by tt = 0x2, tm = 0x5 or 0x6. this includes stack frame writes a nd the vector fetch for the excepti on that forced entry into this mode. the rte instruction exits emulati on mode. the processor status outpu t port provides a unique encoding for emulator mode entry (0xd) and exit (0x7). 30.6.2 concurrent bdm an d processor operation the debug module supports concurrent operation of both the processor and mo st bdm commands. bdm commands may be executed wh ile the processor is running, except t hose following operations that access processor/memory registers: ? read/write address and data registers ? read/write control registers for bdm commands that access memory, the debug m odule requests the processor?s local bus. the processor responds by stalling the in struction fetch pipeli ne and waiting for cu rrent bus activity to mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 debug support freescale semiconductor 30-39 complete before freeing the local bus for the de bug module to perform its acce ss. after the debug module bus cycle, the processor reclaims the bus. breakpoint registers must be carefull y configured in a development syst em if the processor is executing. the debug module contains no hardware interlocks, so tdr should be di sabled while breakpoint registers are loaded, after which tdr can be wr itten to define the exact trigger. this prevents spurious breakpoint triggers. because there are no hardware interlocks in the de bug unit, no bdm operations are allowed while the cpu is writing the debug?s register s (dsclk must be inactive). note that the debug module requires the use of the internal bus to perform bdm commands. in revision a, if the processor is executing a tight loop that is contained within a single alig ned longword, the processor may never grant the internal bus to the debug module, for example: align4 label1: nop bra.b label1 or align4 label2: bra.w label2 the processor grants the internal bus if these loops are forced across two longwords. 30.7 processor status, ddata definition this section specifies the coldfire processor and debug m odule?s generation of the processor status (pst) and debug data (ddata) out put on an instruction basis. in ge neral, the pst/ddata output for an instruction is defined as follows: pst = 0x1, {pst = [0x89b], ddata= operand} where the {...} definition is optional operand info rmation defined by the setting of the csr. the csr provides capabilities to display operands base d on reference type (read, write, or both). a pst value {0x8, 0x9, or 0xb} identi fies the size and presen ce of valid data to foll ow on the ddata output {1, 2, or 4 bytes}. additionally, for ce rtain change-of-flow branch inst ructions, csr[btb] provides the capability to display the target instruction addr ess on the ddata output {2, 3, or 4 bytes} using a pst value of {0x9, 0xa, or 0xb}. 30.7.1 user instruction set table 30-22 shows the pst/ddata specificati on for user-mode instructions. rn represents any {dn, an} register. in this definition, the ?y ? suffix generally denotes the sour ce and ?x? denotes the destination operand. for a given instruc tion, the optional operand data is displayed only for t hose effective addresses referencing memory. the ?dd? nomencl ature refers to the ddata outputs. table 30-22. pst/ddata specification for user-mode instructions instruction operand syntax pst/ddata add.l debug support 30-40 freescale semiconductor addq.l #imm, debug support freescale semiconductor 30-41 extb.l dx pst = 0x1 ff1.l dx pst = 0x1 jmp debug support 30-42 freescale semiconductor exception processingpst = 0xc,{pst = 0xb,dd = destination},// stack frame {pst = 0xb,dd = destination},// stack frame {pst = 0xb,dd = source},// vector read pst = 0x5,{pst = [0x9ab],dd = target}// handler pc the pst/ddata specification for the reset exception is shown below: exception processingpst = 0xc, pst = 0x5,{pst = [0x9ab],dd = target} // handler pc the initial references at address 0 and 4 are never captur ed nor displayed since these accesses are treated as instruction fetches. rts pst = 0x1, {pst = 0xb, dd = source operand}, pst = 0x5, {pst = [0x9ab], dd = target address} scc dx pst = 0x1 sub.l debug support freescale semiconductor 30-43 for all types of exception processing, the pst = 0xc value is driven at all times, unless the pst output is needed for one of the optional marker values or for the taken branch indicator (0x5). table 30-23 shows the pst/ddata specification fo r multiply-accumulat e instructions. 30.7.2 supervisor instruction set the supervisor instruction set has complete access to the user mode instructi ons plus the opcodes shown below. the pst/ddata specificati on for these opcodes is shown in table 30-24 . table 30-23. pst/ddata specif ication for mac instructions instruction operand syntax pst/ddata mac.l ry,rx,accx pst = 0x1 mac.l ryrx, debug support 30-44 freescale semiconductor the move-to-sr, stldsr, and rte in structions include an optional ps t = 0x3 value, indi cating an entry into user mode. additionally, if the execution of a rt e instruction returns the pr ocessor to emulator mode, a multiple-cycle status of 0xd is signaled. similar to the exception processi ng mode, the stopped state (pst = 0xe ) and the halted state (pst = 0xf) display this status throughout the entire time the coldfire processor is in the given mode. rte pst = 0x7, {pst = 0xb, dd = source operand}, {pst = 3}, {pst=0xb, dd =source operand}, pst = 0x5, {[pst = 0x9ab], dd = target address} stldsr.w #imm pst = 0x1, {pst = 0xa, dd = destination operand, pst = 0x3} stop #imm pst = 0x1, pst = 0xe wdebug debug support freescale semiconductor 30-45 30.8 freescale-recommended bdm pinout the coldfire bdm connector, figure 30-41 , is a 26-pin berg connector arranged 2 x 13. figure 30-41. recommended bdm connector 1 3 5 7 9 11 13 15 17 19 21 23 25 2 4 6 8 10 12 14 16 18 20 22 24 26 developer reserved 1 gnd gnd reset pad-voltage 2 gnd pst2 pst0 ddata2 ddata0 freescale reserved gnd core-voltage bkpt dsclk developer reserved 1 dsi dso pst3 pst1 ddata3 ddata1 gnd freescale reserved clkout 2 supplied by target 1 pins reserved for bdm developer use. ta mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 debug support 30-46 freescale semiconductor mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor 31-1 chapter 31 ieee 1149.1 test access port (jtag) the joint test action group, or jtag, is a dedicated us er-accessible test logic, that complies with the ieee 1149.1 standard for boundary-scan testability, to help with system diag nostic and manufacturing testing. this architecture provides access to all data and chip control pins from the board-edge connector through the standard four-pin test access port (tap) and the jtag reset pin, trst . figure 31-1 shows the block diagram of the jtag module. figure 31-1. jtag block diagram 4-bit tap instruction register 30 1-bit bypass register 148-bit boundary scan register 32-bit idcode register trst /dsclk tclk tms/bkpt 0 31 0 147 tap controller tdi/dsi 1 0 tdo/dso jtag module to debug module 7-bit jtag_cfm_clkdiv register 0 6 3-bit test_ctrl register 0 2 4-bit tap instruction decoder 1 0 disable dsclk force bkpt = 1 dsi = 0 jtag_en dso dsi bkpt dsclk mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 ieee 1149.1 test access port (jtag) 31-2 freescale semiconductor 31.1 features the basic features of the jtag module are the following: ? performs boundary-scan operations to te st circuit board electrical continuity ? bypasses instruction to reduce the sh ift register path to a single cell ? sets chip output pins to safety stat es while executing the bypass instruction ? samples the system pins during operati on and transparently shift out the result ? selects between jtag tap controller and background debug module (bdm) using a dedicated jtag_en pin 31.2 modes of operation the jtag_en pin can select between the following modes of operation: ? jtag mode ? bdm - background debug mode (for more information, refer to section 30.5, ?background debug mode (bdm) ).? 31.3 external signal description the jtag module has five input and one out put external signals, as described in table 31-1 . 31.3.1 detailed signal description 31.3.1.1 jtag_en ? jtag enable the jtag_en pin selects betwee n debug module and jtag. if jtag_e n is low, the debug module is selected; if it is high, the jtag is selected. table 31-2 summarizes the pin f unction selected depending upon jtag_en logic state. table 31-1. signal properties name direction function reset state pull up jtag_en input jtag/bdm selector input ? ? tclk input jtag test clock input ? active tms/bkpt input jtag test mode select / bdm breakpoint ? active tdi/dsi input jtag test data input / bdm development serial input ? active trst /dsclk input jtag test reset input / bdm development serial clock ? active tdo/dso output jtag test data output / bd m development serial output hi-z / 0 ? table 31-2. pin function selected jtag_en = 0 jtag_en = 1 pin name mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 ieee 1149.1 test access port (jtag) freescale semiconductor 31-3 when one module is selected, the inpu ts into the other module are disabled or forced to a known logic level as shown in table 31-3 , in order to disable the corresponding module. note the jtag_en does not support dynami c switching between jtag and bdm modes. 31.3.1.2 tclk ? test clock input the tclk pin is a dedicated jtag clock input to synchronize the test logic. pulses on tclk shift data and instructions into the tdi pin on the rising edge and out of the tdo pin on the falling edge. tclk is independent of the processo r clock. the tclk pin has an internal pull-up resist or and holding tclk high or low for an indefinite period does not cause jtag test logic to lose state information. 31.3.1.3 tms/bkpt ? test mode select / breakpoint the tms pin is the test mode select input that se quences the tap state machine. tms is sampled on the rising edge of tclk. the tms pin has an internal pull-up resistor. the bkpt pin is used to request an exte rnal breakpoint. assertion of bkpt puts the processor into a halted state after the current instruction completes. 31.3.1.4 tdi/dsi ? test data in put / development serial input the tdi pin is the lsb-first data and instruction in put. tdi is sampled on the rising edge of tclk. the tdi pin has an internal pull-up resistor. the dsi pin provides data input for the debug module serial communication port. 31.3.1.5 trst /dsclk ? test reset / development serial clock the trst pin is an active low asynchronous reset input with an internal pull-up resistor that forces the tap controller to the test-logic-reset state. module selected bdm jtag ? pin function ? bkpt dsi dso dsclk tclk tms tdi tdo trst tclk bkpt dsi dso dsclk table 31-3. signal state to the disable module jtag_en = 0 jtag_en = 1 disabling jtag trst = 0 tms = 1 ? disabling bdm ? disable dsclk dsi = 0 bkpt = 1 table 31-2. pin function selected mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 ieee 1149.1 test access port (jtag) 31-4 freescale semiconductor the dsclk pin clocks the serial communication port to the debug module. maximum frequency is 1/5 the processor clock speed. at the rising edge of dsclk, the data input on dsi is sampled and dso changes state. 31.3.1.6 tdo/dso ? test data output / development serial output the tdo pin is the lsb-first data output. data is cl ocked out of tdo on the fa lling edge of tclk. tdo is tri-stateable and is actively driven in the shift-ir and shift-dr controller states. the dso pin provides serial output data in bdm mode. 31.4 memory map/register definition 31.4.1 memory map the jtag module registers are not memory mapped and are only accessible through the tdo/dso pin. 31.4.2 register descriptions all registers are shift-in and parallel load. 31.4.2.1 instruction shift register (ir) the jtag module uses a 4-bit shift register with no parity. the ir tr ansfers its value to a parallel hold register and applies an instructi on on the falling edge of tclk when the tap state machine is in the update-ir state. to load an instruc tion into the shift portion of the ir, place the seri al data on the tdi pin before each rising edge of tclk. th e msb of the ir is the bit closest to the tdi pin, and the lsb is the bit closest to the tdo pin. 31.4.2.2 idcode register the idcode is a read-only register; its value is chip dependent. for more information, see section 31.5.3.2, ?idcode instruction .? 31 28 27 22 21 16 field prn[[3:0] dc[5:0] pin[9:0] reset prn[3] prn[2] prn[1] prn[0] 0111_01 pi n[9] pin[8] pin[7] pi n[6] pin[5] pin[4] r/w read only 15 12 11 10 field pin[9:0] jedec[10] id reset 0000_0000_0000_0000 r/w read only figure 31-2. idcode register mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 ieee 1149.1 test access port (jtag) freescale semiconductor 31-5 31.4.2.3 bypass register the bypass register is a single-bit shift register path from tdi to tdo when the bypass instruction is selected. 31.4.2.4 jtag_cfm_clkdiv register the jtag_cfm_clkdiv register is a 7-bit clock divider for the cfm that is used with the lockout_recovery instruction. it controls the peri od of the clock used for timed events in the cfm erase algorithm. the jtag_cfm_cl kdiv register must be loaded before the lockout sequence can begin. 31.4.2.5 test_ctrl register the test_ctrl register is a 3-bit shift register path from tdi to tdo when the enable_test_ctrl instruction is selected. the test_ctrl transfer s its value to a parallel hold register on the rising edge of tclk when th e tap state machine is in the update-dr state. 31.4.2.6 boundary scan register the boundary scan register is connected between tdi and tdo when the extest or sample/preload instruction is selected. it captures input pin data, forces fi xed values on output pins, and selects a logic value and direct ion for bidirectional pins or hi gh impedance for tri-stated pins. the boundary scan register cont ains bits for bonded-out and non bonded-out signals excluding jtag signals, analog signals, power supplies, comp liance enable pins, and clock signals. 31.5 functional description 31.5.1 jtag module the jtag module consists of a tap controller state machine, which is responsible for generating all control signals that execute the jtag inst ructions and read/wr ite data registers. table 31-4. idcode regi ster field descriptions bits name description 31?28 prn part revision number. indicate the revision number of the project. 27?22 dc design center. 21?12 pin part identification number. indicate the device number. 11?1 jedec joint electron device engineering council id bits. indicate the reduced jedec id for freescale. 0 id idcode register id. this bit is set to 1 to identify the register as the idcode register and not the bypass register according to the ieee standard 1149.1. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 ieee 1149.1 test access port (jtag) 31-6 freescale semiconductor 31.5.2 tap controller the tap controller is a state mach ine that changes state based on the sequence of logical values on the tms pin. figure 31-3 shows the machine?s states. the value show n next to each state is the value of the tms signal sampled on the rising edge of the tclk signal. asserting the trst signal asynchronously resets the tap contro ller to the test-logic-reset state. as figure 31-3 shows, holding tms at logic 1 while clocking tclk through at least five rising edges also causes the state machine to en ter the test-logic-reset state, whatever the initial state. figure 31-3. tap controller state machine flow 31.5.3 jtag instructions table 31-5 describes public and private instructions. run-test/idle test-logic-reset 1 1 select dr-scan capture-dr exit1-dr pause-dr update-dr select ir-scan shift-dr exit2-dr capture-ir shift-ir exit1-ir pause-ir exit2-ir update-ir 0 0 1 1 0 0 0 1 1 10 0 0 1 1 0 0 1 1 0 1 0 1 10 1 1 0 0 1 0 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 ieee 1149.1 test access port (jtag) freescale semiconductor 31-7 31.5.3.1 external test instruction (extest) the extest instruction selects the boundary scan register. it forces al l output pins and bidirectional pins configured as outputs to the values preloaded with the sample/preload instruction and held in the boundary scan update regist ers. extest can also configure the di rection of bidire ctional pins and establish high-impedance stat es on some pins. extest asserts internal reset fo r the mcu system logic to force a predictable internal state while pe rforming external boundary scan operations. 31.5.3.2 idcode instruction the idcode instruction selects the 32-bit idcode register for connection as a sh ift path between the tdi and tdo pin. this instruction allows interrogation of the mcu to determine its ve rsion number and other part identification data. the shift register lsb is forced to logic 1 on the ri sing edge of tclk following entry into the capture-dr state.therefore, the first bit to be shifte d out after selecting the idcode register is always a logic 1. the remaining 31 bits are also forced to fixed values on the rising edge of tclk following entr y into the capture-dr state. idcode is the default instruction placed into the inst ruction register when the tap resets. thus, after a tap reset, the idcode register is selected automatically. 31.5.3.3 sample/preload instruction the sample/preload instru ction has two functions: ? sample - obtain a sample of the system data a nd control signals present at the mcu input pins and just before the boundary scan cell at the output pins. this sampling occurs on the rising edge of tclk in the capture-dr state when the ir contains the $2 opcode. the sampled data is table 31-5. jtag instructions instruction ir[3:0] instruction summary extest 0000 selects boundary scan register while applying fixed values to output pins and asserting functional reset idcode 0001 selects idcode register for shift sample/preload 0010 selects boundary scan register for shifting, sampling, and preloading without disturbing functional operation test_leakage 1,2 1 instruction for manufacturing purposes only 2 trst pin assertion or power-on reset is required to exit this instruction. 0101 selects bypass register while tri-stating all output pins and assert to high the jtag_leakage signal enable_test_ctrl 0110 selects test_ctrl register highz 1001 selects bypass register while tri-stating all output pins and asserting functional reset lockout_recovery 1011 allows for the erase of the tfm flash when the part is secure clamp 1100 selects bypass while applying fixed values to output pins and asserting functional reset bypass 1111 selects bypass register for data operations reserved all others decoded to select bypass register 3 3 freescale reserves the right to change the decoding of the unused opcodes in the future. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 ieee 1149.1 test access port (jtag) 31-8 freescale semiconductor accessible by shifting it through the boundary scan register to the tdo output by using the shift-dr state. both the data capture and the shift operation are transparent to system operation. note external synchronization is required to achieve meaningful results because there is no internal synchronization between tclk and the system clock. ? preload - initialize the boundary scan register update cells before selecting extest or clamp. this is achieved by ignoring the data shifting out on the tdo pin and shifting in initialization data. the upda te-dr state and the falling edge of tclk can then transfer this data to the update cells. the data is applied to the ex ternal output pins by the extest or clamp instruction. 31.5.3.4 test_leakage instruction the test_leakage instruction forces the jtag_leakage output signal to high. it is intende d to tri-state all output pad buffers and disable all of the part?s pad input buffers except test and trst. the jtag_leakage signal is asserted at the rising edge of tclk when th e tap controller transitions from update-ir to run-test/idle state. once asserted, the part disables the tclk, tms, and tdi inputs into jtag and forces these jtag inputs to logic 1. the tap controller rema ins in the run-test/idle state until the trst input is asserted (logic 0). 31.5.3.5 enable_test_ctrl instruction the enable_test_ctrl instruction selects a 3-bit shift register (test_ctrl) for connection as a shift path between the tdi and tdo pin. when the user transitions th e tap controller to the update_dr state, the register transfers its value to a parallel hol d register. it allows the control chip to test functions independent of the jt ag tap controller state. 31.5.3.6 highz instruction the highz instruction eliminates th e need to backdrive the output pi ns during circuit-board testing. highz turns off all output drivers, including the 2-state drivers, a nd selects the bypass register. highz also asserts internal reset for the mcu system logic to force a pred ictable internal state. 31.5.3.7 lockout_recovery instruction if a user inadvertently enables security on a mcu, the lockout_re covery instruction allows the disabling of security by the complete erasure of the internal flash contents including the configuration field. this does not compromise security as the entire contents of th e user?s secured code stored in flash gets erased before security is disabled on the mcu on the next reset or power-up sequence. the lockout_recovery instruction selects a 7-bi t shift register for connection as a shift path between the tdi pin and th e tdo pin. when the user transitions the tap controller to the update-dr state, the 7-bit shift regi ster is loaded into the 7-bit jtag_tfm _clkdiv register and this value is output to the tfm?s clock divider circuit. when the user transitions the ta p controller to the run-test/idle state, the erase signal to the tfm asserts and the lo ckout sequence starts. the controller must remain in that state until the eras e sequence has completed. on ce the lockout recovery se quence has completed, the user must reset both the jtag tap controller and the mcu to return to normal operation. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 ieee 1149.1 test access port (jtag) freescale semiconductor 31-9 31.5.3.8 clamp instruction the clamp instruction selects the bypass register and asserts internal reset whil e simultaneously forcing all output pins and bidirectional pins configured as outputs to the fixed values that are preloaded and held in the boundary scan update register. clamp enhances test efficiency by reducing the overall shift path to a single bit (the bypass register) while conducti ng an extest type of instruction through the boundary scan register. 31.5.3.9 bypass instruction the bypass instruction selects the by pass register, creating a single-bit shift register path from the tdi pin to the tdo pin. bypass enhances test efficiency by reducing the overall shift path when a device other than the coldfire processor is the device under test on a board design with multiple chips on the overall boundary scan chain. the shift register lsb is forced to logic 0 on the rising edge of tclk after entry into the capture-dr state. th erefore, the first bit shifted out af ter selecting the bypass register is always logic 0. this differentiates parts that support an idcode regist er from parts that support only the bypass register. 31.6 initialization/application information 31.6.1 restrictions the test logic is a static logic de sign, and tclk can be stopped in eith er a high or low state without loss of data. however, the system cloc k is not synchronized to tclk in ternally. any mixed operation using both the test logic and the system functi onal logic requires external synchronization. using the extest instruction require s a circuit-board test environmen t that avoids de vice-destructive configurations in which mcu output drivers ar e enabled into actively driven networks. low-power stop mode considerations: ? the tap controller must be in th e test-logic-reset state to either enter or remain in the low-power stop mode. leaving the test-logic-reset state negate s the ability to achieve low-power, but does not otherwise affect de vice functionality. ? the tclk input is not blocke d in low-power stop mode. to c onsume minimal power, the tclk input should be externally connected to v dd . ? the tms, tdi, and trst pins include on-chip pull-up resist ors. for minimal power consumption in low-power stop mode, these three pi ns should be either connected to v dd or left unconnected. 31.6.2 nonscan chain operation keeping the tap controller in the test-logic-reset state en sures that the scan chain test logic is transparent to the system logic. it is recomm ended that tms, tdi, tclk, and trst be pulled up. trst could be connected to ground. however, since there is a pull-up on trst , some amount of current results. the internal power-on reset input initiali zes the tap controller to the test -logic-reset state on power-up without asserting trst . mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 ieee 1149.1 test access port (jtag) 31-10 freescale semiconductor mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor 32-1 chapter 32 mechanical data this chapter contains drawings s howing the pinout and the packaging and mechanical characteristics of the mcf528 x and mcf521 x . 32.1 pinout figure 32-1 is the pinout for the mcf5280, mcf5281, and mcf5282 . the shaded cells illustrate the differences between the mcf5214 and mcf5216 pinout. note on the mcf5280 device, which does not contain any flash memory, the vssf and vddf pins must be conne cted to vss and vdd respectively. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 mechanical data 32-2 freescale semiconductor figure 32-1. mcf528 x pinout (256 mapbga) 123456 7 8 910111213 14 1516 a vss a15 a16 a18 a21 vpp etxd3 etxclk erxd3 erxclk ecrs vddf ddata1 pst2 pst0 vss b a14 a13 a17 a19 vssf a22 etxd2 erxer erxd2 emdc ecol vssf ddata0 pst1 irq7 irq6 c a12 a11 a10 a20 vddf a23 etxd1 erxdv erxd1 emdio vpp ddata3 pst3 irq5 irq4 irq3 d a9 a8 a7 a6 vddf etxen etxd0 nc erxd0 etxer vddf ddata2 nc irq2 irq1 canrx e a5 a4 a3 a2 vss vdd vdd vdd vdd vdd vdd vss cantx sda scl qspi_ din f a1 a0 d31 nc vdd vss vdd vdd vdd vdd vss vdd qspi_ dout qspi_ clk qspi_ cs0 qspi_ cs1 g d30 d29 d28 d27 vdd vdd vss vss vss vss vdd vdd qspi_ cs2 qspi_ cs3 dramw sdram_ cs0 h d26 d25 d24 d23 vdd vdd vss vss vss vss vdd vdd sdra_ cs1 scke sras scas j d22 d21 d20 d19 vdd vdd vss vss vss vss vdd vdd dtout0 dtin0 dtout1 dtin1 k d18 d17 d16 nc vdd vdd vss vss vss vss vdd vdd dtout2 dtin2 dtout3 dtin3 l d15 d14 d13 d12 vdd vss vdd vdd vdd vdd vss vdd cs0 cs1 cs2 cs3 m d11 d10 d9 d8 vss vdd vdd vdd vdd vdd vdd vss nc tip ts siz0 n d7 d6 d5 nc d3 urxd0 clkout vddpll nc test vstby gptb0 gpta0 siz1 r/w oe p d4 vddh an55 vrh vssa d0 utxd1 vsspll dsclk bkpt rsto gptb1 gpta1 bs3 tea ta r an3 an1 an56 an52 vdda d1 urxd1 xtal jtag_ en dsi rsti gptb2 gpta2 clkmod0 bs1 bs0 t vssa an2 an0 an53 vrl d2 utxd0 extal tclk dso rcon gptb3 gpta3 clkmod1 bs2 vss mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 mechanical data freescale semiconductor 32-3 figure 32-2 is the pinout for the mcf5214 and mcf5216. the shaded cells illustrate the differences between the mcf5280, mcf5281, and mcf5282 pinout. figure 32-2. mcf521 x pinout (256 mapbga) 123456 7 8 910111213 14 1516 a vss a15 a16 a18 a21 vpp pel7 pel0 pel3 pa s 4 nc vddf ddata1 pst2 pst0 vss b a14 a13 a17 a19 vssf a22 pel6 nc pel2 nc nc vssf ddata0 pst1 irq7 irq6 c a12 a11 a10 a20 vddf a23 pel5 nc pel1 pas5 vpp ddata3 pst3 irq5 irq4 irq3 d a9 a8 a7 a6 vddf nc nc nc nc pel4 vddf ddata2 nc irq2 irq1 canrx e a5 a4 a3 a2 vss vdd vdd vdd vdd vdd vdd vss cantx sda scl qspi_ din f a1 a0 d31 nc vdd vss vdd vdd vdd vdd vss vdd qspi_ dout qspi_ clk qspi_ cs0 qspi_ cs1 g d30 d29 d28 d27 vdd vdd vss vss vss vss vdd vdd qspi_ cs2 qspi_ cs3 dramw sdram_ cs0 h d26 d25 d24 d23 vdd vdd vss vss vss vss vdd vdd sdra_ cs1 scke sras scas j d22 d21 d20 d19 vdd vdd vss vss vss vss vdd vdd dtout0 dtin0 dtout1 dtin1 k d18 d17 d16 nc vdd vdd vss vss vss vss vdd vdd dtout2 dtin2 dtout3 dtin3 l d15 d14 d13 d12 vdd vss vdd vdd vdd vdd vss vdd cs0 cs1 cs2 cs3 m d11 d10 d9 d8 vss vdd vdd vdd vdd vdd vdd vss nc tip ts siz0 n d7 d6 d5 nc d3 urxd0 clkout vddpll nc test vstby gptb0 gpta0 siz1 r/w oe p d4 vddh an55 vrh vssa d0 utxd1 vsspll dsclk bkpt rsto gptb1 gpta1 bs3 tea ta r an3 an1 an56 an52 vdda d1 urxd1 xtal jtag_ en dsi rsti gptb2 gpta2 clkmod0 bs1 bs0 t vssa an2 an0 an53 vrl d2 utxd0 extal tclk dso rcon gptb3 gpta3 clkmod1 bs2 vss mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 mechanical data 32-4 freescale semiconductor table 32-1 lists the mcf521 x and mcf528x signals in pin number orde r for the 256 mapbga package. the shaded cells illustrate the difference signals between the two device families. table 32-1. signal description by pin number mapbga pin pin functions mapbga pin pin functions primary secondary tertiary primary secondary tertiary a1 vss ? ? j1 d22 pb6 ? a2 a15 pg7 ? j2 d21 pb5 ? a3 a16 pf0 ? j3 d20 pb4 ? a4 a18 pf2 ? j4 d19 pb3 ? a5 a21 pf5 cs4 j5 vdd ? ? a6 vpp ? ? j6 vdd ? ? a7 (mcf521 x) pel7 ? ? j7 vss ? ? a7 (mcf528 x) etxclk peh7 ? a8 (mcf521 x) pel0 ? ? j8 vss ? ? a8 (mcf528 x) etxclk peh7 ? a9 (mcf521 x) pel3 ? ? j9 vss ? ? a9 (mcf528 x) erxd3 pel3 ? a10 (mcf521 x) pas4 utxd2 ? j10 vss ? ? a10 (mcf528 x) erxclk peh3 utxd2 a11 (mcf521 x) nc 1 ? ?j 1 1v d d? ? a11 (mcf528 x) ecrs peh0 ? a12 vddf ? ? j12 vdd ? ? a13 ddata1 pdd5 ? j13 dtout0 ptd0 ucts1 / ucts0 a14 pst2 pdd2 ? j14 dtin0 ptd1 ucts1 /ucts0 a15 pst0 pdd0 ? j15 dtout1 ptd2 urts1 /urts0 a16 vss ? ? j16 dtin1 ptd3 urts1 /urts0 b1 a14 pg6 ? k1 d18 pb2 ? b2 a13 pg5 ? k2 d17 pb1 ? b3 a17 pf1 ? k3 d16 pb0 ? b4 a19 pf3 ? k4 nc ? ? b5 vssf ? ? k5 vdd ? ? b6 a22 pf6 cs5 k6 vdd ? ? b7 (mcf521 x) pel6 ? ? k7 vss ? ? b7 (mcf528 x) etxd2 pel6 ? mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 mechanical data freescale semiconductor 32-5 b8 (mcf521 x) nc ? ? k8 vss ? ? b8 (mcf528 x) erxer pel0 ? b9 (mcf521 x) pel2 ? ? k9 vss ? ? b9 (mcf528 x) erxd2 pel2 ? b10 (mcf521 x) nc ? ? k10 vss ? ? b10 (mcf528 x) emdc pas4 utxd2 b11 (mcf521 x) nc ? ?k 1 1v d d? ? b11 (mcf528 x) ecol peh4 ? b12 vssf ? ? k12 vdd ? ? b13 ddata0 pdd4 ? k13 dtout2 ptc0 ucts1 /ucts0 b14 pst1 pdd1 ? k14 dtin2 ptc1 ucts1 /ucts0 b15 irq7 pnq7 ? k15 dtout3 ptc2 urts1 /urts0 b16 irq6 pnq6 ? k16 dtin3 ptc3 urts1 /urts0 c1 a12 pg4 ? l1 d15 pc7 ? c2 a11 pg3 ? l2 d14 pc6 ? c3 a10 pg2 ? l3 d13 pc5 ? c4 a20 pf4 ? l4 d12 pc4 ? c5 vddf ? ? l5 vdd ? ? c6 a23 pf7 cs6 l6 vss ? ? c7 (mcf521 x ) pel5 ?l 7v d d? ? c7 (mcf528 x ) etxd1 pel5 ? c8 (mcf521 x ) nc ?l 8v d d? ? c8 (mcf528 x ) erxdv peh2 ? c9 (mcf521 x ) pel1 ?l 9v d d? ? c9 (mcf528 x ) erxd1 pel1 ? c10 (mcf521 x) pas5 urxd2 l10 vdd ? ? c10 (mcf528 x) emdio pas5 urxd2 c11 vpp ? ? l11 vss ? ? c12 ddata3 pdd7 ? l12 vdd ? ? c13 pst3 pdd3 ? l13 cs0 pj0 ? c14 irq5 pnq5 ? l14 cs1 pj1 ? c15 irq4 pnq4 ? l15 cs2 pj2 ? table 32-1. signal description by pin number (continued) mapbga pin pin functions mapbga pin pin functions primary secondary tertiary primary secondary tertiary mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 mechanical data 32-6 freescale semiconductor c16 irq3 pnq3 ? l16 cs3 pj3 ? d1 a9 pg1 ? m1 d11 pc3 ? d2 a8 pg0 ? m2 d10 pc2 ? d3 a7 ph7 ? m3 d9 pc1 ? d4 a6 ph6 ? m4 d8 pc0 ? d5 vddf ? ? m5 vss ? ? d6 (mcf521 x ) nc ? ?m 6v d d? ? d6 (mcf528 x ) etxen peh6 ? d7 (mcf521 x ) nc ? ?m 7v d d? ? d7 (mcf528 x ) etxd0 peh5 ? d8 nc ? ? m8 vdd ? ? d9 (mcf521 x ) nc ? ?m 9v d d? ? d9 (mcf528 x ) erxd0 peh1 ? d10 (mcf521 x) pel4 ? ?m 1 0v d d? ? d10 (mcf528 x) etxer pel4 ? d11 vddf ? ? m11 vdd ? ? d12 ddata2 pdd6 ? m12 vss ? ? d13 nc ? ? m13 nc ? ? d14 irq2 pnq2 ? m14 tip pe0 syncb d15 irq1 pnq1 ? m15 ts pe1 synca d16 canrx pas3 urxd2 m16 siz0 pe2 syncb e1 a5 ph5 ? n1 d7 pd7 ? e2 a4 ph4 ? n2 d6 pd6 ? e3 a3 ph3 ? n3 d5 pd5 ? e4 a2 ph2 ? n4 nc ? ? e5 vss ? ? n5 d3 pd3 ? e6 vdd ? ? n6 urxd0 pua1 ? e7 vdd ? ? n7 clkout ? ? e8 vdd ? ? n8 vddpll ? ? e9 vdd ? ? n9 nc ? ? e10 vdd ? ? n10 test ? ? e11 vdd ? ? n11 vstby ? ? table 32-1. signal description by pin number (continued) mapbga pin pin functions mapbga pin pin functions primary secondary tertiary primary secondary tertiary mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 mechanical data freescale semiconductor 32-7 e12 vss ? ? n12 gptb0 ptb0 ? e13 cantx pas2 utxd2 n13 gpta0 pta0 ? e14 sda pas1 urxd2 n14 siz1 pe3 synca e15 scl pas0 utxd2 n15 r/w pe4 ? e16 qspi_din pqs1 ? n16 oe pe7 ? f1 a1 ph1 ? p1 d4 pd4 ? f2 a0 ph0 ? p2 vddh ? ? f3 d31 pa7 ? p3 an55 pqa3 etrig1 f4 nc ? ? p4 vrh ? ? f5 vdd ? ? p5 vssa ? ? f6 vss ? ? p6 d0 pd0 ? f7 vdd ? ? p7 utxd1 pua2 ? f8 vdd ? ? p8 vsspll ? ? f9 vdd ? ? p9 dsclk trst ? f10 vdd ? ? p10 bkpt tms ? f11 vss ? ? p11 rsto ?? f12 vdd ? ? p12 gptb1 ptb1 ? f13 qspi_dout pqs0 ? p13 gpta1 pta1 ? f14 qspi_clk pqs2 ? p14 bs3 pj7 ? f15 qspi_cs0 pqs3 ? p15 tea pe5 ? f16 qspi_cs1 pqs4 ? p16 ta pe6 ? g1 d30 pa6 ? r1 an3 pqb3 anz g2 d29 pa5 ? r2 an1 pqb1 anx g3 d28 pa4 ? r3 an56 pqa4 etrig2 g4 d27 pa3 ? r4 an52 pqa0 ma0 g5 vdd ? ? r5 vdda ? ? g6 vdd ? ? r6 d1 pd1 ? g7 vss ? ? r7 urxd1 pua3 ? g8 vss ? ? r8 xtal ? ? g9 vss ? ? r9 jtag_en ? ? g10 vss ? ? r10 dsi tdi ? g11 vdd ? ? r11 rsti ?? table 32-1. signal description by pin number (continued) mapbga pin pin functions mapbga pin pin functions primary secondary tertiary primary secondary tertiary mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 mechanical data 32-8 freescale semiconductor g12 vdd ? ? r12 gptb2 ptb2 ? g13 qspi_cs2 pqs5 ? r13 gpta2 pta2 ? g14 qspi_cs3 pqs6 ? r14 clkmod0 ? ? g15 dramw psd3 ? r15 bs1 pj5 ? g16 sdram_cs0 psd1 ? r16 bs0 pj4 ? h1 d26 pa2 ? t1 vssa ? ? h2 d25 pa1 ? t2 an2 pqb2 any h3 d24 pa0 ? t3 an0 pqb0 anw h4 d23 pb7 ? t4 an53 pqa1 ma1 h5 vdd ? ? t5 vrl ? ? h6 vdd ? ? t6 d2 pd2 ? h7 vss ? ? t7 utxd0 pua0 ? h8 vss ? ? t8 extal ? ? h9 vss ? ? t9 tclk ? ? h10 vss ? ? t10 dso tdo ? h11 vdd ? ? t11 rcon ?? h12 vdd ? ? t12 gptb3 ptb3 ? h13 sdram_cs1 psd2 ? t13 gpta3 pta3 ? h14 scke psd0 ? t14 clkmod1 ? ? h15 sras psd5 ? t15 bs2 pj6 ? h16 scas psd4 ? t16 vss ? ? 1 nc = no connect table 32-1. signal description by pin number (continued) mapbga pin pin functions mapbga pin pin functions primary secondary tertiary primary secondary tertiary mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 mechanical data freescale semiconductor 32-9 figure 32-3. 256 mapbga package dimensions 32.2 ordering information table 32-2. orderable part numbers freescale part number description package speed temperature mcf5214cvf66 mcf5214 risc microprocessor 256 mapbga 66.67 mhz -40 to +85 c mcf5216cvf66 mcf5216 risc microprocessor 256 mapbga 66.67 mhz -40 to +85 c mcf5280cvf66 mcf5280 risc microprocessor 256 mapbga 66.67 mhz -40 to +85 c mcf5280cvf80 mcf5280 risc microprocessor 256 mapbga 80 mhz -40 to +85 c mcf5281cvf66 mcf5281 risc microprocessor 256 mapbga 66.67 mhz -40 to +85 c mcf5281cvf80 mcf5281 risc microprocessor 256 mapbga 80 mhz -40 to +85 c mcf5282cvf66 mcf5282 risc microprocessor 256 mapbga 66.67 mhz -40 to +85 c mcf5282cvf80 mcf5282 risc microprocessor 256 mapbga 80 mhz -40 to +85 c notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimension b is measured at the maximum solder ball diameter, parallel to datum plane z. 4. datum z (seating plane) is defined by the spherical crowns of the solder balls. 5. parallelism measurement shall exclude any effect of mark on top surface of package. x y d e laser mark for pin a1 identification in this area 0.20 metalized mark for pin a1 identification in this area m m 3 a b c d e f g h j k l m n p r t 123456710 11 1213141516 e 15x e 15x b 256x m 0.25 y z m 0.10 x z s detail k view m-m rotated 90 clockwise s a z z a2 a1 4 0.15 z 0.30 256x 5 k dim min max millimeters a 1.25 1.60 a1 0.27 0.47 a2 1.16 ref b 0.40 0.60 d 17.00 bsc e 17.00 bsc e 1.00 bsc s 0.50 bsc mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 mechanical data 32-10 freescale semiconductor mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor 33-1 chapter 33 electrical characteristics this chapter contains electrical specification tables and referenc e timing diagrams for the mcf528 x and mcf521x microcontroller units. this s ection contains detailed inform ation on power considerations, dc/ac electrical char acteristics, and ac timing specifications. note the parameters specified in this mcu document supersede any values found in the module specifications. 33.1 maximum ratings table 33-1. absolute maximum ratings 1, 2 1 functional operating conditions are given in dc electrical specifications. absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond those listed may affect device reliability or cause permanent damage to the device. rating symbol value unit supply voltage v dd ? 0.3 to +4.0 v clock synthesizer supply voltage v ddpll ? 0.3 to +4.0 v ram memory standby supply voltage v stby ? 0.3 to + 4.0 v flash memory supply voltage 3 v ddf ? 0.3 to +4.0 v flash memory program / erase supply voltage 3 v pp ? 0.3 to + 6.0 v analog supply voltage v dda ? 0.3 to +6.0 v analog reference supply voltage v rh ? 0.3 to +6.0 v analog esd protection voltage v ddh ? 0.3 to +6.0 v digital input voltage 4 v in ? 0.3 to + 6.0 v analog input voltage v ain ? 0.3 to + 6.0 v extal pin voltage v extal 0 to 3.3 v xtal pin voltage v xtal 0 to 3.3 v instantaneous maximum current single pin limit (applies to all pins) 3, 5, 6 i d 25 ma maximum power supply current 6 i dd 300 ma operating temperatur e range (packaged) t a ? 40 to 85 c storage temperature range t stg ? 65 to 150 c maximum operating junction temperature t j 105 o c esd target for human body model 7 hbm 2000 v mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 electrical characteristics 33-2 freescale semiconductor 33.2 thermal characteristics table 33-2 lists thermal resistance values. 2 this device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal prec autions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either v ss or v dd ). 3 not applicable for mcf5280. 4 input must be current limited to the value spec ified. to determine the value of the required current-limiting resistor, calculate resistance va lues for positive and negative clamp voltages, then use the larger of the two values. 6.0v voltage excludes xtal and extal pads. 5 all functional non-supply pins are internally clamped to v ss and v dd . 6 power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if positive injection current (v in > v dd ) is greater than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. insure external v dd load will shunt current greater than maximum injection current. this will be the greatest risk when the mcu is not consuming power (ex; no clock).power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. 7 all esd testing methodology is in conformity with cdf-aec-q100 stress test qualification for automotive grade integrated circuits. note it is crucial during power-up that v dd never exceeds v ddh by more than 0.3 v. there are diode devices between the two voltage domains, and violating this rule can lead to a latch-up condition. table 33-2. thermal characteristics characteristic symbol value unit junction to ambient, natural convection four layer board (2s2p) jma 26 1,2 1 jma and jt parameters are simulated in accordance with ei a/jesd standard 51-2 for natural convection. freescale recommends the use of ja and power dissipation specifications in the system design to prevent device junction temperatures from exceeding the rated specif ication. system designers should be aware that device junction temperatures can be significantly influenced by board layout and surrounding devices. conformance to the device junction temperature specificat ion can be verified by physical measur ement in the customer?s system using the jt parameter, the device power dissipation, and the method described in eia/jesd standard 51-2. 2 per jedec jesd51-6 with the board horizontal. c/w junction to ambient (@200 ft/min) four layer board (2s2p) jma 23 1,2 c/w junction to board jb 15 3 3 thermal resistance between the die and the printed ci rcuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. c/w junction to case jc 10 4 4 thermal resistance between the die and the case top su rface as measured by the cold plate method (mil spec-883 method 1012.1). c/w junction to top of package natural convection jt 2 1,5 c/w mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 electrical characteristics freescale semiconductor 33-3 33.3 dc electrical specifications 5 thermal characterization parameter indi cating the temperature difference between package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characterization parameter is written as psi-jt. the average chip-junction temperature (t j ) in c can be obtained from: (1) where: t a = ambient temperature, c q jma = package thermal resistance, junction-to-ambient, c/w p d = p int + p i/o p int = i dd v dd , watts - chip internal power p i/o = power dissipation on input and output pins ? user determined for most applications p i/o < p int and can be neglected. an approximate relationship between p d and t j (if p i/o is neglected) is: (2) solving equations 1 and 2 for k gives: k = p d (t a + 273 c) + q jma p d 2 (3) where k is a constant pertaining to the partic ular part. k can be de termined from equation (3) by measuring p d (at equilibrium) for a known t a . using this value of k, the values of p d and t j can be obtained by solving equations (1 ) and (2) iteratively for any value of t a . table 33-3. dc electrical specifications 1 (v ss = v sspll = v ssf = v ssa = 0 v dc ) characteristic symbol min max unit input high voltage v ih 0.7 x v dd 5.25 v input low voltage v il v ss ? 0.3 0.35 x v dd v input hysteresis v hys 0.06 x v dd ?mv input leakage current v in = v dd or v ss , input-only pins i in -1.0 1.0 a high impedance (off-state) leakage current v in = v dd or v ss , all input/output and output pins i oz -1.0 1.0 a output high voltage (all input/output and all output pins) i oh = ?5.0 ma v oh v dd - 0.5 __ v output low voltage (all inpu t/output and all output pins) i ol = 5.0ma v ol __ 0.5 v weak internal pull up de vice current, tested at v il max. i apu -10 -130 a input capacitance 2 all input-only pins all input/output (three-state) pins c in ? ? 7 7 pf t j t a p d jma () += p d kt j 273 c+ () = mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 electrical characteristics 33-4 freescale semiconductor 33.4 power consumption specifications figure 33-1 shows typical wait/doze and run mode pow er consumption for bot h master and single chip mode as meas ured on an m5282evb. for master mode the run mode current was measur ed executing a continuous loop that performs no operation while running from the on-chip sram. for wait/doze mode measurements the peripherals on the device ar e in their default power savings mode, so the wait and doze power consumption are the same. some modules can be programmed to shutdown in wait and/or doze modes. refer to module chapters for more information. all single chip mode measur ements were taken with all pins in general purpose input mode except for the uart0 and fec pins that are enab led for their module f unctionality; however, neither module is being accessed at the time of the current measurement. si ngle chip run mode current was measured executing a continuous loop that performs no operat ion while running from the on-chip flash. load capacitance 3 (50% partial drive) (100% full drive) c l 25 50 pf supply voltage (includes core modules and pads) v dd 2.7 3.6 v ram memory standby supply voltage normal operation: v dd > v stby - 0.3 v standby mode: v dd < v stby - 0.3 v v stby 0.0 1.8 3.6 3.6 v flash memory supply voltage (not applicable to mcf5280) v ddf 2.7 3.6 v 1 refer to table 33-8 through table 33-12 for additional pll, qadc, and flash specifications. 2 this parameter is characterized before qualification rather than 100% tested. 3 refer to the chip configuration section for more information. drivers for the sdram pins are at 25pf drive strength.drivers fo r the qadc pins are at 50pf drive strength. table 33-4. stop mode current consumption specifications characteristic symbol typical? master mode typical? single chip mode 1 1 single chip mode current measured with all pins in general purpos e input mode except for the uart0 and fec pins that are enable d for their module functionality. max 2 2 maximum values can vary depending on the system?s state and signal loading. unit system clocks disabled (lpcr[stpmd] = 00) i dd 25 7.9 ? ma system clocks and clkout disabled (lpcr[stpmd] = 01) i dd 7.3 5.6 ? ma system clocks, clkout, and pll disabled (lpcr[stpmd] = 10) i dd 4.5 4.7 ? ma system clocks, clkout, pll, and osc disabled (lpcr[stpmd] = 11) i dd 400 750 1000 a table 33-3. dc electrical specifications 1 (continued) (v ss = v sspll = v ssf = v ssa = 0 v dc ) characteristic symbol min max unit mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 electrical characteristics freescale semiconductor 33-5 figure 33-1. typical wait/doze mode current consumption table 33-5 lists the estimated power cons umption for individual modules. the current consumption is for the module itself and does not include power for i/o. table 33-5. estimated module power consumption module estimated power unit eim 20 a/mhz sdramc 30 a/mhz fec 60 a/mhz watchdog 1.5 a/mhz pit 1 a/mhz flexcan 15 a/mhz qspi, uart, i 2 c, and timers 75 a/mhz 0 50 100 150 200 250 8 162432404856647280 frequency (mhz) idd (ma) master mode - run master mode - wait single chip - run single chip - wait mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 electrical characteristics 33-6 freescale semiconductor table 33-7 lists the maximum power consumption specifications. table 33-6. typical application power consumption application current dhrystone benchmark running from cache and on-chip sram (running at 64 mhz f sys ) 181.6 ma dbug rom monitor running from external flash and sdram (running at 64 mhz f sys ) 155 ma table 33-7. maximum power consumption specifications characteristic symbol typical max unit operating supply current 1 master mode ? 66 mhz ? 80 mhz (mcf528 x only) single chip mode wait/doze ? 66 mhz ? 80 mhz (mcf528 x only) 1 current measured at maximum system clock fr equency, all modules active, and default drive strength with matching load. i dd ? ? ? ? ? ? 200 240 150 125 150 ma ma ma ma ma clock synthesizer supply current normal operation 8.25 mhz crystal, vco on, max f sys stop (osc and pll enabled) stop (osc enable, pll disabled) stop (osc and pll disabled) i ddpll ? ? ? ? 4 2 1 10 ma ma ma a ram memory standby supply current normal operation: v dd > v stby - 0.3 v transient condition: v stby - 0.3 v > v dd > v ss + 0.5 v standby operation: v dd < v ss + 0.5 v i stby ? ? ? 10 7 20 a ma a flash memory supply current read program or erase 2 idle stop 2 programming and erasing all 8 blocks of the flash. i ddf 16.5 3 25 4 1.6 4 0.2 3 measured with f sys of 64 mhz. 4 measured with f sys of 32 mhz and f clk of 187.5 khz. 30 64 20 10 ma ma ma a analog supply current normal operation low-power stop i dda ? ? 5.0 10.0 ma a mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 electrical characteristics freescale semiconductor 33-7 33.5 phase lock loop electrical specifications table 33-8. pll electrical specifications (v dd and v ddpll = 2.7 to 3.6 v, v ss = v sspll = 0 v) characteristic symbol min max unit 66mhz 80mhz pll reference frequency range crystal reference external reference 1:1 mode f ref_crystal f ref_ext f ref_1:1 2 2 33.33 8.33 8.33 66.66 10.0 10.0 80 mhz system frequency 1 external clock mode on-chip pll frequency 1 all internal registers retain data at 0 hz. f sys 0 f ref / 32 f sys(max) 66.66 66.66 f sys(max) 80 80 mhz loss of reference frequency 2, 4 2 ?loss of reference frequency? is the reference frequency det ected internally, which transitions the pll into self clocked mode. f lor 100 1000 khz self clocked mode frequency 3, 4 3 self clocked mode frequency is the frequency that the pl l operates at when the reference frequency falls below f lor with default mfd/rfd settings. f scm 15m h z crystal start-up time 4, 5 4 this parameter is characterized before qualification rather than 100% tested. 5 proper pc board layout procedures must be followed to achieve specifications. t cst ?1 0m s extal input high voltage crystal mode all other modes (1:1, bypass, external) v ihext v xtal + 0.4 2.0 v dd v dd v extal input low voltage crystal mode all other modes (1:1, bypass, external) v ilext v ss v ss v xtal - 0.4 0.8 v xtal output high voltage i oh = 1.0 ma v ol v dd - 1.0 ? v xtal output low voltage i ol = 1.0 ma v ol ?0 . 5 v xtal load capacitance 6 ??p f pll lock time 4,7 t lpll ? 500 s power-up to lock time 4, 5,8 with crystal reference without crystal reference t lplk ? ? 10.5 500 ms s 1:1 clock skew (between clkout and extal) 9 t skew -2 2 ns duty cycle of reference 4 t dc 40 60 % f sys frequency un-lock range f ul - 1.5 1.5 % f sys frequency lock range flck - 0.75 0.75 % % f sys clkout period jitter 4, 5, 7, 10,11 , measured at f sys max peak-to-peak (clock edge to clock edge) ? mcf521 x peak-to-peak (clock edge to clock edge) ? mcf528 x long term jitter (averaged over 2 ms interval) c jitter ? ? ? 5 10 .01 % f sys mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 electrical characteristics 33-8 freescale semiconductor 33.6 qadc electrical characteristics 6 load capacitance determined from crystal manufacturer specifications and will include circuit board parasitics. 7 this specification applies to the period r equired for the pll to relock after changing the mfd frequency control bits in the synthesizer control register (syncr). 8 assuming a reference is available at power up, lock time is measured from the time v dd and v ddpll are valid to rsto negating. if the crystal oscillator is being used as th e reference for the pll, then the crystal start up time must be added to the pll lock time to determine the total start-up time. 9 pll is operating in 1:1 pll mode. 10 jitter is the average deviation from t he programmed frequency measured over the specified interval at maximum f sys . measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. noise injected into the pll circuitry via v ddpll and v sspll and variation in crystal oscillator frequency increase the cjitter percentage for a given interval 11 based on slow system clock of 40 mhz measured at f sys max. table 33-9. qadc absolute maximum ratings parameter symbol min max unit analog supply, with reference to v ssa v dda ?0.3 6.0 v internal digital supply 1 , with reference to v ss 1 for internal digital supply of v dd = 3.3v typical. v dd ?0.3 4.0 v reference supply, with reference to v rl v rh ?0.3 6.0 v v ss differential voltage v ss ? v ssa ?0.1 0.1 v v dd differential voltage 2 2 refers to allowed random sequencing of power supplies. v dd ? v dda ?6.0 4.0 v v ref differential voltage v rh ? v rl ?0.3 6.0 v v rh to v dda differential voltage 3 3 refers to allowed random sequencing of power supplies. v rh ? v dda ?6.0 6.0 v v rl to v ssa differential voltage v rl ? v ssa ?0.3 0.3 v v ddh to v dda differential voltage v ddh ? v dda ?1.0 1.0 v maximum input current 4, 5, 6 4 transitions within the limit do not affect device reliab ility or cause permanent dam age. exceeding limit may cause permanent conversion error on stressed channels and on unstressed channels. 5 input must be current limited to the value specified. to de termine the value of the requ ired current-limiting resistor, calculate resistance values using v posclamp = v dda + 0.3v and v negclamp = ?0.3 v, then use the larger of the calculated values. 6 condition applies to one pin at a time. i ma ?25 25 ma mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 electrical characteristics freescale semiconductor 33-9 table 33-10. qadc electrical specifications (operating) 1 (v ddh and v dda = 5.0 v dc 0.5v, v dd = 2.7-3.6v, v ss and v ssa = 0 v dc , fqclk = 2.0 mhz, ta within operating temperature range) 1 qadc converter specifications are only guaranteed fo r vddh and vdda = 5.0v +/- 0.5v. vddh and vdda may be powered down to 2.7v with only gpio functions supported. parameter symbol min max unit analog supply ? mcf521 x analog supply ? mcf528 x v dda 4.5 3.3 5.5 5.5 v v ss differential voltage v ss ? v ssa -100 100 mv reference voltage low 2 2 to obtain full-scale, full-range results, v ssa v rl v indc v rh v dda v rl v ssa v ssa + 0.1 v reference voltage high 2 v rh v dda ? 0.1 v dda v v ref differential voltage ? mcf521 x v ref differential voltage ? mcf528 x v rh ? v rl 4.5 3.3 5.5 5.5 v input voltage v indc v ssa ?0.3 v dda + 0.3 v input high voltage, pqa and pqb v ih 0.7 (v dda )v dda + 0.3 v input low voltage, pqa and pqb v il v ssa ? 0.3 0.4(v dda )v input hysteresis, pqa, pqb 3 3 parameter applies to the following pins: port a: pqa[4:3]/an[ 56:55]/etrig[2:1], pqa[ 1:0]/an[53:52]/ma[1:0] port b: pqb[3:0] /an[3:0]/an[z:w] v hys 0.5 ? v output high voltage, pqa/pqb 3 i oh = tbd v oh vddh-0.8 ? ? v analog supply current normal operation 4 low-power stop 4 current measured at ma ximum system clock freque ncy with qadc active. i dda ? ? 5.0 10.0 ma a reference supply current, dc reference supply current, transient i ref i ref ? ? 250 2.0 a ma load capacitance, pqa/pqb c l ?5 0p f input current, channel off 5 5 maximum leakage occurs at maximum oper ating temperature. current decreases by approximately one-half for each 8 to 12 c, in the ambient temperature range of 50 to 125 c. i off -200 200 na total input capacitance 6 pqa not sampling pqb not sampling incremental capacitance added during sampling 6 this parameter is characterized before qualification rather than 100% tested. c in ? ? ? 15 10 5 pf mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 electrical characteristics 33-10 freescale semiconductor 33.7 flash memory characteristics the flash memory characteristics are shown in table 33-12 and table 33-13. note the mcf5280 does not contain flash memory. table 33-11. qadc conversion specifications (operating) (v ddh and v dda = 5.0 v dc 0.5v, v dd = 2.7-3.6v , v ss and v ssa = 0 v dc , v rh ? v rl = 5 v dc 0.5v, t a within operating temperature range, f sys = 16 mhz) num parameter symbol min max unit 1 qadc clock (qclk) frequency 1 1 conversion characteristics vary with f qclk rate. reduced conversion accuracy occurs at max f qclk rate. using the qadc pins as gpio functions during conversions may result in degraded results. best qadc conversion accuracy is achieved at a frequency of 2 mhz. f qclk 0.5 2.1 mhz 2 conversion cycles cc 14 28 qclk cycles 3 conversion time f qclk = 2.0 mhz 1 min = ccw/ist =%00 max = ccw/ist =%11 t conv 7.0 14.0 s 4 stop mode recovery time t sr ?1 0 s 5 resolution 2 2 at v rh ? v rl = 5.12 v, one count = 5 mv ?5?mv 6 absolute (total unadjusted) error 3, 4, 5 f qclk = 2.0 mhz 2 , 2 clock input sample time 3 accuracy tested and guaranteed at v rh ? v rl = 5.0v 0.5v 4 current coupling ratio, k, is defined as the ratio of the output current, i out , measured on the pin under test to the injection current, i inj , when both adjacent pins are overstressed with the specified injection current. k = i out /i inj . the input voltage error on the channel under test is calculated as verr = i inj * k * r s . 5 performance expected with production silicon. ae -2 2 counts 7 absolute (total unadjusted) error 3, 4, 5 f qclk = 2.0 mhz 2 , 2 clock input sample time ? -3 3 counts table 33-12. sgfm flash program and erase characteristics (v ddf = 2.7 to 3.6 v) parameter symbol min typ max unit system clock (read only) ? mcf521 x system clock (read only) ? mcf528 x f sys(r) 0 0 ? 66.67 80 mhz system clock (program/erase) 1 ? mcf521 x system clock (program/erase) 1 ? mcf528 x 1 refer to the flash sect ion for more information f sys(p/e) 0.15 ? 66.67 80 mhz mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 electrical characteristics freescale semiconductor 33-11 33.8 external interface timing characteristics table 33-14 lists processor bus input timings. note all processor bus timings are synchronous; that is, input setup/hold and output delay with respect to the ri sing edge of a reference clock. the reference clock is the clkout output. all other timing relationships ca n be derived fro m these values. timings listed in table 33-14 are shown in figure 33-2 . table 33-13. sgfm flash module life characteristics (v ddf = 2.7 to 3.6 v) parameter symbol value unit maximum number of guaranteed program/erase cycles 1 before failure 1 a program/erase cycle is defined as switching the bits from 1 0 1. p/e 10,000 2 2 reprogramming of a flash array block prior to erase is not required. cycles data retention at average operating temperature of 85 c retention 10 years table 33-14. processor bus input timing specifications name characteristic 1 1 timing specifications have been indicated taking into account the full drive strength for the pads. symbol min max unit b0 clkout ? mcf521 x clkout ? mcf528 x t cyc 15.15 12.5 ?ns control inputs b1a control input valid to clkout high 2 2 tea and ta pins are being referred to as control inputs. t cvch 10 ? ns b1b bkpt valid to clkout high 3 3 refer to figure a-19. t bkvch 10 ? ns b2a clkout high to control inputs invalid 2 t chcii 0?ns b2b clkout high to asynchronous control input bkpt invalid 3 t bknch 0?ns data inputs b4 data input (d[31:0]) valid to clkout high t divch 6?ns b5 clkout high to data input (d[31:0]) invalid t chdii 0?ns mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 electrical characteristics 33-12 freescale semiconductor figure 33-2. general input timing requirements 33.9 processor bus output timing specifications table 33-14 lists processor bus output timings. table 33-15. external bus output timing specifications name characteristic symbol min max unit control outputs b6a clkout high to chip selects valid 1 t chcv ?0.5t cyc +10 ns b6b clkout high to byte enables (bs [3:0]) valid 2 t chbv ?0.5t cyc +10 ns b6c clkout high to output enable (oe ) valid 3 t chov ?0.5t cyc +10 ns b7 clkout high to control output (bs [3:0], oe ) invalid t chcoi 0.5t cyc + 2 ? ns b7a clkout high to chip selects invalid t chci 0.5t cyc + 2 ? ns address and attribute outputs invalid invalid clkout(66.67 mhz) t setup t hold input setup and hold 1.5v t rise = 1.5 ns v h = v ih v l = v il 1.5v 1.5v valid t fall = 1.5 ns v h = v ih v l = v il input rise time input fall time * the timings are also valid for inputs sampled on the negative clock edge. inputs clkout b4 b5 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 electrical characteristics freescale semiconductor 33-13 read/write bus timings listed in table 33-15 are shown in figure 33-3 , figure 33-4, and figure 33-5 . b8 clkout high to address (a[23:0]) and control (ts , siz[1:0], tip , r/w) valid t chav ?1 0n s b9 clkout high to address (a[23:0]) and control (ts , siz[1:0], tip , r/w) invalid t chai 2?n s data outputs b11 clkout high to data output (d[31:0]) valid t chdov ?1 0n s b12 clkout high to data output (d[31:0]) invalid t chdoi 2?n s b13 clkout high to data output (d[31:0]) high impedance t chdoz ?6n s 1 cs n transitions after the falling edge of clkout. 2 bs transitions after the falling edge of clkout. 3 oe transitions after the falling edge of clkout. table 33-15. external bus output timing specifications (continued) name characteristic symbol min max unit mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 electrical characteristics 33-14 freescale semiconductor figure 33-3. read/write (internally terminated) timing figure 33-4 shows a bus cycle terminated by ta showing timings listed in table 33-15 . clkout cs n a[23:0] r/w bs [3:0] d[31:0] ta (h) (h) s0 s2 s3 s1 s4 s5 s0 s1 s2 s3 s4 s5 tea (h) b6a b8 b7a b6c b7 b6b b7 b4 b5 b11 b12 b9 b9 b8 b6b b13 oe b0 b7 b9 ts tip b8 b8 b9 b8 b9 siz[1:0] b7a b6a b8 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 electrical characteristics freescale semiconductor 33-15 figure 33-4. read bus cycle terminated by ta figure 33-5 shows a bus cycle terminated by tea ; it displays the timings listed in table 33-15 . clkout cs n a[23:0] oe r/w bs [3:0] ta (h) s0 s2 s3 s1 s4 s5 s0 s1 tea (h) b6a b8 b7a b9 b6c b7 b6b b7 b2a b1a d[31:0] b4 b5 b8 b9 ts b9 tip b8 siz[1:0] mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 electrical characteristics 33-16 freescale semiconductor figure 33-5. read bus cycle terminated by tea figure 33-6 shows an sdram read cycle. clkout cs n a[23:0] oe r/w bs [3:0] tea (h) s0 s2 s3 s1 s4 s5 s0 s1 ta (h) b6a b8 b7a b9 b6c b7 b6b b7 b2a b1a d[31:0] b8 b9 ts b9 tip b8 siz[1:0] mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 electrical characteristics freescale semiconductor 33-17 figure 33-6. sdram read cycle table 33-16. sdram timing num characteristic 1 1 all timing specifications are based on taking into account, a 25pf load on the sdram output pins. symbol min max unit d1 clkout high to sdram address valid t chdav ?10ns d2 clkout high to sdram control valid t chdcv ?10ns d3 clkout high to sdram address invalid t chdai 2?ns d4 clkout high to sdram control invalid t chdci 2?ns d5 sdram data valid to clkout high t ddvch 6?ns d6 clkout high to sdram data invalid t chddi 1?ns d7 2 2 d7 and d8 are for write cycles only. clkout high to sdram data valid t chddvw ?10ns d8 2 clkout high to sdram data invalid t chddiw 2?ns a[23:0] sras d[31:0] actv nop sdram_cs [1:0] read column clkout 0 dramw bs [3:0] 1 2 3 4 5 6 7 8 9 10 11 12 13 d1 d2 d4 d6 d5 d4 1 dacr[casl] = 2 scas 1 nop d4 row d3 pre mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 electrical characteristics 33-18 freescale semiconductor figure 33-7 shows an sdram write cycle. figure 33-7. sdram write cycle 33.10 general purpose i/o timing table 33-17. gpio timing 1, 2 (v dd = 2.7 to 3.6 v, v ss = 0 v, v ddh = 5 v) num characteristic symbol min max unit g1 g2 clkout high to gpio output valid t chpov ?1 2n s clkout high to gpio output invalid t chpoi 2?n s g3 g4 gpio input valid to clkout high t pvch 10 ? ns clkout high to gpio input invalid t chpi 2?n s g1a g2a clkout high to pqa/pqb output valid t chpaov ?1 2n s clkout high to pqa/pqb output invalid t chpaoi 2?n s g3a g4a pqa/pqb input vali d to clkout low t pav c h 10 ? ns clkout low to pqa/pqb input invalid t chpai 2?n s a[23:0] sras scas 1 d[31:0] actv pall nop sdram_cs [1:0] write row column clkout dramw bs [3:0] d1 d2 d4 d8 d4 0 1 2 3 4 5 6 7 8 9 10 11 12 d7 nop 1 dacr[casl] = 2 d4 d3 d2 d4 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 electrical characteristics freescale semiconductor 33-19 figure 33-8. gpio timing 33.11 reset and configuration override timing 1 gpio pins include: ports a-i, in t, spi, sci1/2 (including sci functions), flexcan and timer. 2 because of long delays associated with the pqa/pqb pads , signals on the pqa/pqb pins will be updated on the following edge of the clock. table 33-18. reset and configuration override timing (v dd = 2.7 to 3.6 v, v ss = 0 v) 1 1 all ac timing is shown with respect to 50% v dd levels unless otherwise noted. num characteristic symbol min max unit r1 rsti input valid to clkout high t rvch 10 ? ns r2 clkout high to rsti input invalid t chri 2?ns r3 rsti input valid time 2 2 during low-power stop, the synchronizers for the rsti input are bypassed and rsti is asserted asynchronously to the system. thus, rsti must be held a minimum of 100 ns. t rivt 5?t cyc r4 clkout high to rsto valid t chrov ?12ns r5 rsto valid to config. overrides valid t rovcv 0?ns r6 configuration override setup time to rsto invalid t cos 20 ? t cyc r7 configuration override hold time after rsto invalid t coh 0?ns r8 rsto invalid to configuration override high impedance t roicz ?1t cyc g1 clkout gpio outputs g2 pqa/pqb outputs g2a g3a g4a pqa/pqb inputs g3 g4 gpio inputs g1a mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 electrical characteristics 33-20 freescale semiconductor figure 33-9. rsti and configuration override timing 33.12 i 2 c input/output timing specifications table 33-19 lists specifications for the i 2 c input timing parameters shown in figure 33-10 . table 33-20 lists specifications for the i 2 c output timing parameters shown in figure 33-10 . table 33-19. i 2 c input timing specifications between scl and sda num characteristic min max units i1 start condition hold time 2 ? bus clocks i2 clock low period 8 ? bus clocks i3 scl/sda rise time (v il = 0.5 v to v ih = 2.4 v) ? 1 ms i4 data hold time 0 ? ns i5 scl/sda fall time (v ih = 2.4 v to v il = 0.5 v) ? 1 ms i6 clock high time 4 ? bus clocks i7 data setup time 0 ? ns i8 start condition setup time (for repeated start condition only) 2 ? bus clocks i9 stop condition setup time 2 ? bus clocks table 33-20. i 2 c output timing specifications between scl and sda num characteristic min max units i1 1 start condition hold time 6 ? bus clocks i2 1 clock low period 10 ? bus clocks i3 2 scl/sda rise time (v il = 0.5 v to v ih = 2.4 v) ? ? s i4 1 data hold time 7 ? bus clocks i5 3 scl/sda fall time (v ih = 2.4 v to v il = 0.5 v) ? 3 ns i6 1 clock high time 10 ? bus clocks i7 1 data setup time 2 ? bus clocks r1 r2 clkout rsti rsto r3 r4 r8 r7 r6 r5 configuration overrides: r4 (rcon , override pins) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 electrical characteristics freescale semiconductor 33-21 figure 33-10 shows timing for the values in table 33-19 and table 33-20 . figure 33-10. i 2 c input/output timings 33.13 fast ethernet ac timing specifications mii signals use ttl signal levels compatible with devices operating at either 5.0 v or 3.3 v. note the mcf5214 and mcf5216 do not contain an fec module. 33.13.1 mii receive signal timing (erx d[3:0], erxdv, erxer, and erxclk) the receiver functions correctly up to a erxclk maximum freque ncy of 25 mhz +1%. there is no minimum frequency requirement. in addition, the processor clock fre quency must exceed twice the erxclk frequency. table 33-21 lists mii receive channel timings. i8 1 start condition setup time (for repeated start condition only) 20 ? bus clocks i9 1 stop condition setup time 10 ? bus clocks 1 note: output numbers depend on the value programmed into the ifdr; an ifdr programmed with the maximum frequency (ifdr = 0x20) results in minimum output timings as shown in table 33-20 . the i 2 c interface is designed to scale the actual data transition time to move it to the middle of the scl low period. the actual posi tion is affected by the prescale and division values programmed into the ifdr; however, the numbers given in table 33-20 are minimum values. 2 because scl and sda are open-collector-type outp uts, which the processor can only actively drive low, the time scl or sda take to reach a high level depends on external signal capacitance and pull-up resistor values. 3 specified at a nominal 50-pf load. table 33-20. i 2 c output timing specifications between scl and sda (continued) num characteristic min max units i2 i6 i1 i4 i7 i8 i9 i5 i3 scl sda mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 electrical characteristics 33-22 freescale semiconductor figure 33-11 shows mii receive sign al timings listed in table 33-21 . figure 33-11. mii receiv e signal timing diagram 33.13.2 mii transmit signal timing (etxd[3:0], etxen, etxer, etxclk) the transmitter functions correctly up to a etxclk maximum frequency of 25 mhz +1%. in addition, the processor clock frequency must exceed twice the etxclk frequency. table 33-22 lists mii transmit channel timings. figure 33-12 shows mii transmit signal timings listed in table 33-22 . table 33-21. mii receive signal timing num characteristic 1 1 erxdv, erxclk, and erxd[0] have same timing in 10 mbps 7-wire interface mode. min max unit m1 erxd[3:0], erxdv, erxer to erxclk setup 5 ? ns m2 erxclk to erxd[3:0], erxdv, erxer hold 5 ? ns m3 erxclk pulse width high 35% 65% erxclk period m4 erxclk pulse width low 35% 65% erxclk period table 33-22. mii transmit signal timing num characteristic 1 1 etxclk, etxd0, and etxen have the same timing in 10 mbit 7-wire interface mode. min max unit m5 etxclk to etxd[3:0], etxen, etxer invalid 5 ? ns m6 etxclk to etxd[3:0], etxen, etxer valid ? 25 ns m7 etxclk pulse width high 35% 65% etxclk period m8 etxclk pulse width low 35% 65% etxclk period m1 m2 erxclk (input) erxd[3:0] (inputs) erxdv erxer m3 m4 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 electrical characteristics freescale semiconductor 33-23 figure 33-12. mii transmit signal timing diagram 33.13.3 mii async inputs sign al timing (ecrs and ecol) table 33-23 lists mii asynchronous inputs signal timing. figure 33-13 shows mii asynchronous input timings listed in table 33-23 . figure 33-13. mii async inputs timing diagram 33.13.4 mii serial management channel timing (emdio and emdc) the fec functions correctly with a maximum mdc frequency of 2.5 mhz. table 33-24 lists mii serial management channel timings. figure 33-14 shows mii serial management channel timings listed in table 33-24 . table 33-23. mii async inputs signal timing num characteristic min max unit m9 1 1 ecol has the same timing in 10 mbit 7-wire interface mode. ecrs, ecol minimum pulse width 1.5 ? etxclk period table 33-24. mii serial management channel timing num characteristic min max unit m10 emdc falling edge to emdio output invalid (minimum propagation delay) 0? ns m11 emdc falling edge to emdio output valid (max prop delay) ? 25 ns m12 emdio (input) to emdc rising edge setup 10 ? ns m13 emdio (input) to emdc rising edge hold 0 ? ns m14 emdc pulse width high 40% 60% mdc period m15 emdc pulse width low 40% 60% mdc period m6 etxclk (input) etxd[3:0] (outputs) etxen etxer m5 m7 m8 ecrs, ecol m9 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 electrical characteristics 33-24 freescale semiconductor figure 33-14. mii serial management channel timing diagram 33.14 dma timer module ac timing specifications table 33-25 lists timer module ac timings. 33.15 qspi electrical specifications table 33-26 lists qspi timings. the values in table 33-26 correspond to figure 33-15 . table 33-25. timer module ac timing specifications name characteristic 1 1 all timing references to clkout are given to its risi ng edge when bit 3 of the sdram control register is 0. min max unit t1 dtin0 / dtin1 / dtin2 / dtin3 cycle time 3 ? t cyc t2 dtin0 / dtin1 / dtin2 / dtin3 pulse width 1 ? t cyc table 33-26. qspi modules ac timing specifications name characteristic min max unit qs1 qspi_cs[3:0] to qspi_clk 1 tcyc 510 tcyc ns qs2 qspi_clk high to qspi_dout valid. ? 12 ns qs3 qspi_clk high to qspi_dout invalid. (output hold) 2 ? ns qs4 qspi_din to qspi_clk (input setup) 10 ? ns qs5 qspi_din to qspi_clk (input hold) 10 ? ns m11 emdc (output) emdio (output) m12 m13 emdio (input) m10 m14 m15 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 electrical characteristics freescale semiconductor 33-25 figure 33-15. qspi timing 33.16 jtag and boundary scan timing table 33-27. jtag and boundary scan timing num characteristics 1 1 jtag_en is expected to be a static signal. hence, it is not associated with any timing symbol min max unit 1 tclk frequency of operation f jcyc dc 1/4 f sys 2 tclk cycle period t jcyc 4?t cyc 3 tclk clock pulse width t jcw 25.0 ? ns 4 tclk rise and fall times t jcrf 0.0 3.0 ns 5 boundary scan input data se tup time to tclk rise t bsdst 5.0 ? ns 6 boundary scan input data hold time after tclk rise t bsdht 25.0 ? ns 7 tclk low to boundary scan output data valid t bsdv 0.0 30.0 ns 8 tclk low to boundary scan output high z t bsdz 0.0 30.0 ns 9 tms, tdi input data setup time to tclk rise t tapbst 5.0 ? ns 10 tms, tdi input data hold time after tclk rise t tapbht 10.0 ? ns 11 tclk low to tdo data valid t tdodv 0.0 25.0 ns 12 tclk low to tdo high z t tdodz 0.0 8.0 ns 13 trst assert time t trstat 100.0 ? ns 14 trst setup time (negation) to tclk high t trstst 10.0 ? ns qspi_cs[3:0] qspi_clk qspi_dout qs5 qs1 qspi_din qs3 qs4 qs2 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 electrical characteristics 33-26 freescale semiconductor figure 33-16. test clock input timing figure 33-17. boundary scan (jtag) timing figure 33-18. test access port timing tclk v il v ih 33 44 2 (input) input data valid output data valid output data valid tclk data inputs data outputs data outputs data outputs v il v ih 56 7 8 7 input data valid output data valid output data valid tclk tdi tdo tdo tdo tms v il v ih 91 0 11 12 11 bkpt mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 electrical characteristics freescale semiconductor 33-27 figure 33-19. trst timing figure 33-20. bkpt timing 33.17 debug ac timing specifications table 33-28 lists specifications for the debug ac timing parameters shown in figure 33-22 . figure 33-21 shows real-time trace timing for the values in table 33-28 . table 33-28. debug ac timing specification num characteristic min max units d1 pst, ddata to tclk setup 5 ns d2 tclk to pst, ddata hold 2 ns d3 dsi-to-dsclk setup 1 clkout cycles d4 1 1 dsclk and dsi are synchronized internally. d4 is measured from the synchronized dsclk input relative to the rising edge of clkout. dsclk-to-dso hold 4 clkout cycles d5 dsclk cycle time 5 clkout cycles d6 bkpt input data setup time to clkout rise 5.0 ns d7 bkpt input data ho ld time to clkout rise 2.0 ns d8 clkout high to bkpt high z 0.0 10.0 ns tclk trst 14 13 input data valid clkout bkpt (input) v il v ih 15 16 b1b b2b 17 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 electrical characteristics 33-28 freescale semiconductor figure 33-21. real-time trace ac timing figure 33-22 shows bdm serial port ac timing for the values in table 33-28 . figure 33-22. bdm serial port ac timing clkout pst[3:0] d2 d1 ddata[3:0] dsi dso current next clkout past current dsclk d3 d4 d5 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor a-1 appendix a register memory map table a-1 summarizes the address, na me, and byte assignmen t for registers within the cpu space. table a-2 lists an overview of the memory map for the on-chip modules, and table a-3 is a detailed memory map including all of the registers for on-chip modules. table a-1. cpu space register memory map address name mnemonic size cpu @ 0x002 cache control register cacr 32 cpu @ 0x004 access control register 0 acr0 32 cpu @ 0x005 access control register 1 acr1 32 cpu @ 0x800 other stack pointer other_a7 32 cpu @ 0x801 vector base register vbr 32 cpu @ 0x804 mac status register macsr 8 cpu @ 0x805 mac mask register mask 16 cpu @ 0x806 mac accumulator 0 acc0 16 cpu @ 0x807 mac accumulator 0, 1 extension bytes accext01 16 cpu @ 0x808 mac accumulator 2, 3 extension bytes accext23 16 cpu @ 0x809 mac accumulator 1 acc1 16 cpu @ 0x80a mac accumulator 2 acc2 16 cpu @ 0x80b mac accumulator 3 acc3 16 cpu @ 0x80e status register sr 16 cpu @ 0x80f program counter pc 32 cpu @ 0xc04 flash base address register flashbar 32 cpu @ 0xc05 ram base address register rambar 32 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 register memory map a-2 freescale semiconductor table a-2. module memory map overview address module size ipsbar + 0x00_0000 system c ontrol module 64 bytes ipsbar + 0x00_0040 sdram controller 64 bytes ipsbar + 0x00_0080 chip selects 128 bytes ipsbar + 0x00_0100 dma (channel 0) 64 bytes ipsbar + 0x00_0140 dma (channel 1) 64 bytes ipsbar + 0x00_0180 dma (channel 2) 64 bytes ipsbar + 0x00_01c0 dma (channel 3) 64 bytes ipsbar + 0x00_0200 uart0 64 bytes ipsbar + 0x00_0240 uart1 64 bytes ipsbar + 0x00_0280 uart2 64 bytes ipsbar + 0x00_0300 i 2 c6 4 b y t e s ipsbar + 0x00_0340 qspi 64 bytes ipsbar + 0x00_0400 dma timer 0 64 bytes ipsbar + 0x00_0440 dma timer 1 64 bytes ipsbar + 0x00_0480 dma timer 2 64 bytes ipsbar + 0x00_04c0 dma timer 3 64 bytes ipsbar + 0x00_0c00 interrupt controller 0 256 bytes ipsbar + 0x00_0d00 interrupt controller 1 256 bytes ipsbar + 0x00_0f00 global interrupt acknowledge cycles 256 bytes ipsbar + 0x00_1000 fast et hernet controller (registers and mib ram) (reserved for mcf5214 and mcf5216) 1 k ipsbar + 0x00_1400 fast ethernet controller (fifo memory) (reserved for mcf5214 and mcf5216) 1k ipsbar + 0x10_0000 ports 64k ipsbar + 0x11_0000 reset controller, chip configuration, and power management 64k ipsbar + 0x12_0000 clock module 64k ipsbar + 0x13_0000 edge port 64k ipsbar + 0x14_0000 w atchdog timer 64k ipsbar + 0x15_0000 programma ble interval timer 0 64k ipsbar + 0x16_0000 programma ble interval timer 1 64k ipsbar + 0x17_0000 programma ble interval timer 2 64k ipsbar + 0x18_0000 programma ble interval timer 3 64k ipsbar + 0x19_0000 qadc 64k ipsbar + 0x1a_0000 general purpose timer a 64k ipsbar + 0x1b_0000 general purpose timer b 64k mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 register memory map freescale semiconductor a-3 ipsbar + 0x1c_0000 flexcan 64k ipsbar + 0x1d_0000 cfm (flash) control registers 64k ipsbar + 0x400_0000 cfm (flash) memory for ips reads and writes 512k table a-3. register memory map address name mnemonic size scm registers ipsbar + 0x000 internal peripheral sy stem base address register ipsbar 32 ipsbar + 0x008 copy of rambar rambar 32 ipsbar + 0x00c reserved ? ipsbar + 0x010 core reset status register crsr 8 ipsbar + 0x011 core watchdog control register cwcr 8 ipsbar + 0x012 low-power interrupt control register lpicr 8 ipsbar + 0x013 core watchdog service register cwsr 8 ipsbar + 0x014 dma request control register dmareqc 32 ipsbar + 0x01c bus master park register mpark 32 ipsbar + 0x020 master privilege register mpr 32 ipsbar + 0x024 peripheral access control register 0 pacr0 8 ipsbar + 0x025 peripheral access control register 1 pacr1 8 ipsbar + 0x026 peripheral access control register 2 pacr2 8 ipsbar + 0x027 peripheral access control register 3 pacr3 8 ipsbar + 0x028 peripheral access control register 4 pacr4 8 ipsbar + 0x02a peripheral access control register 5 pacr5 8 ipsbar + 0x02b peripheral access control register 6 pacr6 8 ipsbar + 0x02c peripheral access control register 7 pacr7 8 ipsbar + 0x02e peripheral access control register 8 pacr8 8 ipsbar + 0x030 grouped peripheral access control register 0 gpacr0 8 ipsbar + 0x031 grouped peripheral access control register 1 gpacr1 8 sdramc registers ipsbar + 0x040 dram control register dcr 16 ipsbar + 0x048 dram address and control register 0 dacr0 32 ipsbar + 0x04c dram mask register block 0 dmr0 32 ipsbar + 0x050 dram address and control register 1 dacr1 32 table a-2. module memory map overview (continued) address module size mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 register memory map a-4 freescale semiconductor ipsbar + 0x054 dram mask register block 1 dmr1 32 chip select registers ipsbar + 0x080 chip select address register 0 csar0 16 ipsbar + 0x084 chip select mask register 0 csmr0 32 ipsbar + 0x08a chip select control register 0 cscr0 16 ipsbar + 0x08c chip select address register 1 csar1 16 ipsbar + 0x090 chip select mask register 1 csmr1 32 ipsbar + 0x096 chip select control register 1 cscr1 16 ipsbar + 0x098 chip select address register 2 csar2 16 ipsbar + 0x09c chip select mask register 2 csmr2 32 ipsbar + 0x0a2 chip select control register 2 cscr2 16 ipsbar + 0x0a4 chip select address register 2 csar3 16 ipsbar + 0x0a8 chip select mask register 3 csmr3 32 ipsbar + 0x0ae chip select control register 3 cscr3 16 ipsbar + 0x0b0 chip select address register 4 csar4 16 ipsbar + 0x0b4 chip select mask register 4 csmr4 32 ipsbar + 0x0ba chip select control register 4 cscr4 16 ipsbar + 0x0bc chip select address register 5 csar5 16 ipsbar + 0x0c0 chip select mask register 5 csmr5 32 ipsbar + 0x0c6 chip select control register 5 cscr5 16 ipsbar + 0x0c8 chip select address register 6 csar6 16 ipsbar + 0x0cc chip select mask register 6 csmr6 32 ipsbar + 0x0d2 chip select control register 6 cscr6 16 dma registers ipsbar + 0x100 source address register 0 sar0 32 ipsbar + 0x104 destination address register 0 dar0 32 ipsbar + 0x108 dma control register 0 dcr0 32 ipsbar + 0x10c byte count register 0 bcr0 1 32 ipsbar + 0x110 dma status register 0 dsr0 8 ipsbar + 0x140 source address register 1 sar1 32 ipsbar + 0x144 destination address register 1 dar1 32 ipsbar + 0x148 dma control register 1 dcr1 32 table a-3. register memory map (continued) address name mnemonic size mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 register memory map freescale semiconductor a-5 ipsbar + 0x14c byte count register 1 bcr1 1 32 ipsbar + 0x150 dma status register 1 dsr1 8 ipsbar + 0x180 source address register 2 sar2 32 ipsbar + 0x184 destination address register 2 dar2 32 ipsbar + 0x188 dma control register 2 dcr2 32 ipsbar + 0x18c byte count register 2 bcr2 1 32 ipsbar + 0x190 dma status register 2 dsr2 8 ipsbar + 0x1c0 source address register 3 sar3 32 ipsbar + 0x1c4 destination address register 3 dar3 32 ipsbar + 0x1c8 dma control register 3 dcr3 32 ipsbar + 0x1cc byte count register 3 bcr3 1 32 ipsbar + 0x1d0 dma status register 3 dsr3 8 uart registers ipsbar + 0x200 uart mode register 0 2 umr10, umr20 8 ipsbar + 0x204 (read) uart status register 0 usr0 8 (write) uart clock select register 0 1 ucsr0 8 ipsbar + 0x208 (read) reserved 8 (write) uart command register 0 ucr0 8 ipsbar + 0x20c (read) uart receive buffer 0 urb0 8 (write) uart transmit buffer 0 utb0 8 ipsbar + 0x210 (read) uart input port change register 0 uipcr0 8 (write) uart auxiliary control register 0 1 uacr0 8 ipsbar + 0x214 (read) uart interrupt status register 0 uisr0 8 (write) uart interrupt mask register 0 uimr0 8 ipsbar + 0x218 (read) reserved 8 uart baud rate generator register 10 ubg10 8 ipsbar + 0x21c (read) reserved 8 uart baud rate generator register 20 ubg20 8 ipsbar + 0x234 (read) uart input port register 0 uip0 8 (write) reserved 8 table a-3. register memory map (continued) address name mnemonic size mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 register memory map a-6 freescale semiconductor ipsbar + 0x238 (read) reserved 8 (write) uart output port bit set command register 0 uop10 8 ipsbar + 0x23c (read) reserved 8 (write) uart output port bit reset command register 0 uip00 8 ipsbar + 0x240 uart mode registers 1 2 umr11, umr21 8 ipsbar + 0x244 (read) uart status register 1 usr1 8 (write) uart clock select register 1 1 ucsr1 8 ipsbar + 0x248 (read) reserved 8 (write) uart command register 1 ucr1 8 ipsbar + 0x24c (uart/read) uart receive buffer 1 urb1 8 (uart/write) uart transmit buffer 1 utb1 8 ipsbar + 0x250 (read) uart input port change register 1 uipcr1 8 (write) uart auxiliary control register 1 1 uacr1 8 ipsbar + 0x254 (read) uart interrupt status register 1 uisr1 8 (write) uart interrupt mask register 1 uimr1 8 ipsbar + 0x258 (read) reserved 8 uart baud rate generator register 11 ubg11 8 ipsbar + 0x25c (read) reserved 8 uart baud rate generator register 21 ubg21 8 ipsbar + 0x274 (read) uart input port register 1 uip1 8 (write) reserved 8 ipsbar + 0x278 (read) reserved 8 (write) uart output port bit set command register 1 uop11 8 ipsbar + 0x27c (read) reserved 8 (write) uart output port bit reset command register 1 uip01 8 ipsbar + 0x280 uart mode register 2 2 umr12, umr22 8 ipsbar + 0x284 (read) uart status register 2 usr2 8 (write) uart clock select register 2 1 ucsr2 8 table a-3. register memory map (continued) address name mnemonic size mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 register memory map freescale semiconductor a-7 ipsbar + 0x288 (read) reserved 8 (write) uart command register 2 ucr2 8 ipsbar + 0x28c (read) uart receive buffer 2 urb2 8 (write) uart transmit buffer 2 utb2 8 ipsbar + 0x290 (read) uart input port change register 2 uipcr2 8 (write) uart auxiliary control register 2 1 uacr2 8 ipsbar + 0x294 (read) uart interrupt status register 2 uisr2 8 (write) uart interrupt mask register 2 uimr2 8 ipsbar + 0x298 (read) reserved 8 uart baud rate generator register 12 ubg12 8 ipsbar + 0x29c (read) reserved 8 uart baud rate generator register 22 ubg22 8 ipsbar + 0x2b4 (read) uart input port register 2 uip2 8 (write) reserved 8 ipsbar + 0x2b8 (read) reserved 8 (write) uart output port bit set command register 2 uop12 8 ipsbar + 0x2bc (read) reserved 8 (write) uart output port bit reset command register 2 uip02 8 i 2 c registers ipsbar + 0x300 i 2 c address register i2adr 8 ipsbar + 0x304 i 2 c frequency divider register i2fdr 8 ipsbar + 0x308 i 2 c control register i2cr 8 ipsbar + 0x30c i 2 c status register i2sr 8 ipsbar + 0x310 i 2 c data i/o register i2dr 8 qspi registers ipsbar + 0x340 qspi mode register qmr 16 ipsbar + 0x344 qspi delay register qdlyr 16 ipsbar + 0x348 qspi wrap register qwr 16 ipsbar + 0x34c qspi interrupt register qir 16 ipsbar + 0x350 qspi address register qar 16 ipsbar + 0x354 qspi data register qdr 16 table a-3. register memory map (continued) address name mnemonic size mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 register memory map a-8 freescale semiconductor dma timer registers ipsbar + 0x400 dma timer mode register 0 dtmr0 16 ipsbar + 0x402 dma timer exte nded mode register 0 dtxmr0 8 ipsbar + 0x403 dma timer event register 0 dter0 8 ipsbar + 0x404 dma timer reference register 0 dtrr0 32 ipsbar + 0x408 dma timer capture register 0 dtcr0 32 ipsbar + 0x40c dma timer co unter register 0 dtcn0 32 ipsbar + 0x440 dma timer mode register 1 dtmr1 16 ipsbar + 0x442 dma timer exte nded mode register 1 dtxmr1 8 ipsbar + 0x443 dma timer event register 1 dter1 8 ipsbar + 0x444 dma timer reference register 1 dtrr1 32 ipsbar + 0x448 dma timer capture register 1 dtcr1 32 ipsbar + 0x44c dma timer co unter register 1 dtcn1 32 ipsbar + 0x480 dma timer mode register 2 dtmr2 16 ipsbar + 0x482 dma timer exte nded mode register 2 dtxmr2 8 ipsbar + 0x483 dma timer event register 2 dter2 8 ipsbar + 0x484 dma timer reference register 2 dtrr2 32 ipsbar + 0x488 dma timer capture register 2 dtcr2 32 ipsbar + 0x48c dma timer co unter register 2 dtcn2 32 ipsbar + 0x4c0 dma timer mode register 3 dtmr3 16 ipsbar + 0x4c2 dma timer exten ded mode register 3 dtxmr3 8 ipsbar + 0x4c3 dma timer event register 3 dter3 8 ipsbar + 0x4c4 dma timer reference register 3 dtrr3 32 ipsbar + 0x4c8 dma timer capture register 3 dtcr3 32 ipsbar + 0x4cc dma timer counter register 3 dtcn3 32 interrupt controller 0 ipsbar + 0xc00 interrupt pend ing register high 0 iprh0 32 ipsbar + 0xc04 interrupt pending register low 0 iprl0 32 ipsbar + 0xc08 interrupt mask register high 0 imrh0 32 ipsbar + 0xc0c interrupt mask register low 0 imrl0 32 ipsbar + 0xc10 interrupt forc e register high 0 intfrch0 32 ipsbar + 0xc14 interrupt force register low 0 intfrcl0 32 table a-3. register memory map (continued) address name mnemonic size mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 register memory map freescale semiconductor a-9 ipsbar + 0xc18 interrupt level request register 0 ilrr0 8 ipsbar + 0xc19 interrupt acknowledge level and priority register 0 iacklpr0 8 ipsbar + 0xc41 interrupt cont rol register 0-01 icr001 8 ipsbar + 0xc42 interrupt cont rol register 0-02 icr002 8 ipsbar + 0xc43 interrupt cont rol register 0-03 icr003 8 ipsbar + 0xc44 interrupt cont rol register 0-04 icr004 8 ipsbar + 0xc45 interrupt cont rol register 0-05 icr005 8 ipsbar + 0xc46 interrupt cont rol register 0-06 icr006 8 ipsbar + 0xc47 interrupt cont rol register 0-07 icr007 8 ipsbar + 0xc48 interrupt cont rol register 0-08 icr008 8 ipsbar + 0xc49 interrupt cont rol register 0-09 icr009 8 ipsbar + 0xc4a interrupt cont rol register 0-10 icr010 8 ipsbar + 0xc4b interrupt cont rol register 0-11 icr011 8 ipsbar + 0xc4c interrupt cont rol register 0-12 icr012 8 ipsbar + 0xc4d interrupt cont rol register 0-13 icr013 8 ipsbar + 0xc4e interrupt cont rol register 0-14 icr014 8 ipsbar + 0xc4f interrupt cont rol register 0-15 icr015 8 ipsbar + 0xc51 interrupt cont rol register 0-17 icr017 8 ipsbar + 0xc52 interrupt cont rol register 0-18 icr018 8 ipsbar +0xc53 interrupt cont rol register 0-19 icr019 8 ipsbar + 0xc54 interrupt cont rol register 0-20 icr020 8 ipsbar + 0xc55 interrupt cont rol register 0-21 icr021 8 ipsbar + 0xc56 interrupt cont rol register 0-22 icr022 8 ipsbar + 0xc57 interrupt cont rol register 0-23 icr023 8 ipsbar + 0xc58 interrupt cont rol register 0-24 icr024 8 ipsbar + 0xc59 interrupt cont rol register 0-25 icr025 8 ipsbar + 0xc5a interrupt cont rol register 0-26 icr026 8 ipsbar + 0xc5b interrupt cont rol register 0-27 icr027 8 ipsbar + 0xc5c interrupt cont rol register 0-28 icr028 8 ipsbar + 0xc5d interrupt cont rol register 0-29 icr029 8 ipsbar + 0xc5e interrupt cont rol register 0-30 icr030 8 ipsbar + 0xc5f interrupt cont rol register 0-31 icr031 8 ipsbar + 0xc60 interrupt cont rol register 0-32 icr032 8 table a-3. register memory map (continued) address name mnemonic size mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 register memory map a-10 freescale semiconductor ipsbar + 0xc61 interrupt cont rol register 0-33 icr033 8 ispbar + 0xc62 interrupt cont rol register 0-34 icr034 8 ipsbar + 0xc63 interrupt cont rol register 0-35 icr035 8 ipsbar + 0xc64 interrupt cont rol register 0-36 icr036 8 ipsbar + 0xc65 interrupt cont rol register 0-37 icr037 8 ipsbar + 0xc66 interrupt cont rol register 0-38 icr038 8 ipsbar + 0xc67 interrupt cont rol register 0-39 icr039 8 ipsbar + 0xc68 interrupt cont rol register 0-40 icr040 8 ipsbar + 0xc69 interrupt cont rol register 0-41 icr041 8 ipsbar + 0xc6a interrupt cont rol register 0-42 icr042 8 ipsbar + 0xc6b interrupt cont rol register 0-43 icr043 8 ipsbar + 0xc6c interrupt cont rol register 0-44 icr044 8 ipsbar + 0xc6d interrupt co ntrol register 0-45 icr45 8 ipsbar + 0xc6e interrupt cont rol register 0-46 icr046 8 ipsbar + 0xc6f interrupt cont rol register 0-47 icr047 8 ipsbar + 0xc70 interrupt cont rol register 0-48 icr048 8 ipsbar + 0xc71 interrupt cont rol register 0-49 icr049 8 ipsbar + 0xc72 interrupt cont rol register 0-50 icr050 8 ipsbar + 0xc73 interrupt cont rol register 0-51 icr051 8 ipsbar + 0xc74 interrupt cont rol register 0-52 icr052 8 ipsbar + 0xc75 interrupt cont rol register 0-53 icr053 8 ipsbar + 0xc76 interrupt cont rol register 0-54 icr054 8 ipsbar + 0xc77 interrupt cont rol register 0-55 icr055 8 ipsbar + 0xc78 interrupt cont rol register 0-56 icr056 8 ipsbar + 0xc79 interrupt cont rol register 0-57 icr057 8 ipsbar + 0xc7a interrupt cont rol register 0-58 icr058 8 ipsbar + 0xc7b interrupt cont rol register 0-59 icr059 8 ipsbar + 0xc7c interrupt cont rol register 0-60 icr060 8 ipsbar + 0xc7d interrupt cont rol register 0-61 icr061 8 ipsbar + 0xc7e interrupt cont rol register 0-62 icr062 8 ipsbar + 0xce0 software interrupt acknowledge register 0 swackr0 8 ipsbar + 0xce4 level 1 interrupt acknowledge register 0 l1iackr0 8 ipsbar + 0xce8 level 2 interrupt acknowledge register 0 l2iackr0 8 table a-3. register memory map (continued) address name mnemonic size mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 register memory map freescale semiconductor a-11 ipsbar + 0xcec level 3 interrupt acknowledge register 0 l3iackr0 8 ipsbar + 0xcf0 level 4 interrupt acknowledge register 0 l4iackr0 8 ipsbar + 0xcf4 level 5 interrupt acknowledge register 0 l5iackr0 8 ipsbar + 0xcf8 level 6 interrupt acknowledge register 0 l6iackr0 8 ipsbar + 0xcfc level 7 interrupt acknowledge register 0 l7iackr0 8 interrupt controller 1 ipsbar + 0xd00 interrupt pend ing register high 1 iprh1 32 ipsbar + 0xd04 interrupt pending register low 1 iprl1 32 ipsbar + 0xd08 interrupt mask register high 1 imrh1 32 ipsbar + 0xd0c interrupt mask register low 1 imrl1 32 ipsbar + 0xd10 interrupt forc e register high 1 intfrch1 32 ipsbar + 0xd14 interrupt force register low 1 intfrcl1 32 ipsbar + 0xd18 interrupt level request register 1 ilrr1 8 ipsbar + 0xd19 interrupt acknowledge le vel and priority register 1 iacklpr1 8 ipsbar + 0xd48 interrupt cont rol register 1-08 icr108 8 ipsbar + 0xd49 interrupt cont rol register 1-09 icr109 8 ipsbar + 0xd4a interrupt cont rol register 1-10 icr110 8 ipsbar + 0xd4b interrupt cont rol register 1-11 icr111 8 ipsbar + 0xd4c interrupt cont rol register 1-12 icr112 8 ipsbar + 0xd4d interrupt cont rol register 1-13 icr113 8 ipsbar + 0xd4e interrupt cont rol register 1-14 icr114 8 ipsbar + 0xd4f interrupt cont rol register 1-15 icr115 8 ipsbar + 0xd50 interrupt cont rol register 1-16 icr116 8 ipsbar + 0xd51 interrupt cont rol register 1-17 icr117 8 ipsbar + 0xd52 interrupt cont rol register 1-18 icr118 8 ipsbar + 0xd53 interrupt cont rol register 1-19 icr119 8 ipsbar + 0xd54 interrupt cont rol register 1-20 icr120 8 ipsbar + 0xd55 interrupt cont rol register 1-21 icr121 8 ipsbar + 0xd56 interrupt cont rol register 1-22 icr122 8 ipsbar + 0xd57 interrupt cont rol register 1-23 icr123 8 ipsbar + 0xd58 interrupt cont rol register 1-24 icr124 8 ipsbar + 0xd59 interrupt cont rol register 1-25 icr125 8 table a-3. register memory map (continued) address name mnemonic size mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 register memory map a-12 freescale semiconductor ipsbar + 0xd5a interrupt cont rol register 1-26 icr126 8 ipsbar + 0xde0 software interrupt acknowledge register 1 swackr1 8 ipsbar + 0xde4 level 1 interrupt acknowledge register 1 l1iackr1 8 ipsbar + 0xde8 level 2 interrupt acknowledge register 1 l2iackr1 8 ipsbar + 0xdec level 3 interrupt acknowledge register 1 l3iackr1 8 ipsbar + 0xdf0 level 4 interrupt acknowledge register 1 l4iackr1 8 ipsbar + 0xdf4 level 5 interrupt acknowledge register 1 l5iackr1 8 ipsbar + 0xdf8 level 6 interrupt acknowledge register 1 l6iackr1 8 ipsbar + 0xdfc level 7 interrupt acknowledge register 1 l7iackr1 8 global interrupt acknowledge cycle registers ipsbar + 0xfe0 global software interrupt acknowledge register gswackr 8 ipsbar + 0xfe4 global level 1 interrupt acknowledge register gl1iackr 8 ipsbar + 0xfe8 global level 2 interrupt acknowledge register gl2iackr 8 ipsbar + 0xfec global level 3 interrupt acknowledge register gl3iackr 8 ipsbar + 0xff0 global level 4 interrupt acknowledge register gl4iackr 8 ipsbar + 0xff4 global level 5 interrupt acknowledge register gl5iackr 8 ipsbar + 0xff8 global level 6 interrupt acknowledge register gl6iackr 8 ipsbar + 0xffc global level 7 interrupt acknowledge register gl7iackr 8 fec registers (reserved for mcf5214 and mcf5216) ipsbar + 0x1004 interrupt event register eir 32 ipsbar + 0x1008 interrupt mask register eimr 32 ipsbar + 0x1010 receive descrip tor active register rdar 32 ipsbar + 0x1014 transmit descriptor active register xdar 32 ipsbar + 0x1024 ethernet control register ecr 32 ipsbar + 0x1040 mii data register mdata 32 ipsbar + 0x1044 mii speed control register mscr 32 ipsbar + 0x1064 mib contro l/status register mibc 32 ipsbar + 0x1084 receive control register rcr 32 ipsbar + 0x10c4 transmit control register tcr 32 ipsbar + 0x10e4 physical address low palr 32 ipsbar + 0x10e8 physical address high+ type field paur 32 ipsbar + 0x10ec opcode + pause duration opd 32 table a-3. register memory map (continued) address name mnemonic size mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 register memory map freescale semiconductor a-13 ipsbar + 0x1118 upper 32 bits of individual hash table iaur 32 ipsbar + 0x111c lower 32 bits of individual hash table ialr 32 ipsbar + 0x1120 upper 32-bits of group hash table gaur 32 ipsbar + 0x1124 lower 32-bits of group hash table galr 32 ipsbar + 0x1144 transmit fifo watermark tfwr 32 ipsbar + 0x114c fifo receive bound register frbr 32 ipsbar + 0x1150 fifo receive start address frsr 32 ipsbar + 0x1180 pointer to re ceive descriptor ring erdsr 32 ipsbar + 0x1184 pointer to tran smit descriptor ring etdsr 32 ipsbar + 0x1188 maximum receive buffer size emrbr 32 ipsbar + 0x1200-0x13ff ram used to store manag ement counters mib_ram 32 gpio registers ipsbar + 0x10_0000 port a output data register porta 8 ipsbar + 0x10_0001 port b output data register portb 8 ipsbar + 0x10_0002 port c output data register portc 8 ipsbar + 0x10_0003 port d output data register portd 8 ipsbar + 0x10_0004 port e output data register porte 8 ipsbar + 0x10_0005 port f output data register portf 8 ipsbar + 0x10_0006 port g output data register portg 8 ipsbar + 0x10_0007 port h output data register porth 8 ipsbar + 0x10_0008 port j output data register portj 8 ipsbar + 0x10_0009 port dd output data register portdd 8 ipsbar + 0x10_000a port eh output data register (reserved for mcf5214 and mcf5216) porteh 8 ipsbar + 0x10_000b port el output data register portel 8 table a-3. register memory map (continued) address name mnemonic size mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 register memory map a-14 freescale semiconductor ipsbar + 0x10_000c port as output data register portas 8 ipsbar + 0x10_000d port qs output data register portqs 8 ipsbar + 0x10_000e port sd output data register portsd 8 ipsbar + 0x10_000f port tc output data register porttc 8 ipsbar + 0x10_0010 port td output data register porttd 8 ipsbar + 0x10_0011 port ua output data register portua 8 ipsbar + 0x10_0014 port a data direction register ddra 8 ipsbar + 0x10_0015 port b data direction register ddrb 8 ipsbar + 0x10_0016 port c data direction register ddrc 8 ipsbar + 0x10_0017 port d data direction register ddrd 8 ipsbar + 0x10_0018 port e data direction register ddre 8 ipsbar + 0x10_0019 port f data direction register ddrf 8 ipsbar + 0x10_001a port g data direction register ddrg 8 ipsbar + 0x10_001b port h data direction register ddrh 8 ipsbar + 0x10_001c port j data direction register ddrj 8 ipsbar + 0x10_001d port dd data direction register ddrdd 8 ipsbar + 0x10_001e port eh data direction register (reserved for mcf5214 and mcf5216) ddreh 8 ipsbar + 0x10_001f port el data direction register ddrel 8 ipsbar + 0x10_0020 port as data direction register ddras 8 ipsbar + 0x10_0021 port qs data direction register ddrqs 8 table a-3. register memory map (continued) address name mnemonic size mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 register memory map freescale semiconductor a-15 ipsbar + 0x10_0022 port sd data direction register ddrsd 8 ipsbar + 0x10_0023 port tc data direction register ddrtc 8 ipsbar + 0x10_0024 port td data direction register ddrtd 8 ipsbar + 0x10_0025 port ua data direction register ddrua 8 ipsbar + 0x10_0028 port a pin data/set data register portap/ seta 8 ipsbar + 0x10_0029 port b pin data/set data register portbp/ setb 8 ipsbar + 0x10_002a port c pin data/set data register portcp/ setc 8 ipsbar + 0x10_002b port d pin data/set data register portdp/ setd 8 ipsbar + 0x10_002c port e pin data/set data register portep/ sete 8 ipsbar + 0x10_002d port f pin data/set data register portfp/ setf 8 ipsbar + 0x10_002e port g pin data/set data register portgp/ setg 8 ipsbar + 0x10_002f port h pin data/set data register porthp/ seth 8 ipsbar + 0x10_0030 port j pin data/set data register portjp/ setj 8 ipsbar + 0x10_0031 port dd pin data/set data register portddp/ setdd 8 ipsbar + 0x10_0032 port eh pin data/set data registerport eh data direction register (reserved for mcf5214 and mcf5216) portehp/ seteh 8 ipsbar + 0x10_0033 port el pin data/set data register portelp/ setel 8 ipsbar + 0x10_0034 port as pin data/set data register portasp/ setas 8 ipsbar + 0x10_0035 port qs pin data/set data register portqsp/ setqs 8 ipsbar + 0x10_0036 port sd pin data/set data register portsdp/ setsd 8 ipsbar + 0x10_0037 port tc pin data/set data register porttcp/ settc 8 table a-3. register memory map (continued) address name mnemonic size mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 register memory map a-16 freescale semiconductor ipsbar + 0x10_0038 port td pin data/set data register porttdp/ settd 8 ipsbar + 0x10_0039 port ua pin data/set data register portuap/ setua 8 ipsbar + 0x10_003c port a clear output data register clra 8 ipsbar + 0x10_003d port b clear output data register clrb 8 ipsbar + 0x10_003e port c clear output data register clrc 8 ipsbar + 0x10_003f port d clear output data register clrd 8 ipsbar + 0x10_0040 port e clear output data register clre 8 ipsbar + 0x10_0041 port f clear output data register clrf 8 ipsbar + 0x10_0042 port g clear output data register clrg 8 ipsbar + 0x10_0043 port h clear output data register clrh 8 ipsbar + 0x10_0044 port j clear output data register clrj 8 ipsbar + 0x10_0045 port dd clear output data register clrdd 8 ipsbar + 0x10_0046 port eh clear output data registerport eh data direction register (reserved for mcf5214 and mcf5216) clreh 8 ipsbar + 0x10_0047 port el clear output data register clrel 8 ipsbar + 0x10_0048 port as clear output data register clras 8 ipsbar + 0x10_0049 port qs clear output data register clrqs 8 ipsbar + 0x10_004a port sd clear output data register clrsd 8 ipsbar + 0x10_004b port tc clear output data register clrtc 8 ipsbar + 0x10_004c port td clear output data register clrtd 8 ipsbar + 0x10_004d port ua clear output data register clrua 8 table a-3. register memory map (continued) address name mnemonic size mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 register memory map freescale semiconductor a-17 ipsbar + 0x10_0050 port b, c, and d pin assignment register pbcdpar 8 ipsbar + 0x10_0051 port f pin assignment register pfpar 8 ipsbar + 0x10_0052 port e pin assignment register pepar 16 ipsbar + 0x10_0054 port j pin assignment register pjpar 8 ipsbar + 0x10_0055 port sd pin assignment register psdpar 8 ipsbar + 0x10_0056 port as pin assignment register paspar 16 ipsbar + 0x10_0058 port eh and el pin assignment register (port eh is not present on mcf5214 and mcf5216) pehlpar 8 ipsbar + 0x10_0059 port qs pin assignment register pqspar 8 ipsbar + 0x10_005a port tc pin assignment register ptcpar 8 ipsbar + 0x10_005b port td pin assignment register ptdpar 8 ipsbar + 0x10_005c port ua pin assignment register puapar 8 reset control, chip configuration, and power management registers ipsbar + 0x11_0000 reset control register rcr 8 ipsbar + 0x11_0001 reset status register rsr 8 ipsbar + 0x11_0004 chip configuration register ccr 16 ipsbar + 0x11_0007 low-power control register lpcr 8 ipsbar + 0x11_0008 reset configuration register rcon 16 ipsbar + 0x11_000a chip identification register cir 16 clock module registers ipsbar + 0x12_0000 synthesizer control register syncr 16 ipsbar + 0x12_0002 synthesizer status register synsr 16 table a-3. register memory map (continued) address name mnemonic size mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 register memory map a-18 freescale semiconductor edge port registers ipsbar + 0x13_0000 eport pin assignment register eppar 16 ipsbar + 0x13_0002 eport data direction register epddr 8 ipsbar + 0x13_0003 eport interrupt enable register epier 8 0x0013_0004 eport data register epdr 8 ipsbar + 0x13_0005 eport pin data register eppdr 8 0x0013_0006 eport flag register epfr 8 watchdog timer registers ipsbar + 0x14_0000 watchdog control register wcr 16 ipsbar + 0x14_0002 watchdog modulus register wmr 16 ipsbar + 0x14_0004 watchdog count register wcntr 16 ipsbar + 0x14_0006 watchdog service register wsr 16 programmable interrupt timer 0 registers ipsbar + 0x15_0000 pit control and status register 0 pcsr 0 16 ipsbar + 0x15_0002 pit modulus register 0 pmr 0 16 ipsbar + 0x15_0004 pit count register 0 pcntr 0 16 programmable interrupt timer 1 registers ipsbar + 0x16_0000 pit control and status register 1 pcsr 1 16 ipsbar + 0x16_0002 pit modulus register 1 pmr 1 16 ipsbar + 0x16_0004 pit count register 1 pcntr 1 16 programmable interrupt timer 2 registers ipsbar + 0x17_0000 pit control and status register 2 pcsr 2 16 table a-3. register memory map (continued) address name mnemonic size mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 register memory map freescale semiconductor a-19 ipsbar + 0x17_0002 pit modulus register 2 pmr 2 16 ipsbar + 0x17_0004 pit count register 2 pcntr 2 16 programmable interrupt timer 3 registers ipsbar + 0x18_0000 pit control and status register 3 pcsr 3 16 ipsbar + 0x18_0002 pit modulus register 3 pmr 3 16 ipsbar + 0x18_0004 pit count register 3 pcntr 3 16 qadc registers 0x19_0000 qadc module configuration register qadcmcr 16 0x19_0006 port qa data register portqa 8 ipsbar + 0x19_0007 port qb data register portqb 8 0x19_0008 port qa data direction register ddrqa 8 ipsbar + 0x19_0009 port qb data direction register ddrqb 8 0x19_000a qadc control register 0 qacr0 16 0x19_000c qadc control register 1 qacr1 16 0x19_000e qadc control register 2 qacr2 16 0x19_0010 qadc status register 0 qasr0 16 0x19_0012 qadc status register 1 qasr1 16 0x19_0200? 0x19_027e conversion command word table ccw0? ccw63 64x16 0x19_0280? 0x19_02fe right justified, unsigned result register rjurr0? rjurr63 64x16 0x19_0300? 0x19_037e left justified, signed result register ljsrr0? ljsrr63 64x16 0x19_0380? 0x19_03fe left justified, unsigned result register ljurr0? ljurr63 64x16 general purpose timer a registers ipsbar + 0x1a_0000 gpta ic/oc select register gptaios 8 ipsabar + 0x1a_0001 gpta compare force register gptacforc 8 table a-3. register memory map (continued) address name mnemonic size mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 register memory map a-20 freescale semiconductor ipsbar + 0x1a_0002 gpta output compare 3 mask register gptaoc3m 8 ipsbar + 0x1a_0003 gpta output compare 3 data register gptaoc3d 8 ipsbar + 0x1a_0004 gpta counter register gptacnt 16 ipsbar + 0x1a_0006 gpta system control register 1 gptascr1 8 ipsbar + 0x1a_0008 gpta toggle-on-overflow register gptatov 8 ipsbar + 0x1a_0009 gpta control register 1 gptactl1 8 ipsbar + 0x1a_000b gpta control register 2 gptactl2 8 ipsbar + 0x1a_000c gpta interrupt enable register gptaie 8 ipsbar + 0x1a_000d gpta system control register 2 gptascr2 8 ipsbar + 0x1a_000e gpta flag register 1 gptaflg1 8 ipsbar + 0x1a_000f gpta flag register 2 gptaflg2 8 ipsbar + 0x1a_0010 gpta channel 0 register gptac0 16 ipsbar + 0x1a_0012 gpta channel 1 register gptac1 16 ipsbar + 0x1a_0014 gpta channel 2 register gptac2 16 ipsbar + 0x1a_0016 gpta channel 3 register gptac3 16 ipsbar + 0x1a_0018 pulse accumulator control register gptapactl 8 ipsbar + 0x1a_0019 pulse accumulator flag register gptpaflg 8 ipsbar + 0x1a_001a pulse accumulator counter register gptapacnt 8 ipsbar + 0x1a_001d gpta port data register gptaport 8 ipsbar + 0x1a_001e gpta port data direction register gptaddr 8 table a-3. register memory map (continued) address name mnemonic size mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 register memory map freescale semiconductor a-21 general purpose timer b registers ipsbar + 0x1b_0000 gptb ic/oc select register gptbios 8 ipsbar + 0x1b_0001 gptb compare force register gptbcforc 8 ipsbar + 0x1b_0002 gptb output compare 3 mask register gptboc3m 8 ipsbar + 0x1b_0003 gptb output compare 3 data register gptboc3d 8 ipsbar + 0x1b_0004 gptb counter register gptbcnt 16 ipsbar + 0x1b_0006 gptb system control register 1 gptbscr1 8 ipsbar + 0x1b_0008 gptb toggle-on-overflow register gptbtov 8 ipsbar + 0x1b_0009 gptb control register 1 gptbctl1 8 ipsbar + 0x1b_000b gptb control register 2 gptbctl2 8 ipsbar + 0x1b_000c gptb interrupt enable register gptbie 8 ipsbar + 0x1b_000e gptb system control register 2 gptbscr2 8 ipsbar + 0x1b_000e gptb flag register 1 gptbflg1 8 ipsbar + 0x1b_000f gptb flag register 2 gptbflg2 8 ipsbar + 0x1b_0010 gptb channel 0 register gptbc0 16 ipsbar + 0x1b_0012 gptb channel 1 register gptbc1 16 ipsbar + 0x1b_0014 gptb channel 2 register gptbc2 16 ipsbar + 0x1b_0016 gptb channel 3 register gptbc3 16 ipsbar + 0x1b_0018 pulse accumulator control register gptbpactl 8 ipsbar + 0x1b_0019 pulse accumulator flag register gptbpaflg 8 table a-3. register memory map (continued) address name mnemonic size mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 register memory map a-22 freescale semiconductor ipsbar + 0x1b_001a pulse accumulator counter register gptbpacnt 16 ipsbar + 0x1b_001d gptb port data register gptbport 8 ipsbar + 0x1b_001e gptb port data direction register gptbddr 8 flexcan registers ipsbar + 0x1c_0000 module configuration register canmcr 16 ipsbar + 0x1c_0006 control register 0 canctrl0 8 ipsbar + 0x1c_0007 control register 1 canctrl1 8 ipsbar + 0x1c_0008 prescaler divider presdiv 8 ipsbar + 0x1c_0009 control register 2 canctrl2 8 ipsbar + 0x1c_000a free running timer timer 16 ipsbar + 0x1c_0010 rx global mask rxgmask 32 ipsbar + 0x1c_0014 rx buffer 14 mask rx14mask 32 ipsbar + 0x1c_0018 rx buffer 15 mask rx15mask 32 ipsbar + 0x1c_0020 error and status esr 16 ipsbar + 0x1c_0022 interrupt masks imask 16 ipsbar + 0x1c_0024 interrupt flags iflag 16 ipsbar + 0x1c_0026 rx error counters rxerrcnt 8 ipsbar + 0x1c_0027 tx error counter txerrcnt 8 ipsbar + 0x1c_0080 message buffer 0 - message buffer 15 mbuff0? mbuff15 16x16bytes flash registers ipsbar + 0x1d_0000 cfm configuration register cfmmcr 16 table a-3. register memory map (continued) address name mnemonic size mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 register memory map freescale semiconductor a-23 ipsbar + 0x1d_0002 cfm clock divider register cfmclkd 8 ipsbar + 0x1d_0008 cfm security register cfmsec 32 ipsbar + 0x1d_0010 cfm protection register cfmprot 32 ipsbar + 0x1d_0014 cfm supervisor access register cfmsacc 32 ipsbar + 0x1d_0018 cfm data access register cfmdacc 32 ipsbar + 0x1d_0020 cfm user status register cfmustat 8 ipsbar + 0x1d_0024 cfm command register cfmcmd 8 1 the dma module originally supported a left-justified 16 -bit byte count register (bcr). this function was later reimplemented as a right-justified 24-bit bcr. the operation of the dma and the interpretation of the bcr is controlled by the mpark[bcr24bit]. see chapter 8, ?system control module (scm) ? for more details. 2 umr1 n , umr2 n , and ucsr n should be changed only after the receiver/transmitter is issued a software reset command. that is, if channel operation is not disabled, undesirable results may occur. table a-3. register memory map (continued) address name mnemonic size mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 register memory map a-24 freescale semiconductor mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor b-1 appendix b revision history this appendix lists major changes betw een versions of the mcf5282um document. b.1 changes between rev. 0 and rev. 0.1 table b-1. rev. 0 to rev. 0.1 changes location description title page changed title from ?mcf5282 coldfire ? integrated microprocessor user?s manual? to ?mcf5282 coldfire ? microcontroller user?s manual.? 33.1/33-1 added ?this product incorporates superflash? technology licensed from sst.? table 9-4 on page 9-6 changed equation in footnote to f sys = f ref 2(mfd + 2)/2 exp rfd; f ref 2(mfd + 2) 80 mhz, f sys 66 mhz. table 9-4 on page 9-6 multiplied all pll frequencies in table by 2. table 10-13 on page 10-13 changed dtmrx to dtimx. figure 10-1 on page 10-6 changed bit numbers from 63?32 to 31?0. figure 10-3 on page 10-8 changed bit numbers from 63?32 to 31?0. figure 10-5 on page 10-10 changed bit numbers from 63?32 to 31?0. 14.2.4/14-22 added section 14.2.4, ?chip configuration signals .? table 14-3 on page 14-11 added ta b l e 1 4 - 3 . 15.2/15-3 added ?unlike the mcf5272, the mcf5282 does not have an independent sdram clock signal. for the mcf5282, the timing of the sdram controller is controlled by the clkout signal.? 15.2.3.2/15-13 added section 15.2.3.2, ?sdram byte strobe connections .? 15.2.3.1/15-9 added ?note: because the mcf5282 has 24 external address lines, the maximum sdram address size is 128 mbits.? figure 27-4 on page 27-6 changed reset value to 0010_0000_0000_0000. chapter 30, ?debug support ? changed ?pstclk? references to ?clkout.? figure 30-41 on page 30-45 changed ?tea ? to ?ta .? mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 revision history b-2 freescale semiconductor b.2 changes between rev. 0.1 and rev. 1 figure 32-1 on page 32-2 changed ?ras0? and ?ras1? to ?sdram_cs0? and ?sdram_cs1.? table 32-1 on page 32-4 added ta b l e 3 2 - 1 . table 33-3 on page 33-3 changed max input high voltage to 5.25 v. appendix a, ?register memory map changed ?system integration module ? to ?system control module.? table b-2. rev. 0.1 to rev. 1 changes location description figure 6-1 on page 6-3 replaced figure 6-1 with a more accurate block diagram. 6.2/6-2 enhanced discussion of flash blocks. 6.3.4.3/6-10 added ?note: enabling flash security will disable bdm communications.? 6.3.4.3/6-10 added ?note: when flash security is enabled, the chip will boot in single chip mode regardless of the external reset configuration.? 6.4.3.1/6-17 changed text in step 1 to read ?if f sys 2 is greater than 12.8 mhz, prdiv8 = 1; otherwise prdiv8 = 0.? 6.4.3.1/6-17 changed equation in step 2 to the following: 6.4.3.1/6-17 changed equation in step 3 to the following: 6.4.3.1/6-17 changed equations in example to reflect revisions above. 6.4.3.1/6-17 changed text to read ?so, for f sys = 66 mhz, writing 0x54 to cfmclkd will set fclk to 196.43 khz which is a valid frequency for the timing of program and erase functions.? 6.4.3.1/6-17 changed text to read ?consider the follwoing example for f sys = 66 mhz.? table 6-12 on page 6-16 added ?page erase verify? category. table 6-13 on page 6-19 added ?page erase verify? category and description. table 6-14 on page 6-23 added ?access error? row. table b-1. rev. 0 to rev. 0.1 changes (continued) location description f sys 2 x 200khz x (1 + (prdiv8 x 7)) div[5:0] = f sys 2 x (div[5:0] + 1) x (1 + (prdiv8 x 7)) f clk = mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 revision history freescale semiconductor b-3 chapter 8, ?system control module (scm) and 16.2/16-2 moved information in section 8.4.6, ?dma request control register,? to section 16.2, ?dma request control (dmareqc) .? figure 8-2 on page 8-4 changed offset for the copy of rambar to ?0x008.? table 8-5 on page 8-6 changed cwtic to cwtif. 8.5.2.1/8-9 changed text to read ?setting mpark[prk_last] causes the arbitration pointer to be parked on the highest priority master.? figure 9-2 on page 9-4 changed ? mfd (2?9)? to ? mfd (4?18).? table 9-7 on page 9-10 changed equation in ?normal pll clock mode? row to the following: f sys = f ref 2(mfd + 2)/2 rfd chapter 12, ?chip select module eliminated section 12.4.1.4, ?code example.? figure 12-4 on page 12-8 in ?reset: cscr0? row, changed ?d7, d6, d5? to ??, d19, d18.? table 14-1 on page 14-3 replaced ?scke ? with ?scke.? 17.4.21/17-23 changed text to read ?the transmit fifo uses addresses from the start of the fi fo to the location four bytes before the address programmed into the frsr.? table 17-29 on page 17-28 added the following footnote: ?the receive buffer point er, which contains the address of the associated data buffer, must always be evenly divisible by 16. the buffer must reside in memory external to the fec. this value is never modified by the ethernet controller.? table 17-30 on page 17-29 added the following footnote: ?the tran smit buffer pointer, which contains the address of the associated data buffer, must always be evenly divisible by 4. the buffer must reside in memory external to the fec. this value is never modified by the ethernet controller.? figure 18-1 on page 18-2 changed value in ?divide by? block to 8192. table 19-3 on page 19-4 multiplied all system clock divisor values in pre field description by 2. 19.3.3/19-7 changed equation in text to the following: timeout period = pre[3:0] ( pm[15:0] + 1) system clock 2 figure 23-12 on page 23-14 in ?uisr field? row, changed bit 6 to a reserved bit. table 23-10 on page 23-14 changed bit 6 to a reserved bit. table b-2. rev. 0.1 to rev. 1 changes (continued) location description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 revision history b-4 freescale semiconductor table 25-12 on page 25-22 changed equation in pres_div field description to the following: 27.6.2/27-8 added ?note: when flash security is enabled, the chip will boot in single chip mode regardless of the external reset configuration.? table 28-4 on page 28-10 changed equation in qpr field description to the following: table 28-5 on page 28-11 multiplied all f sys divisor values in this table by 2. 30.1/30-1 added ?note: enabling flash security will disable bdm communications.? figure 32-1 on page 32-2 replaced ?scke ? with ?scke.? table 32-1 on page 32-4 replaced ?pel2? with ?pel6, ? ?pnq 6? with ?pnq7,? ?pnq5? with ?pnq 6,? ?pel5? with ?pel1,? ?pnq4? with ?pnq5,? ?pnq3? with ?pnq4,? ?pnq2? with ?pnq3,? ?pnq1? with ?pnq2,? ?pnq0? with ?pnq1,? ?pqs0? with ?pqs1,? ?pqs1? with ?pqs0,? ?pj6? with ?pj7,? ?ras0 ? with ?sdram_cs0 ,? ?ras1 ? with ?sdram_cs1 ,? and ?scke ? with ?scke.? table 33-1 on page 33-1 changed value for ?esd target for human body model? to ?2000? and ?esd target for machine model? to ?200.? table 33-13 on page 33-11 changed value in ?maximum number of guaranteed prog ram/erase cycles before failure? row to ?10,000.? table 33-15 on page 33-12 changed the max value in specs b6a?b6c to ?0.5t cyc + 10.? table 33-15 on page 33-12 figure 33-3 on page 33-14 figure 33-4 on page 33-15 figure 33-5 on page 33-16 changed the min value in spec b7a to ?0.5t cyc + 2? and reflected the change in figure 33-3 , figure 33-4 , and figure 33-5 . table 33-16 on page 33-17 changed the min value in spec d8 to ?2? and the max value to?'??. table 33-17 on page 33-18 changed the max value in spec g1a to ?12.? table 33-17 on page 33-18 added the following footnote: ?because of long delay s associated with the pqa/pqb pads, signals on the pqa/pqb pins will be updated on the following edge of the clock.? table b-2. rev. 0.1 to rev. 1 changes (continued) location description s-clock f sys 2 presdiv + 1 () -------------------------------------------- - = f qclk = f sys 2(qpr[6:0] + 1) mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 revision history freescale semiconductor b-5 b.3 changes between rev. 1 and rev. 2 33.13/33-21 added timing diagrams and tables to section 33.13, ?fast ethernet ac timing specifications .? table 33-27 on page 33-25 changed the max value in spec 1 to ?1/4.? table 33-27 on page 33-25 changed the min value in spec 2 to ?4.? table 33-27 on page 33-25 changed the min value in spec 3 to ?25.? table 33-27 on page 33-25 changed the min value in spec 6 to ?25.? table 33-27 on page 33-25 changed the max value in spec 7 to ?30.? table 33-27 on page 33-25 changed the max value in spec 8 to ?30.? table 33-27 on page 33-25 changed the max value in spec 11 to ?25.? table 33-28 on page 33-27 changed the min value in spec d1 to ?5.? table 33-28 on page 33-27 changed the min value in spec d2 to ?2.? table a-3 on page a-3 changed offset for the copy of rambar to ?0x008.? table b-3. rev. 1 to rev. 2 changes location description throughout manual added mcf5281 device to manual. t he mcf5281 implements half the flash of the mcf5282. 1.1/1-1 changed the description of r eal time debug support. it has only one user-visible hardware breakpoint register. table 2-2/2-7 change the i field description to read: ?interrupt level mask. defines the current interrupt level. interrupt requests are inhibited for all priority levels less than or equal to the current level, except the edge-sensitive level 7 request, which cannot be masked.? table 5-1/5-2 replaced the description of pri1 and pri2. table 5-1/5-3 added note to the spv bit description, ?the bde bit in the second rambar register must also be set to allow dual port access to the sram. for more info rmation, see section 8.4.2, ?memory base address register (rambar).?? figure 6-2/6-4 replaced figure 6-2, ?cfm 512k array me mory map? and renamed it ?cfm array memory map? table 6-12/6-16 change value for page erase verify command to 0x06. table 6-13/6-20 change value for page erase verify command to 0x06. table b-2. rev. 0.1 to rev. 1 changes (continued) location description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 revision history b-6 freescale semiconductor table 8-3/8-5 add the following note to th e bde bit description: ?the spv bit in the cpu?s rambar must also be set to allow dual port access to the sram. for more info rmation, see section 5.3.1, ?sram base address register (rambar).?? figure 9-1/9-3 remove 2 from clkgen block. 10.3.6/10-11 add this text to the end of the first paragraph: ?if a specific interrupt request is completely unused, the icr nx value can remain in its re set (and disabled) state.? 10.5/10-17 added the following note : ?the wakeup mask level taken from lpi cr[6:4] is adjusted by hardware to allow a level 7 irq to generate a wakeup. that is, the wakeup mask value used by the interrupt controller must be in the range of 0?6.? figure 12-4/12-8 changed cscr n to reflect that aa is set at reset. 13.5/13-15 removed final paragraph. the paragraph incorrectly states that the mcf5282 does not have a bus monitor. table 14-3/14-11 changed pull-up indications in the ?internal pull-up? column. table 17-13/17-26 change encodings for bits 31?9 to: 0 the corresponding interrupt source is masked. 1the corresponding interrupt source is not masked. chapter 19 change pit1?pit4 to pit0?p it3 throughout chapter. when a timer is referenced individually, pit1 should be pit0, pit2 should be pit1, pit3 should be pit2, and pit4 should be pit3. other chapters in the user?s manual use the co rrect nomenclature: pit0?pit3. 19.6.3/19-7 change timeout period equation to the equation below. figure 23-11 change uisr bits 5?3 to reserved bits 24.6.1/24-11 change ?i2cr = 0xa? to ?i2cr = 0xa0.? 27.2.1/27-2 changed ?when interfacing to 16-bit ports, the port c and d pins and pj[ 5:4 ] (bs [ 1:0 ]) can be configured as general-purpose input/output (i/o)? 32.2/32-7 added additional device number order information to ta b l e 3 2 - 2 for mcf5280 and mcf5281 at 66- and 80-mhz, and mcf5282 at 80 mhz. chapter 33 delete references to ?t a = t l to t h ?. table 33-1/33-1 replace v in row with the row below, in which the maximum value has been changed to 6.0 v. table 33-6/33-8 replace i dda row with the row below, in which the maximum value in normal operation has been changed to 5.0 ma. figure 33-5/33-16 replaced figure, ?sdram read cycle? table b-3. rev. 1 to rev. 2 changes (continued) location description timeout period pre[3:0] (pm[15:0] 1) +2 system clock ----------------------------------------------------------------------------- = mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 revision history freescale semiconductor b-7 b.4 changes between rev. 2 and rev. 2.1 b.5 changes between rev. 2.1 and rev. 2.2 b.6 changes between rev. 2.2 and rev. 2.3 table b-4. rev. 2 to rev. 2.1 changes location description title page added mcf5280 to ?devices supported? list on the title page. table 33-8/33-9 deleted reference to ?ta=tl to th? table b-5. rev. 2.1 to rev. 2.2 changes location description chapter 33 added power spec info to electricals chapter table b-6. rev. 2.2 to rev. 2.3 changes location description figure 4-2/4-6 changed bit 23 from didi to disi table 4-6/4-9 under ?configuration? for ?instruction cache? the ?operation? entry changed to ?invalidate 2 kbyte data cache? table 4-6/4-9 under ?configuration? for ?data cache? the ?o peration? entry changed to ?invalidate 2 kbyte instruction cache? figure 6-3/6-6 changed bit 8 to write-only instead of read/write table 6-10/6-15 removed ?selected by bksl[1:0]? as these are internal signal names not necessary for end-user. 10.3.2/10-8 added note after register descrip tions: ?if an interrupt source is being masked in the interrupt controller mask register (imr) or a module?s in terrupt mask register while the inte rrupt mask in the status register (sr[i]) is set to a value lower than the interrupt?s level, a spurious interrupt may occur. this is because by the time the status register acknowledges this in terrupt, the interrupt has been masked. a spurious interrupt is generated because the cpu cannot determin e the interrupt source. to avoid this situation for interrupts sources with levels 1-6, first write a high er level interrupt mask to the status register, before setting the mask in the imr or the module?s interrup t mask register. after the mask is set, return the interrupt mask in the status register to its previous value. since level seven interrupts cannot be disabled in the status register prior to masking, use of the imr or module interrupt mask registers to disable level seven interrupts is not recommended. table 17-2/17-5 in palr/paur entry, deleted ?(only needed for full duplex flow control)? figure 17-23/17-39 changed frsr to read/write instead of read-only 25.4.10/25-16 changed canicr to icr n table 25-17/25-29 added the following information to biterr and ackerr descriptions: ?to clear this bit, first read it as a one, then write it as a one. writing zero has no effect.? table 25-17/25-30 changed bit ordering: errint should be bit 2 and boffint should be bit 1. mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 revision history b-8 freescale semiconductor b.7 changes between rev. 2.3 and rev. 3 table 25-19/25-32 changed buf n i field description from ?to clear an interrupt flag, first read the flag as a one, then write it as a zero ? to ?to clear an interrupt flag, first read the flag as a one, then write it as a one .? chapter 33 updated power consumption tables. table b-7. rev. 2.3 to rev. 3 changes location description throughout added mcf5214 and mcf5216 to list of the devi ces supported in this document. these two devices are the same as the mcf5282 except they do not have an fec and have a rated frequency of 66 mhz. changed title of document. preface moved revision history to this appendix table 2-1/page 2-4 remove last sentence in c bit field description. table 2-3/page 2-7 change pc?s written with movec entry to ?no?. section 2.5/page 2-8 change last bullet to ?use of separate system stack pointers for user and supervisor modes? section 2.5/page 2-9 change last sentence in fourth paragraph (step 2) to ?the iack cycle is mapped to special locations within the interrupt controller's address space with the interrupt level encoded in the address." figure 3-6/page 3-8 add minus sign to the exponent so that it is ??(i + 1 ? n)?. table 4-3/page 4-5 change reset value of acr0, acr1 to ?see section? since some of the bits are undefined after reset. figure 4-2/page 4-6 change cacr fields to r/w, since they may be read via the debug module. table 4-5/page 4-8 for split instru ction/data cache entry, swap text in paranthese s in the description fi eld. instruction cache uses the upper half of the arrays, while data cache uses the lower half. figure 4-3/page 4-9 change reset value of acr: bits 31-16, 14-13, 6-5, and 2 are undefined, and other bits are cleared. change acr fields to r/w, since they may be read via the debug module. section 4.4.2.2/page 4-9 change note to: note peripheral (ipsbar) space should not be cached. the combination of the cacr defaults and the two acr n registers must define the non-cacheable attribute for this address space. figure 5-1/page 5-2 change rambar fields to r/w, since they may be read via the debug module. table 5-1/page 5-2 the pri1/pri2 text description does not match th e table below it. it should be: ?if a bit is set, cpu has priority. if a bit is cleared, dma has priority.? figure 6-3/page 6-6 changed flashbar[wp] to read-only. table 6-2/page 6-7 changed bit description of flashbar[wp] to read-only and that this bit is always set. table b-6. rev. 2.2 to rev. 2.3 changes (continued) location description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 revision history freescale semiconductor b-9 chapter 8 remove any references to the core watchdog timer being able to reset the device. it is only able to interrupt the processor. use the peripheral watc hdog timer described in chapter 18 if needing a watchdog timer to reset the device. table 8-5/page 8-6 cwcr[cwri] bit description, change ?...is progra mmed in the interrupt control register 7 (icr7)...? to ?...is programmed in the interrupt control register 8 (icr8)...? table 9-4/page 9-7 in the table for mfd bit defin ition, footnote (1) equation should read: where f sys(max) is the maximum system frequency for the particular mcf5282 device (66mhz or 80mhz) section 10.3.6/page 10-11 include the following text in the section description and as a note in figure 10-9. ?it is the responsibility of the software to program the icr n x registers with unique and non-overlapping level and priority definitions. failure to program the icr n x registers in this manner can result in undefined behavior. if a specific interrupt request is completely unused, the icr n x value can remain in its reset (and disabled) state.? figure 10-6/page 10-9 interrupt force register low (intfrcl n ) is illustrated as read-only in the figure. however, this register should be read/write. table 10-14/page 10-15 change flag clearing mechanism for sources 24-26. they should read as follows: write err_int = 1 after reading err_int = 1 write boff_int = 1 after reading boff_int = 1 write wake_int = 1 after reading wake_int = 1 table 12-7/page 12-7 bam bit field description, the first example should read ?so, if csar0 = 0x0000 and csmr0[bam] = 0x0001? instead of ?so, if csar0 = 0x0000 and csmr0[bam] = 0x0008?. table 10-2/page 10-4 in footnote, remove mention of the swiack register, as it is not supported in the global iack space. section 10.3.7/page 10-16 change last paragraph to: ?in addition to the iack re gisters within each interr upt controller, there are global l n iack registers. a read fr om one of the global l n iack registers returns the vector for the highest priority unmasked interrupt within a level for all interrupt controllers. there is no global swiack register. however, reading the swiack register from each inte rrupt controller returns th e vector number of the highest priority unmasked request within that controller.? figure 15-1/page 15-1 change sdram address lines from a[31:0] to a[23:0]. table 15-1/page 15-3 nop command entry. replace ?sras asserted? with ?sdram_cs [1:0] asserted? table 15-5/page 15-7 add the following note to the dacr n [cbm] field description: note: it is important to set cbm according to the location of the command bit. section 16.5/page 16-11 remove last sentence in th is section starting with ?bcr n decrements...? since saa bit is not supported. table b-7. rev. 2.3 to rev. 3 changes (continued) location description f sys f ref 2mfd 2 + () 2 rfd --------------------------------------------- f ref 2mfd 2 + () f sys max () f sys f sys max () ; ; = mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 revision history b-10 freescale semiconductor section 17.4.6/page 17-7 add the following subsection entitled ?duplicate frame transmission?: the fec fetches transmit buffer descriptors (txbds ) and the corresponding transmit data continuously until the transmit fifo is full. it does not determine whether the txbd to be fetched is already being processed internally (as a result of a wrap). as the fec nears the end of the transmission of one frame, it begins to dma the data for the next frame. in order to remain one bd ahead of the dma, it also fetches the txbd for the next frame. it is possible that the fec will fetch from memory a bd that has already been processed but not yet written back (that is, it is read a second time with the r bit still set). in this case, the data is fetched and transmitted again. using at least three txbds fixes this problem for larg e frames, but not for small frames. to ensure correct operation for either large or small frames, one of the following must be true: ? the fec software driver ensures that there is al ways at least one txbd with the ready bit cleared. ? every frame uses more than one txbd and every tx bd but the last is written back immediately after the data is fetched. ? the fec software driver ensures a minimum frame size, n . the minimum number of txbds is then (tx fifo size (n + 4)) rounded up to the nearest integer (though the result cannot be less than three). the default tx fifo size is 192 bytes; this size is programmable. table 17-9/page 17-17 correct mib block counters end addresses to ipsbar + 0x12ff. table 17-11/page 17-19 add rmon_r_drop with an ipsbar offset of 0x1280 and a descripti on of ?count of frames not counted correctly?. figure 17-26/page 17-41 change emrbr register address from ?ipsbar + 0x11b8? to ?ipsbar + 0x1188?. section 20.5.13/page 20-12 deleted reference to nonexistent cf bits in the figure and bit descriptions for the gptflg2 register. figure 23-18/page 23-18 remove the two 16-bit divider blocks from timer input, as the divider is not available using external clock sources. section 23.5.1.2.2/page 23-19 remove 16-bit divider from equation, as the divide r is not available using external clock sources. section 25.5.8/page 25-25 change end of last sentence from ?...and can be written by the host to ?0?.? to ?...and can be written by the host to ?1?.? table 25-17/page 25-29 remove the following information from the biterr and ackerr descriptions as these fields are read only: ?to clear this bit, first read it as a one, then writ e it as a one. writing zero has no effect.? (this is a rescindment of a previous documentation errata.) change last sentence in errint description from: ?to clear this bit, first read it as a one, then write as a zero. writing a one has no effect.? to ?to clear this bit, first read it as a one, then write a one. writing a zero has no effect.? add the following information to the boffint and wakeint descriptions: ?to clear this bit, first read it as a one, then write it as a one. writing zero has no effect.? table 25-17/page 25-27 definition of bits errint and boffint are incorrect for register estat: errint should be bit 1, boffint should be bit 2. they should be clea red by writing a one instead of a zero. table b-7. rev. 2.3 to rev. 3 changes (continued) location description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 revision history freescale semiconductor b-11 table 26-1/page 26-5 change description field for dtout1 from ?dma timer 1 output / port td[3]...? to ?dma timer 1 output / port td[2]...? change description field for dtin0 from ?dma timer 0 input / port td[3]...? to ?dma timer 1 output / port td[1]...? change description field for dtout0 from ?dma timer 0 output / port td[3]...? to ?dma timer 1 output / port td[0]...? chapter 27 the clkmod pins determine the clock mode regardless of rcon assertion during reset. because of this, the following were done for clarity: ? removed the rcon[rpllref, rpllsel] bit fields and descriptions. ? added the following note in the reset configuratio n section: ?the clkmod pins always determine the clock mode, regardless of the rcon pin value.? ? in the configuration during reset table, clock mode section, changed the default configuration from ?rcon[7:6]? to ?n/a? ? in clock mode selection section, changed ?the clock mode is selected during reset and reflected...? to ?the clock mode is selected during reset by the clkmod pins and reflected...? ? in clock mode selection table, added clkmod[1:0] column showing the corresponding clkmod settings for each mode. table 30-12/page 30-14 add the following note to the pbr[address] field description: note: pbr[0] should always be loaded with a 0. table 30-20/page 30-35 change csr?s initial state to 0x0000_0000. chapter 33 add the following note: ?it is crucial during power-up that vdd never exc eeds vddh by more that ~0.3v. there are diode devices between the two voltage domains, and violating this rule can lead to a latch-up condition.? table 33-3/page 33-3 in the v oh and v ol entries, change the respective i oh and i ol specs from ?i oh = -2.0ma? to ?i oh = -5.0ma? and ?i ol = +2.0ma? to ?i ol = +5.0ma? table 33-8/page 33-7 in the pll electrical specifications table, only specs for the 80mhz mcf5282 device were listed. insert specs for the 66mhz device in the first 2 rows and also declare symbol f sys(max) , as shown below: table 33-8/page 33-7 change extal input high voltage (v ihext ) crystal mode minimum spec from ?v dd -1.0? to ?v xtal +0.4?. change extal input low voltage (v ilext ) crystal mode maximum spec from ?1.0? to ?v xtal -0.4?. section 33.13.1/page 33-21 remove second sentence: ?there is no minimum frequency requirement.? table b-7. rev. 2.3 to rev. 3 changes (continued) location description characteristic symbol min max unit 66mhz 80mhz pll reference frequency range crystal reference external reference 1:1 mode f ref_crystal f ref_ext f ref_1:1 2 2 33.33 8.33 8.33 66.66 10.0 10.0 80 mhz system frequency 1 external clock mode on-chip pll frequency f sys 0 f ref / 32 f sys(max) 66.66 66.66 f sys(max) 80 80 mhz mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 revision history b-12 freescale semiconductor section 33.13.2/page 33-22 remove second sentence: ?there is no minimum frequency requirement.? remove second paragraph as this featur e is not supported on this device: ?the transmit outputs (etxd[3:0], etxen, etxer) can be programmed to transition from either the rising or falling edge of etxclk, and the timi ng is the same in either case. this options allows the use of non-compliant mii phys. refer to the ethernet chapter for details of this option and how to enable it.? table a-3/page a-4 the csmr1 and cscr1 register addresses are incorrect. they should be ipsbar + 0x090 and ipsbar + 0x096 respectively table b-7. rev. 2.3 to rev. 3 changes (continued) location description mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor index-1 appendix c index a a/d converter bias 28-34 block diagram 28-32 channel decode 28-33 comparator 28-33 cycle times 28-32 multiplexer 28-33 operation 28-31 sample buffer 28-33 state machine 28-34 successive approximation register (sar) 28-34 acknowledge error (ackerr) 25-26 address variant 30-4 analog inputs 28-66 analog power signals 28-56 analog reference signals 28-56 analog supply filtering 28-61 grounding 28-61 async inputs signal timing 33-23 b bdm see debug commands dump 30-27 fill 30-29 format 30-20 go 30-31 nop 30-31 rareg/rdreg 30-23 rcreg 30-31 rdmreg 30-35 read 30-24 sequence diagrams 30-21 summary 30-19 wareg/wdreg 30-23 wcreg 30-34 wdmreg 30-36 write 30-26 cpu halt 30-16 operation with processor 30-38 packet format receive 30-18 transmit 30-19 recommended pinout 30-45 register accesses emac 30-33 stack pointer 30-33 serial interface 30-18 timing diagrams bdm serial port ac timing 33-28 real-time trace ac timing 33-28 bit error (biterr) 25-26 bit stuff error (stufferr) 25-26 branch instruction execution times bra, bcc instruction execution times (table 3-16) 2-32 table 3-15 2-32 bus access by matches in cscr and dacr 13-4 characteristics 13-2 data transfer back-to-back cycles 13-9 burst cycles 13-10 allowable line access patterns 13-10 line read bus cycles 13-10 line transfers 13-10 line write bus cycles 13-12 cycle execution 13-3 cycle states 13-4 fast termination cycle 13-8 read cycle 13-6 write cycle 13-7 electrical characteristics input timing specifications 33-11 output timing specifications 33-12 features 13-1 internal arbitration 8-7 algorithms 8-9 fixed mode 8-9 overview 8-8 round-robin mode 8-9 mpark 8-9 operands, misaligned 13-14 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 index-2 freescale semiconductor sacu 8-11 bus off interrupt (boffint) 25-27 busy 25-11 bypass instruction 31-9 c cache block diagram 4-2 coherency 4-8 fill buffer 4-2 , 4-9 invalidation 4-8 miss fetch algorithm 4-9 organization 4-1 registers access control 0?1 (acr n )2-7 , 4-6 control (cacr) 2-7 , 4-3 sram interaction 4-7 channel flags 20-21 chip configuration module block diagram 27-2 boot device selection 27-9 chip mode selection 27-8 chip select 27-10 clock mode selection 27-9 features 27-1 interrupts 27-10 memory map 27-3 operation low-power modes 7-9 master mode 27-1 output pad strength 27-9 programming model 27-3 registers chip configur ation (ccr) 27-4 chip identification (cir) 27-6 reset configuration register (rcon) 27-5 reset configuration 27-7 single-chip mode 27-1 chip select module 8-, 16-, and 32-bit port sizing 12-3 memory map 12-4 operation external boot 12-4 general 12-3 low-power modes 7-7 port sizing 12-3 overview 12-1 registers address (csar n ) 12-6 control (cscr n ) 12-7 mask (csmr n )12-6 clamp 31-9 clock module block diagram 9-2 features 9-1 memory map 9-5 operation 1-1 pll mode 9-1 during reset 9-11 external clock mode 9-1 low-power modes 7-10 , 9-2 normal pll mode 9-1 pll charge pump/loop filter 9-12 , 9-13 lock detection 9-13 loss-of-clock alternate clock selection 9-15 detection 9-15 reset 9-15 stop mode 9-16 loss-of-lock conditions 9-14 reset 9-15 multiplication factor divider (mfd) 9-13 operation 9-11 phase and frequency detector (pfd) 9-12 voltage control output (vco) 9-13 registers synthesizer control (syncr) 9-6 synthesizer status (synsr) 9-8 system clock generation 9-11 modes 9-10 coldfire core branch instruction execution times 2-32 instruction set summary move instruction executino times move long execution times 2-27 move instruction execution times 2-26 move byte and word execu tion times table 3-9 2-27 timing assumptions 2-25 misaligned operand references table 3-8 2-26 coldfire flash module block diagram 6-2 configuration field 6-5 electrical characteristics module life 33-11 program and erase 33-10 features 6-1 interrupts 6-23 memory map 6-4 , 6-7 operation low-power modes 7-7 , 7-13 master mode 6-22 program and erase 6-17 , 6-18 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor index-3 reads 6-17 setting cfmclkd 6-17 stop mode 6-21 verify 6-18 writes 6-17 registers clock divider (cfmclkd) 6-9 setting 6-17 command (cfmcmd) 6-16 configuration (cfmcr) 6-8 data access (cfmdacc) 6-14 flashbar 6-5 protection (cfmprot) 6-12 security (cfmsec) 6-10 supervisor access (cfmsacc) 6-13 user status (cfmustat) 6-15 reset 6-23 security back door access 6-23 erase verify check 6-23 collision handling 17-42 core block diagram 2-1 low-power modes 7-6 registers address (a n )2-4 condition code (ccr) 2-6 data (d n )2-4 program counter (pc) 2-7 stack pointer (a7) 2-5 status register (sr) 2-8 vector base (vbr) 2-7 cyclic redundancy check error (crcerr) bit 25-26 d dc characteristics 33-3 debug see bdm breakpoint functions 30-7 operation 30-37 data 30-39 electrical characteristics ac timing specifications 33-27 emulator mode 30-38 interrupt 30-37 low-power modes 7-13 operation 30-37 overview 30-1 processor status 30-2 , 30-39 programming model 30-5 registers address attribute trigger (aatr) 30-7 address breakpoint (ablr, abhr) 30-9 configuration/status (csr) 30-10 data breakpoint/mask (dbr, dbmr) 30-12 program counter breakpoint/mask (pbr, pbmr) 30-13 trigger definition (tdr) 30-14 support, real-time 30-37 taken branch 30-4 trace, real-time 30-2 debug interrupt 30-37 dma controller channel prioritization 16-12 data transfer auto alignment 16-13 bandwidth control 16-14 dual-address 16-12 overview 16-4 requests 16-11 termination 16-14 functional description 16-11 low-power modes 7-7 overview 16-1 programming 16-12 registers byte count (bcr n ) 16-7 control (dcr n )16-7 destination address (dar n ) 16-6 request control (dmareqc) 16-2 source address (sar n ) 16-5 status (dsr n) 16-10 signal diagram 16-1 dma timers electrical characteristics ac timing specifications 33-24 operation low-power modes 7-8 doze mode 7-6 e electrical ch aracteristics bus external output timin g specifications 33-12 processor input timing specifications 33-11 coldfire flash module module life characteristics 33-11 program and erase characteristics 33-10 dc specifications 33-3 debug ac timing specifications 33-27 dma timer ac timing specifications 33-24 fec ac timing specifications 33-21 gpio timing 33-18 i 2 c input timing between scl and sda 33-20 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 index-4 freescale semiconductor i 2 c input/output timing specifications 33-20 i 2 c output timing between scl and sda 33-20 jtag and boundary scan timing 33-25 maximum ratings 33-1 mii async inputs signal timing 33-23 mii receive signal timing 33-21 mii serial management channel timing 33-23 mii transmit signal timing 33-22 pll specifications 33-4 qadc absolute maximum ratings 33-8 qadc operating conversion specifications 33-10 qadc operating electri cal specifications 33-9 qspi ac timing specifications 33-24 qspi specifications 33-24 reset and configuration override timing 33-19 sdram timing 33-17 thermal 33-2 emac data representation 3-14 instructions execution timing 3-13 summary 3-12 memory map 3-3 opcodes 3-14 operation fractional 3-10 registers bdm accesses 30-33 mask (mask) 3-5 status (macsr) 3-3 enable_test_ctrl instruction 31-8 end-of-frame (eof) 25-12 eport low-power modes 7-10 , 11-1 memory map 11-3 overview 11-1 programming model 7-1 registers data direction (epddr) 11-4 flag (epfr) 11-6 pin assignment (eppar) 11-3 pin data (eppdr) 11-6 port data (epdr) 11-5 port interrupt enable (epier) 11-5 error counters 25-13 error interrupt (errint) bit 25-27 ethernet address recognition 17-35 block diagram 17-2 buffer descriptors receive (rxbd) 17-27 transmit (txbd) 17-29 collision handling 17-42 electrical characteristics mii receive signal timing 33-21 mii serial management channel timing 33-23 mii transmit signal timing 33-22 errors handling 17-42 reception crc 17-44 frame length 17-44 non-octet 17-43 overrun 17-43 truncation 17-44 transmission attempts limit expired 17-43 heartbeat 17-43 late collision 17-43 underrun 17-43 frame reception 17-35 frame transmission 17-33 hash table 17-38 initialization 17-30 operation 10 mbps 7-wire 17-4 , 17-32 10 mbps and 100 mbps mii 17-32 full duplex 17-4 , 17-41 half duplex 17-4 loopback 17-42 low-power modes 7-9 registers control (ecr) 17-12 descriptor group upper/lower address (gaur/galr) 17-21 descriptor individual upper/lower (iaur/ialr) 17-20 descriptor individual upper/lower address (iaur/ialr) 17-20 fifo receive bound (frbr) 17-22 fifo receive start (frsr) 17-23 fifo transmit fifo watermark (tfwr) 17-22 interrupt event (eir) 17-9 interrupt mask (eimr) 17-10 mib control (mibc) 17-16 mii management frame (mmfr) 17-13 mii speed control (mscr) 17-15 opcode/pause duration (opd) 17-19 physical address low (palr n ) 17-18 physical address low/high (palr, paur) 17-18 receive buffer size (emrbr) 17-24 receive control (rcr) 17-16 receive descriptor active (rdar) 17-11 receive descriptor ri ng start (erdsr) 17-23 transmit buffer descriptor ring start (etsdr) 17-24 transmit control (tcr) 17-17 transmit descriptor active (tdar) 17-12 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor index-5 exceptions access error 2-18 divide-by-zero 2-20 exception stack frame 2-17 format error 2-21 illegal instruction 2-19 overview 2-15 privilege violation 2-20 reset 2-22 trace 2-20 trap instruction 2-22 external interface module (eim), see bus extest instruction 31-7 f fault confinement state (fcs) 25-27 fault-on-fault 2-22 fault-on-fault halt 30-17 fec, see ethernet flash, see coldfire flash module flexcan bit timing 25-12 can system overview 25-4 error counters 25-13 features 25-1 format frames 25-5 ? 25-7 idle bit 25-27 initialization sequence 25-14 interrupts 25-17 memory map 25-2 message buffers busy 25-6 empty 25-6 full 25-6 handling 25-10 locking and releasing 25-11 receive deactivation 25-10 serial message buffers 25-10 transmit deactivation 25-10 not active 25-6 overload frames 25-12 overrun 25-6 receive codes 25-6 error status flag (rxwarn) 25-27 pin configuration control (rxmode) 25-20 remote frames 25-11 self-received frames 25-10 status 25-27 structure 25-4 time stamp 25-12 transmit codes 25-6 error status flag (txwarn) 25-26 length 25-6 pin configuration control (txmode) 25-20 notrdy bit 25-17 operation auto power save mode 25-17 bit timing configuration 25-13 debug mode 25-15 listen-only mode 25-12 low-power modes 7-11 , 25-15 overview 25-1 receive process 25-9 registers bit timing 25-12 control 0?2 (canctrl n ) 25-20 ? 25-22 error and status (estat) 25-25 free running timer (timer) 25-23 interrupt flag (iflag) 25-28 interrupt mask (imask) 25-27 module configuration (canmcr) 25-18 prescaler divide (presdiv) 25-22 receive error coun ter (rxectr) 25-29 receive mask (rxgmask, rx n mask) 25-24 transmit error co unter (txectr) 25-30 samp bit 25-21 transmit process 25-8 frame reception, flexcan 25-9 frame transmission, flexcan 25-8 g general purpose timers block diagram 20-2 features 20-1 functional description 20-17 gpio ports 20-19 input capture 20-17 interrupts channel flags 20-21 pulse accumulator input 20-22 pulse accumulator overflow 20-22 timer overflow 20-22 low-power modes 7-11 memory map 20-4 operation event counter mode 20-18 gated time accumulation mode 20-19 low-power modes 20-3 output compare 20-18 prescaler 20-17 pulse accumulator event counter mode 20-18 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 index-6 freescale semiconductor gated time accumulation 20-19 registers channel (gptc n )20-13 compare force (gpcforc) 20-6 control 1?2 (gptctl n ) 20-9 counter (gptcnt) 20-7 flag 1?2 (gptflgn) 20-12 input capture/output compare select (gptios) 20-5 interrupt enable (gptie) 20-10 output compare 3 data (gptoc3d) 20-7 output compare 3 mask (gptoc3m) 20-6 port data (portt n ) 20-16 port data direction (gptddr) 20-17 pulse accumulator control (gptpactl) 20-14 pulse accumulator counter (gptpacnt) 20-16 pulse accumulator flag (gptpaflg) 20-15 system control 1?2 (gptscr n )20-8 , 20-11 toggle-on-overflow (gpttov) 20-9 reset 20-21 gpio block diagram 26-2 , 26-3 electrical characteristics timing 33-18 features 26-4 initialization 26-28 memory map 26-7 operation 26-4 low-power modes 7-9 overview 26-1 , 26-4 registers port as pin assignment (paspar) 26-21 port b/c/d pin assignment (pbcdpar) 26-16 port clear output data (clr n ) 26-14 port data direction (ddr n ) 26-11 port e pin assignment (pepar) 26-17 port eh/el pin assignment (pehlpar) 26-22 port f pin assignment (pfpar) 26-19 port j pin assignment (pjpar) 26-20 port output data (port n )26-10 port pin data/set data (port n p/set n )26-13 port qs pin assignment (pqspar) 26-23 port sd pin assignment (psdpar) 26-21 port tc pin assignment (ptcpar) 26-24 port td pin assignment (ptdpar) 26-25 port ua pin assignment (puapar) 26-26 timing diagrams 33-19 digital input 26-28 digital output 26-28 h halt, fault-on-fault 30-17 highz instruction 31-8 i i 2 c arbitration procedure 24-11 clock arbitration 24-11 stretching 24-12 synchronization 24-11 electrical characteristics input timing between scl and sda 33-20 output timing between scl and sda 33-20 handshaking 24-12 memory map 24-3 operation 24-7 low-power modes 7-8 programming examples initialization 24-12 repeated start generation 24-14 start generation 24-12 stop generation 24-13 registers address (i2adr) 24-3 control (i2cr) 24-4 data i/o (i2dr) 24-6 frequency divider (i2fdr) 24-3 status (i2sr) 24-5 slave mode 24-14 timing diagrams input/output timing 33-21 idcode instruction 31-7 identifier (id) bits 25-7 idle bit 25-27 information processing time (ipt) 25-13 input capture 20-17 instructions additions 2-14 execution timing miscellaneous 2-30 one-operand 2-28 two-operand 2-28 jtag bypass 31-9 clamp 31-9 enable_test_ctrl 31-8 extest 31-7 highz 31-8 idcode 31-7 lockout_recovery 31-8 sample/preload 31-7 test_leakage 31-8 rte 2-21 intermission 25-12 interrupt controller mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor index-7 interrupts coldfire flash module 6-23 debug 2-21 , 30-37 flexcan 25-17 overview 10-1 pit 19-7 prioritization 10-4 qadc operation 28-68 sources 28-68 recognition 10-3 sources 10-13 vector determination 10-4 memory map 10-4 operation general 10-2 low-power modes 7-9 registers (iacklpr n ) 10-11 interrupt control (icr nx ) 10-12 interrupt force high/low (intfrch n, intfrcl n ) 10-9 interrupt pending high/low (iprh n , iprl n ) 10-6 interrupt request level (irlr n )10-11 mask high/low (imrh n , n) 10-7 j jtag block diagram 31-1 electrical characteristics boundary scan timing 33-25 features 31-2 initialization 31-9 nonscan chain operation 31-9 restrictions 31-9 instructions bypass 31-9 clamp 31-9 enable_test_ctrl 31-8 extest 31-7 highz 31-8 idcode 31-7 lockout_recovery 31-8 sample/preload 31-7 test_leakage 31-8 low-power modes 7-13 memory map 31-4 overview 31-1 registers boundary scan 31-5 bypass 31-5 idcode 31-4 instruction shift (ir) 31-4 jtag_cfm_clkdiv 31-5 test_ctrl 31-5 tap controller 31-6 timing diagrams bkpt timing 33-27 boundary scan 33-26 test access port 33-26 test clock input 33-26 trst timing 33-27 l listen-only mode 25-12 lockout_recovery instruction 31-8 lowest buffer transmitted first (lbuf) 25-21 low-power modes doze 7-6 peripheral behavior chip configuration module 7-9 chip select module 7-7 clock module 7-10 coldfire flash module 7-7 , 7-13 core 7-6 debug 7-13 dma controller 7-7 dma timers 7-8 eport 7-10 ethernet 7-9 flexcan 7-11 general purpose timers 7-11 gpio 7-9 i 2 c7-8 interrupt controller 7-9 jtag 7-13 modules 7-8 programmable interrupt timers 7-10 qadc 7-11 qspi 7-8 reset controller 7-9 scm 7-7 sdram controller 7-7 sram 7-6 watchdog timer 7-10 run 7-5 stop 7-6 summary 7-13 wait 7-6 m mapga package 32-9 memory map chip configuration module 27-3 clock module 9-5 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 index-8 freescale semiconductor coldfire flash module 6-4 , 6-7 emac 3-3 eport 11-3 flexcan 25-2 general purpose timers 20-4 gpio 26-7 i 2 c 24-3 interrupt controller 10-4 jtag 31-4 pit 19-2 power management 7-2 qadc 28-6 qspi 22-3 reset controller 29-2 scm 8-2 , 8-12 sdram controller 15-4 uart modules 23-3 watchdog timer 18-2 message buffers extended format frames 25-5 , 25-7 handling 25-10 overload frames 25-12 receive codes 25-6 deactivation 25-10 error status flag (rxwarn) 25-27 pin configuration control (rxmode) 25-20 remote frames 25-11 self-received frames 25-10 standard format frames 25-5 , 25-7 structure 25-4 time stamp 25-12 transmit codes 25-6 deactivation 25-10 error status flag (txwarn) 25-26 pin configuration control (txmode) 25-20 message format error (formerr) bit 25-26 mii serial management channel timing 33-23 transmit signal timing 33-22 o ordering information 32-9 output compare 20-18 overload frames 25-12 p phase buffer segment 1, 2 (pseg n ) bits 25-23 pinout 32-1 pll charge pump/loop filter 9-12 , 9-13 electrical specifications 33-4 lock detection 9-13 loss-of-clock alternate clock selection 9-15 detection 9-15 reset 9-15 stop mode 9-16 loss-of-lock conditions 9-14 reset 9-15 multiplication factor divider (mfd) 9-13 operation 9-11 1-1 mode 9-1 normal mode 9-1 phase and frequency detector (pfd) 9-12 voltage control output (vco) 9-13 power management features 7-1 low-power modes 7-5 doze 7-6 peripheral behavior chip configuration module 7-9 chip select module 7-7 clock module 7-10 coldfire flash module 7-7 , 7-13 core 7-6 debug 7-13 dma controller 7-7 dma timers 7-8 eport 7-10 ethernet 7-9 flexcan 7-11 general purpose timers 7-11 gpio 7-9 i 2 c7-8 interrupt controller 7-9 jtag 7-13 programmable interrupt timers 7-10 qadc 7-11 qspi 7-8 reset controller 7-9 scm 7-7 sdram controller 7-7 sram 7-6 uart modules 7-8 watchdog timer 7-10 run 7-5 stop 7-6 summary 7-13 wait 7-6 memory map 7-2 programming model 7-1 registers mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor index-9 low-power control (lpcr) 7-4 low-power interrupt control (lpicr) 7-2 prescaler divide (presdiv) bits 25-22 processor status 30-2 , 30-39 program counter 2-7 programmable interrupt timers operation low-power modes 7-10 programming model chip configuration module 27-3 debug 30-5 eport 7-1 power management 7-1 pulse accumulator event counter mode 20-18 gated time accumulation 20-19 input interrupt 20-22 overflow interrupt 20-22 pulse instruction 30-3 q qadc a/d converter bias 28-34 block diagram 28-32 channel decode 28-33 comparator 28-33 cycle times 28-32 multiplexer 28-33 operation 28-31 sample buffer 28-33 state machine 28-34 analog inputs 28-66 analog subsystem 28-31 analog supply filtering 28-61 grounding 28-61 block diagram 28-2 boundary conditions 28-45 digital control subsystem 28-34 electrical characteristics absolute maximum ratings 33-8 operating conversion specifications 33-10 operating electrical specifications 33-9 external multiplexing 28-29 operation 28-29 options 28-31 features 28-1 interrupts operation 28-68 sources 28-68 leakage 28-67 memory map 28-6 operation continuous-scan 28-49 externally gated 28-51 externally triggered 28-50 periodic timer 28-51 software-initiated 28-50 debug mode 28-2 disabled 28-47 low-power modes 7-11 reserved 28-47 single-scan 28-47 externally gated 28-48 externally triggered 28-48 interval timer 28-49 software-initiated 28-48 stop mode 28-3 overview 28-1 periodic/interval timer 28-52 qclk generation 28-52 queue priority 28-34 , 28-36 registers control 2?0 (qacr n )28-10 ? 28-14 conversion command word (ccw) 28-24 , 28-53 left-justified signed result (ljsrr) 28-27 left-justified unsigned result (ljurr) 28-28 module configuration (qadcmcr) 28-7 port data (portqa and portqb) 28-8 port qa and qb data direction (ddrqa, ddrqb) 28-9 result word table 28-55 right-justified unsigned result (rjurr) 28-27 status 0?1 (qasr n )28-17 , 28-23 successive approximation (sar) 28-34 test (qadctest) 28-8 result coherency 28-28 stress conditions 28-62 timing diagrams conversion in gated mode, continuous scan 28-60 conversion in gated mode, single scan 28-60 conversion timing 28-33 conversion timing, bypass mode 28-33 qspi baud rate 22-12 electrical characteristics ac timing specifications 33-24 memory map 22-3 operation low-power modes 7-8 master mode 22-2 programming example 22-15 ram command 22-12 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 index-10 freescale semiconductor model 22-11 receive 22-11 transmit 22-12 registers address (qar) 22-7 command ram (qcr n )22-8 data (qdr) 22-8 delay (qdlyr) 22-5 interrupt (qir) 22-6 mode (qmr) 22-3 wrap (qwr) 22-6 rx ram 22-11 signals 22-2 timing diagram 33-25 tx delays 22-13 length 22-14 ram 22-12 r registers cache access control 0?1 (acr n )2-7 , 4-6 control (cacr) 2-7 , 4-3 chip configuration module chip configur ation (ccr) 27-4 chip identification (cir) 27-6 reset configuration (rcon) 27-5 chip select module address (csar n ) 12-6 control (cscr n ) 12-7 mask (csmr n )12-6 clock module synthesizer control (syncr) 9-6 synthesizer status (synsr) 9-8 coldfire flash module clock divider (cfmclkd) 6-9 command (cfmcmd) 6-16 configuration (cfmcr) 6-8 data access (cfmdacc) 6-14 flashbar 6-5 protection (cfmprot) 6-12 security (cfmsec) 6-10 supervisor access (cfmsacc) 6-13 user status (cfmustat) 6-15 core address (a n )2-4 condition code (ccr) 2-6 data (d n )2-4 program counter (pc) 2-7 stack pointer (a7) 2-5 status register (sr) 2-8 vector base (vbr) 2-7 debug address attribute trigger (aatr) 30-7 address breakpoint (ablr, abhr) 30-9 configuration/status (csr) 30-10 data breakpoint/mask (dbr, dbmr) 30-12 program counter breakpoint/mask (pbr/pbmr) 30-13 trigger definition (tdr) 30-14 dma controller byte count (bcr n ) 16-7 control (dcr n )16-7 destination address (dar n ) 16-6 request control (dmareqc) 16-2 source address (sar n ) 16-5 status (dsr n) 16-10 emac mask (mask) 3-5 status (macsr) 3-3 eport data direction (epddr) 11-4 flag (epfr) 11-6 pin assignment (eppar) 11-3 pin data (eppdr) 11-6 port data (epdr) 11-5 port interrupt enable (epier) 11-5 ethernet control (ecr) 17-12 descriptor group upper/lower address (gaur/galr) 17-21 descriptor individual upper/lower (iaur/ialr) 17-20 descriptor individual upper/lower address (iaur/ialr) 17-20 fifo receive bound (frbr) 17-22 fifo receive start (frsr) 17-23 fifo transmit fifo watermark (tfwr) 17-22 interrupt event (eir) 17-9 interrupt mask (eimr) 17-10 mib control (mibc) 17-16 mii management frame (mmfr) 17-13 mii speed control (mscr) 17-15 opcode/pause duration (opd) 17-19 physical address low (palr n ) 17-18 physical address low/high (palr, paur) 17-18 receive buffer size (emrbr) 17-24 receive control (rcr) 17-16 receive descriptor active (rdar) 17-11 receive descriptor ri ng start (erdsr) 17-23 transmit buffer descriptor ring start (etsdr) 17-24 transmit control (tcr) 17-17 transmit descriptor active (tdar) 17-12 flexcan control 0?2 (canctrl n ) 25-20 ? 25-22 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor index-11 error and status (estat) 25-25 free running timer (timer) 25-23 interrupt flag (iflag) 25-28 interrupt mask (imask) 25-27 module configuration (canmcr) 25-18 prescaler divide (presdiv) 25-22 receive error coun ter (rxectr) 25-29 receive mask (rxgmask, rx n mask) 25-24 transmit error counter (txectr) 25-30 general purpose timers channel (gptc n )20-13 compare force (gpcforc) 20-6 control 1?2 (gptctl n ) 20-9 counter (gptcnt) 20-7 flag 1?2 (gptflgn) 20-12 input capture/output compare select (gptios) 20-5 interrupt enable (gptie) 20-10 output compare 3 data (gptoc3d) 20-7 output compare 3 mask (gptoc3m) 20-6 port data (portt n ) 20-16 port data direction (gptddr) 20-17 pulse accumulator control (gptpactl) 20-14 pulse accumulator counter (gptpacnt) 20-16 pulse accumulator flag (gptpaflg) 20-15 system control 1?2 (gptscr n )20-8 , 20-11 toggle-on-overflow (gpttov) 20-9 gpio port as pin assignment (paspar) 26-21 port b/c/d pin assignment (pbcdpar) 26-16 port clear output data (clr n ) 26-14 port data direction (ddr n ) 26-11 port e pin assignment (pepar) 26-17 port eh/el pin assignment (pehlpar) 26-22 port f pin assignment (pfpar) 26-19 port j pin assignment (pjpar) 26-20 port output data (port n )26-10 port pin data/set data (port n p/set n )26-13 port qs pin assignment (pqspar) 26-23 port sd pin assignment (psdpar) 26-21 port tc pin assignment (ptcpar) 26-24 port td pin assignment (ptdpar) 26-25 port ua pin assignment (puapar) 26-26 i 2 c address (i2adr) 24-3 control (i2cr) 24-4 data i/o (i2dr) 24-6 frequency divider (i2fdr) 24-3 status (i2sr) 24-5 interrupt controller interrupt acknowledge level and priority (iacklpr n ) 10-11 interrupt control (icr nx ) 10-12 interrupt force high/low (intfrch n, intfrcl n ) 10-9 interrupt pending high/low (iprh n, iprl n ) 10-6 interrupt request level (irlr n )10-11 mask high/low (imrh n , n) 10-7 jtag boundary scan 31-5 bypass 31-5 idcode 31-4 instruction shift (ir) 31-4 jtag_cfm_clkdiv 31-5 test_ctrl 31-5 power management low-power control (lpcr) 7-4 low-power interrupt control (lpicr) 7-2 qadc control 2?0 (qacr n )28-10 ? 28-14 conversion command word (ccw) 28-24 , 28-53 left-justified signed (ljsrr) 28-27 left-justified unsigned (ljurr) 28-28 module configuration (qadcmcr) 28-7 port data (portqa and portqb) 28-8 port qa and qb data direction (ddrqa, ddrqb) 28-9 result word table 28-55 right-justified unsigned result (rjurr) 28-27 status 0?1 (qasr n )28-17 , 28-23 successive approximation (sar) 28-34 test (qadctest) 28-8 qspi address (qar) 22-7 command ram (qcr n ) 22-8 data (qdr) 22-8 delay (qdlyr) 22-5 interrupt (qir) 22-6 mode (qmr) 22-3 wrap (qwr) 22-6 reset controller control (rcr) 29-3 status (rsr) 29-4 scm bus master park (mpark) 8-9 core reset status (crsr) 8-5 core watchdog control (cwcr) 8-5 core watchdog service (cwsr) 8-7 grouped peripheral access control (gpacr n )8-15 ipsbar 8-2 master privilege (mpr) 8-13 peripheral access control (pacr n )8-13 rambar 5-1 , 8-3 sdram controller address and control 1?0 (dacr n ) 15-6 control (dcr) 15-4 mask (dmr n ) 15-8 mode register mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 index-12 freescale semiconductor initialization 15-23 settings 15-18 timers dtim capture (dtcr n ) 21-7 counters (dtcn n )21-8 event (dter n )21-5 mode (dtmr n ) 21-3 reference (dtrr n )21-7 pit control and status (pcsr) 19-3 count (pcntr) 19-5 modulus (pmr) 19-5 uart modules auxiliary control (uacr n )23-13 baud rate generator (ubg1 n /ubg2 n ) 23-15 clock select (ucsrn ) 23-9 command (ucr n )23-9 input port (uip n )23-15 input port change (uipcr n )23-12 interrupt status/mask (uisr n /uimr n )23-13 mode 1 (umr1 n ) 23-5 mode 2 (umr n )23-6 output port command (uop1 n /uop0n ) 23-16 receive buffers (urb n )23-11 status (usr n )23-8 transmit buffers (utb n ) 23-12 watchdog timer control (wcr) 18-3 count (wcntr) 18-5 modulus (wmr) 18-4 service (wsr) 18-5 remote frames 25-11 reset controller block diagram 29-1 control flow 29-7 electrical characteristics reset and configuration override timing 33-19 features 29-1 low-power modes 7-9 memory map 29-2 overview 29-1 registers control (rcr) 29-3 status (rsr) 29-4 requests internal 29-9 synchronous 29-9 sources of reset 29-5 external reset 29-6 ldv reset 29-6 loss-of-clock reset 29-6 loss-of-lock reset 29-6 power-on reset 29-6 software reset 29-6 watchdog timer reset 29-6 status flags 29-10 timing diagrams rsti and configuration override 33-20 run mode 7-5 rx/tx frames 25-6 s sacu features 8-12 overview 8-11 sample/preload instructions 31-7 sampling mode (samp) 25-21 s-clock 25-12 scm features 8-1 low-power modes 7-7 memory map 8-2 , 8-12 overview 8-1 registers bus master park (mpark) 8-9 core reset status (crsr) 8-5 core watchdog control (cwcr) 8-5 core watchdog service (cwsr) 8-7 grouped peripheral access control (gpacr n )8-15 ipsbar 8-2 master privilege (mpr) 8-13 peripheral access control (pacr n )8-13 rambar 5-1 , 8-3 sacu 8-11 features 8-12 overview 8-11 sdram controller auto-refresh 15-15 block diagram 15-1 burst page mode 15-13 definitions 15-1 example dacr initialization 15-20 dcr initialization 15-20 dmr initialization 15-22 initialization code 15-23 interface confi guration 15-20 initialization 15-17 interfacing 15-13 memory map 15-4 operation general 15-3 low-power modes 7-7 synchronous mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor index-13 address multiplexing 15-9 general guidelines 15-9 overview 15-1 registers address and control 1?0 (dacr n )15-6 control (dcr) 15-4 mask (dmr n ) 15-8 mode register initialization 15-23 settings 15-18 self-refresh 15-16 timing diagrams read cycle 33-17 write cycle 33-18 timing specifications 33-17 self-received frames 25-10 signals block diagram 14-2 bus address bus (a23?0) 14-19 byte strobes (bs 3?0) 14-19 chip select (cs 6?0) 14-21 data (d31?0) 14-19 output enable (oe ) 14-19 read/write (r/w )14-20 summary 13-1 transfer acknowledge (ta )14-19 transfer error acknowledge (tea ) 14-20 transfer in progress (tip ) 14-21 transfer size (siz1?0) 14-20 transfer start (ts )14-20 chip configuration clkmod1?0 9-5 chip configuration module clkmod1?0 14-22 , 27-2 rcon 14-22 , 27-2 reset configuration override (d26?24, 21, 19?16) 27-3 chip select module byte strobes (bs 3?0) 12-1 chip select (cs 6?0) 12-1 output enable (oe ) 12-1 clock module clkmod1?0 9-5 clock output (clkout) 9-5 , 14-22 extal 9-4 , 14-22 rstout l9-5 xtal 9-5 , 14-22 debug breakpoint (bkpt ) 30-2 breakpoint/test mode select (bkpt /tms) 14-30 clkout 30-2 debug data (ddata3?0) 14-31 , 30-2 development serial clock (dsclk) 30-2 development serial clock/test reset (dsclk/trst ) 14-30 development serial input (dsi) 30-2 development serial input/test data (dsi/tdi) 14-30 development serial output (dso) 30-2 development serial output/test data (dso/tdo) 14-30 jtag_en 14-29 processor status (pst3?0) 30-2 processor status output (pst3?0) 14-31 test clock (tclk) 14-30 description by pin 32-4 dma timers timer 0 input (dtin0) 14-27 timer 0 output (dtout0) 14-27 timer 1 input (dtin1) 14-27 timer 1 output (dtout1) 14-28 timer 2 input (dtin2) 14-28 timer 2 output (dtout2) 14-28 timer 3 input (dtin3) 14-28 timer 3 output (dtout3) 14-28 ethernet carrier receive sense (ecrs) 14-24 collision (ecol) 14-24 management data (emdio) 14-23 management data clock (emdc) 14-23 receive clock (erxclk) 14-24 receive data 0 (erxdo) 14-24 receive data 3?1 (erxd3?1) 14-24 receive data valid (erxdv) 14-24 receive error (erxer) 14-25 transmit clock (extclk) 14-23 transmit data 0 (etxd0) 14-23 transmit data 1?3 (etxd3?1) 14-24 transmit enable (etxen) 14-23 transmit error (etxer) 14-24 external boot mode 14-18 flexcan receive (canrx) 14-25 transmit (cantx) 14-25 general purpose timers external clock input (sync x ) 14-27 , 20-4 gptb3?0 14-27 gpt n 2?0 20-3 gpt n 320-3 gpt x 3?0 14-27 i 2 c serial clock (scl) 14-26 serial data (sda) 14-26 interrupts irq 7?1 14-23 jtag jtag_en 31-2 tclk 31-3 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 index-14 freescale semiconductor test data input/development serial input (tdi/dsi) 31-3 test data output/development serial output (tdo/dso) 31-4 test mode select/breakpoint (tms/bkpt ) 31-3 test reset/development serial clock (trst /dsclk) 31-3 overview 14-1 power and reference v dd 14-32 v dda , v ssa 14-32 v ddf , v ssf 14-32 v ddh 14-32 v ddpll , v sspll 14-32 v pp 14-32 v rh , vrl 14-32 v ss 14-32 v stby 14-32 qadc analog input (an n /an x ) 14-28 ? 14-29 analog power (v dda , v ssa) 28-56 analog reference (v rh , v rl ) 28-56 dedicated digital i/o port supply (v ddh ) 28-6 external trigger input (etrig2?1) 28-5 multiplexed address output (ma1?0) 28-5 multiplexed analog input (an x ) 28-5 port qa analog input (an56?55, 53?52) 28-4 port qa digital input/output (pqa4?3, 1?0) 28-4 port qb analog input (an3?0) 28-4 port qb digital i/o (pqb3?0) 28-5 qspi chip select (qspi_cs3?0) 14-25 serial clock (qspi_clk) 14-25 summary 22-2 synchronous serial data input (qspi_din) 14-25 synchronous serial data output (qspi_dout) 14-25 reset controller reset in (rsti )14-22 , 29-2 reset out (rsto )29-2 sdram controller bank select (sdram_cs 1?0) 14-21 clock enable (scke) 14-22 column address strobe (scas ) 14-21 row address strobe (sras )14-21 summary 15-4 write enable (dramw )14-21 single-chip mode 14-17 test 14-31 uart modules clear-to-send (ucts 1?0) 14-26 receive serial data input (urxd2?0) 14-26 request-to-send (urts 1?0) 14-27 transmit serial data output (utxd2?0) 14-26 sram cache, interaction 4-7 features 5-1 initialization 5-3 operation low-power modes 7-6 overview 5-1 power management 5-4 programming model 5-1 timing diagrams bus cycle terminated by ta 33-15 bus cycle terminated by tea 33-16 stack pointer 2-5 stack pointer registers bdm accesses 30-33 start-of-frame (sof) 25-13 stop instruction 30-4 , 30-17 stop mode 7-6 stufferr 25-26 system clock generation 9-11 modes 9-10 t tap controller 31-6 test_leakage 31-8 time quanta clock 25-12 time stamp 25-6 , 25-12 timer overflow interrupt 20-22 timers dtim capture mode 21-8 code example 21-9 operation general 21-9 output mode 21-9 prescaler 21-8 reference compare 21-8 registers capture (dtcr n )21-7 counters (dtcn n ) 21-8 event (dter n ) 21-5 mode (dtmr n )21-3 reference (dtrr n ) 21-7 time-out values 21-10 general purpose, see general purpose timers pit block diagram 19-1 interrupts 19-7 memory map 19-2 operation free-running 19-6 low-power modes 19-1 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 freescale semiconductor index-15 set-and-forget 19-6 registers control and status (pcsr) 19-3 count (pcntr) 19-5 modulus (pmr) 19-5 timeout 19-7 watchdog, see watchdog timer 18-2 timing diagrams debug bdm serial port ac timing 33-28 real-time trace ac timing 33-28 ethernet mii async input signal 33-23 general input timing requirements 33-12 gpio 33-19 digital input 26-28 digital output 26-28 i 2 c input/output timing 33-21 jtag bkpt timing 33-27 boundary scan 33-26 test access port 33-26 test clock input timing 33-26 trst timing 33-27 qadc bypass mode conversion timing 28-33 conversion in external positive edge trigger mode 28-59 conversion in gated mode, continuous scan 28-60 conversion in gated mode, single scan 28-60 conversion timing 28-33 qspi timing 33-25 reset controller rsti and configuration override timing 33-20 sdram controller read cycle 33-17 write cycle 33-18 sram bus cycle terminated by ta 33-15 bus cycle terminated by tea 33-16 transmit bit error (biterr) 25-26 u uart modules clock select registers (ucsr n ) 23-9 clock source baud rates 23-17 divider 23-17 external 23-18 command registers (ucrn )23-9 core interrupts 23-26 dma service 23-27 fifo stack 23-21 initialization 23-29 input port change (uipcr n )23-12 memory map 23-3 operation looping modes automatic echo 23-23 local loop-back 23-23 remote loop-back 23-23 low-power modes 7-8 multidrop mode 23-24 receiver 23-20 transmitter 23-18 registers auxiliary control (uacr n )23-13 baud rate generator (ubg1n/ubg2n) 23-15 input port (uip n ) 23-15 interrupt status/mask (uisr n /uimrn ) 23-13 mode 1 (umr1 n ) 23-5 mode 2 (umr2 n ) 23-6 output port command (uop1 n/uop0 n ) 23-16 receive buffers (urb n ) 23-11 status (usr n ) 23-8 transmit buffers (utb n )23-12 v variant address 30-4 w wait mode 7-6 wake interrupt (wakeint) 25-16 , 25-27 watchdog timer block diagram 18-2 memory map 18-2 operation low-power 7-10 , 18-1 overview 18-1 registers control (wcr) 18-3 count (wcntr) 18-5 modulus (wmr) 18-4 service (wsr) 18-5 wddata execution 30-3 mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 index-16 freescale semiconductor mcf5282 and mcf5216 coldfire microcontroller users manual, rev. 3 overview coldfire core enhanced multiply-acc umulate unit (emac) cache static ram (sram) coldfire flash module (cfm) power management system control module (scm) clock module interrupt controller modules edge port module (eport) chip select module external interface module (eim) synchronous dram controller module dma controller module fast ethernet controller (fec) watchdog timer module programmable interrupt timer (pit) modules general purpose timer (gpt) modules flexcan module general purpose i/o module i 2 c module 3 4 5 7 8 9 10 11 12 13 15 16 17 18 19 24 6 20 25 26 21 23 22 dma timers queued serial peripheral interface module (qspi) uart modules 1 2 27 28 29 30 31 32 33 a chip configuration module (ccm) queued analog-to-digital converter (qadc) reset controller module debug support ieee 1149.1 test access port (jtag) mechanical data electrical characteristics memory map b revision history signal descriptions 14 ind index overview coldfire core enhanced multiply-accumulate unit (emac) cache static ram (sram) coldfire flash module (cfm) power management system control module (scm) clock module interrupt controller modules edge port module (eport) chip select module external interface module (eim) signal descriptions synchronous dram controller module dma controller module fast ethernet controller (fec) watchdog timer module programmable interrupt timer (pit) modules general purpose timer (gpt) modules flexcan module general purpose i/o module i 2 c module 3 4 5 7 8 9 10 11 12 13 14 15 16 17 18 19 24 6 20 25 26 21 23 22 dma timers queued serial peripheral interface module (qspi) uart modules 1 2 27 28 29 30 31 32 33 a chip configuration module (ccm) queued analog-to-digi tal converter (qadc) reset controller module debug support ieee 1149.1 test access port (jtag) mechanical data electrical characteristics memory map b revision history ind index |
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